Burst Buffer Controller 2 Module
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
4-3
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Implements a parked master on the U-bus, resulting in zero clock delays for RCPU fetch accesses
to the U-bus
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Fully utilizes the U-bus pipeline for fetch accesses
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Avoids undesirable delays through a tight interface with the L2U module (fully utilizing U-bus
bandwidth and back-to-back accesses)
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Supports program trace and show cycles
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Supports a special attribute for debug port fetch accesses.
4.1.2
IMPU Key Features
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There are four regions in which the base address and size can be programmed.
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Available region sizes include 2 Kbytes, 8 Kbytes, 16 Kbytes, 32 Kbytes, 64 Kbytes, 128 Kbytes,
256 Kbytes, 512 Kbytes, 1 Mbyte, 2 Mbytes, 4 Mbytes, 8 Mbytes, 16 Mbytes....4 Gbytes.
•
Overlap between regions is allowed.
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Each of the four regions supports the following attributes:
— User/supervisor
— Guard attribute (causes an interrupt in case of speculative fetch attempt)
— Compressed/non-compressed (MPC562/MPC564 only)
— Regions are enabled or disabled in software.
•
Global region entry declares the default access attributes for all memory areas not covered by the
four regions:
•
The RCPU gets the instruction storage protection exception generated upon
— An access violation of protection attributes
— A fetch from a guarded region.
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The RCPU MSR[IR] bit controls IMPU protection.
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Programming is performed by using the RCPU mtspr/mfspr instructions to/from implementation
specific special-purpose registers.
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The IMPU supplies relocation addresses of all the exceptions within the internal memory space.
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The IMPU implements external interrupt vector splitting to reduce the external interrupt latency.
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There is a special reset exception vector for decompression on mode (MPC562/MPC564 only).
4.1.3
ICDU Key Features
The following are instruction code decompression unit key features of the MPC562/MPC564. See
Appendix A, “MPC562/MPC564 Compression Features
” for more information.
•
Instruction code on-line decompression based on “instruction classes” algorithm.
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No need for address translation between compressed and non-compressed address spaces — ICDU
provides “next instruction address” to the RCPU
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In most cases, instruction decompression takes one clock
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Code decompression is pipelined:
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
