Development Support
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
23-39
The assertion and negation of the freeze signal when in debug mode disable is controlled by the exception
cause register (ECR) and the debug enable register (DER) as described in
. In order to assert
the freeze signal the software needs to program the relevant bits in the debug enable register (DER). In
order to negate the freeze line the software needs to read the exception cause register (ECR) in order to
clear it and perform an rfi instruction.
If the exception cause register (ECR) is not cleared before the rfi is performed the freeze signal is not
negated. Therefore it is possible to nest inside a software monitor debugger without affecting the value of
the freeze line although rfi may be performed a few times. Only before the last rfi the software needs to
clear the exception cause register (ECR).
The above mechanism enables the software to accurately control the assertion and the negation of the
freeze signal.
23.6
Development Support Registers
lists the registers used for development support in SPR number order, and the register
sections,
Section 23.6.2, “Comparator A–D Value Registers (CMPA–CMPD)
” through
“Development Port Data Register (DPDR)
,” follow the same SPR order. The registers are accessed with
the mtspr and mfspr instructions.
Table 23-14. Development Support Programming Model
SPR Number
(Decimal)
Name
144
Comparator A Value Register (CMPA)
See
for bit descriptions.
145
Comparator B Value Register (CMPB)
See
for bit descriptions.
146
Comparator C Value Register (CMPC)
See
for bit descriptions.
147
Comparator D Value Register (CMPD)
See
for bit descriptions.
148
Exception Cause Register (ECR)
See
for bit descriptions.
149
Debug Enable Register (DER)
See
for bit descriptions.
150
Breakpoint Counter A Value and Control Register (COUNTA)
See
for bit descriptions.
151
Breakpoint Counter B Value and Control Register (COUNTB)
See
for bit descriptions.
152
Comparator E Value Register (CMPE)
See
for bit descriptions.
153
Comparator F Value Register (CMPF)
See
for bit descriptions.
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
