IBM Power 595 Technical Overview And Introduction Download

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Chapter 2. Architectural and technical overview

Examples are discussed in the following list:

Java applications: Applications running IBM Technology for Java 6.0 32-bit and 64-bit JVM
automatically take advantage of the hardware assist during the initial just in time (JIT)
processing. Applications running under IBM i require release level 6.1. Java 5.0 does not
use DCP.

C and C++ applications: For the C and C++ compilers running under AIX and Linux for
Power, as of v9.0, DFP support through the POWER6 hardware instructions is available.
Software emulation is supported on all other POWER architectures.

Running under IBM i 6.1, support for DFP has been added to the IBM i 6.1 ILE C compiler.
If a C program that uses DFP data is compiled on POWER 6 hardware, hardware DFP
instructions is generated; otherwise, software emulation is used.

IBM i support for DFP in the ILE C++ compiler is planned for a future release.

For your information, C and C++ on z/OS®, as of V1R9, use hardware DFP support where
the run time code detects hardware analogous to POWER 6.

IBM i ILE RPG and COBOL: These languages do not use decimal floating point. The
normal zoned decimal or packed decimal instructions receive

normal

performance gains

merely by running under IBM i 6.1 on POWER6.

IBM i 6.1 supports decimal floating point data, for example, in DB2 for i5/OS tables. If the
RPG or COBOL compiler encounters a decimal float variable in an externally-described
file or data structure, it will ignore the variable and issue an identifying information
message.

Some applications, such those available from SAP®, that run on POWER6-based
systems, can provide specific ways to take advantage of decimal floating point.

For example, the SAP NetWeaver® 7.10 ABAP™ kernel introduces a new SAP ABAP
data type called

DECFLOAT

to enable more accurate and consistent results from decimal

floating point computations. The decimal floating point (DFP) support by SAP NetWeaver
leverages the built-in DFP feature of POWER6 processors. This allows for simplified
ABAP-coding while increasing numeric accuracy and with a potential for significant
performance improvements.

2.6.3 AltiVec and Single Instruction, Multiple Data

IBM semiconductor’s advanced Single Instruction, Multiple Data (SIMD) technology based on
the AltiVec instruction set is designed to enable exceptional general-purpose processing
power for high-performance POWER processors. This leading-edge technology is engineered
to support high-bandwidth data processing and algorithmic-intensive computations, all in a
single-chip solution

With its computing power, AltiVec technology also enables high-performance POWER
processors to address markets and applications in which performance must be balanced with
power consumption, system cost and peripheral integration.

The AltiVec technology is a well known environment for software developers who want to add
efficiency and speed to their applications. A 128-bit vector execution unit was added to the
architecture. This engine operates concurrently with the existing integer and floating-point
units and enables highly parallel operations, up to 16 operations in a single clock cycle. By
leveraging AltiVec technology, developers can optimize applications to deliver acceleration in
performance-driven, high-bandwidth computing.

The AltiVec technology is not comparable to the IBM POWER6 processor implementation,
using the simultaneous multithreading functionality.