104
January, 2004
Developer’s Manual
Intel XScale® Core
Developer’s Manual
Performance Monitoring
Table 8-4.
Performance Monitor Control Register (CP14, register 0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
evtCount1
evtCount0
flag
inten
D C P E
reset value:
E
and
inten
are 0, others unpredictable
Bits
Access
Description
31:28
Read-unpredictable / Write-as-0
Reserved
27:20
Read / Write
Event Count1
- identifies the source of events that
PMN1 counts. See
Table 8-12
for a description of the
values this field may contain.
19:12
Read / Write
Event Count0
- identifies the source of events that
PMN0 counts. See
Table 8-12
for a description of the
values this field may contain.
11
Read-unpredictable / Write-as-0
Reserved
10:8
Read / Write
Overflow/Interrupt Flag
- identifies which counter
overflowed
Bit 10 = clock counter overflow flag
Bit 9 = performance counter 1 overflow flag
Bit 8 = performance counter 0 overflow flag
Read Values:
0 = no overflow
1 = overflow has occurred
Write Values:
0 = no change
1 = clear this bit
7
Read-unpredictable / Write-as-0
Reserved
6:4
Read / Write
Interrupt Enable
- used to enable/disable interrupt
reporting for each counter
Bit 6 = clock counter interrupt enable
0 = disable interrupt
1 = enable interrupt
Bit 5 = performance counter 1 interrupt enable
0 = disable interrupt
1 = enable interrupt
Bit 4 = performance counter 0 interrupt enable
0 = disable interrupt
1 = enable interrupt
3
Read / Write
Clock Counter Divider (D)
-
0 = CCNT counts every processor clock cycle
1 = CCNT counts every 64
th
processor clock cycle
2
Read-unpredictable / Write
Clock Counter Reset (C)
-
0 = no action
1 = reset the clock counter to ‘0x0’
1
Read-unpredictable / Write
Performance Counter Reset (P)
-
0 = no action
1 = reset both performance counters to ‘0x0’
0
Read / Write
Enable (E)
-
0 = all 3 counters are disabled
1 = all 3 counters are enabled