38
January, 2004
Developer’s Manual
Intel XScale® Core
Developer’s Manual
Memory Management
3.2
Architecture Model
3.2.1
Version 4 vs. Version 5
ARM* MMU Version 5 Architecture introduces the support of tiny pages, which are 1 KByte in
size. The reserved field in the first-level descriptor (encoding 0b11) is used as the fine page table
base address. The exact bit fields and the format of the first and second-level descriptors can be
found in
Section 2.3.2, “New Page Attributes” on page 2-29
.
3.2.2
Memory Attributes
The attributes associated with a particular region of memory are configured in the memory
management page table and control the behavior of accesses to the instruction cache, data cache,
mini-data cache and the write buffer. These attributes are ignored when the MMU is disabled.
To allow compatibility with older system software, the new core attributes take advantage of
encoding space in the descriptors that was formerly reserved.
3.2.2.1
Page (P) Attribute Bit
The P bit allows an ASSP to assign its own page attribute to a memory region. This bit is only
present in the first level descriptors. Refer to the Intel XScale
®
core implementation section of the
ASSP architecture specification to find out how this has been defined. Accesses to memory for
page table walks do not use the MMU. The core provides ASSP definable memory attributes for
these accesses in the Auxiliary Control Register. See
Table 7-7, “Auxiliary Control Register” on
page 7-84
.
3.2.2.2
Cacheable (C), Bufferable (B), and eXtension (X) Bits
3.2.2.3
Instruction Cache
When examining these bits in a descriptor, the Instruction Cache only utilizes the C bit. If the C bit is
clear, the Instruction Cache considers a code fetch from that memory to be non-cacheable, and will not
fill a cache entry. If the C bit is set, then fetches from the associated memory region will be cached.