Developer’s Manual
January, 2004
123
Intel XScale® Core
Developer’s Manual
Software Debug
9.4
Debug Control and Status Register (DCSR)
The DCSR register is the main control register for the debug unit.
Table 9-1
shows the format of
the register. The DCSR register can be accessed in privileged modes by software running on the
core or by a debugger through the JTAG interface. Refer to
Section 9.11.1, “SELDCSR JTAG
Register”
for details about accessing DCSR through JTAG.
Table 9-1.
Debug Control and Status Register (DCSR) (Sheet 1 of 2)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GE H B
TF TI
TD TA TS TU TR
SA
MOE
M E
Bits
Access
Description
Reset Value
TRST Value
31
SW Read / Write
JTAG Read-Only
Global Enable (GE)
0: disables all debug functionality
1: enables all debug functionality
0
unchanged
30
SW Read Only
JTAG Read / Write
Halt Mode (H)
0: Monitor Mode
1: Halt Mode
unchanged
0
29
SW Read-Only
JTAG Read-Only
SOC Break (B)
Value of SOC break core input
undefined
undefined
28:24
Read-undefined / Write-As-Zero
Reserved
undefined
undefined
23
SW Read Only
JTAG Read / Write
Trap FIQ (TF)
unchanged
0
22
SW Read Only
JTAG Read / Write
Trap IRQ (TI)
unchanged
0
21
Read-undefined / Write-As-Zero
Reserved
undefined
undefined
20
SW Read Only
JTAG Read / Write
Trap Data Abort (TD)
unchanged
0
19
SW Read Only
JTAG Read / Write
Trap Prefetch Abort (TA)
unchanged
0
18
SW Read Only
JTAG Read / Write
Trap Software Interrupt (TS)
unchanged
0
17
SW Read Only
JTAG Read / Write
Trap Undefined Instruction (TU)
unchanged
0
16
SW Read Only
JTAG Read / Write
Trap Reset (TR)
unchanged
0