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Silicon Laboratories EFM32G, Reference Manual

The Silicon Laboratories EFM32G is a premier microcontroller offering exceptional performance and energy efficiency. Explore its limitless potential with the comprehensive Reference Manual, available for free download from our website. Discover valuable insights and unleash the full potential of your EFM32G through this detailed and user-friendly manual.

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...the world's most energy friendly microcontrollers

2014-07-02 - Gecko Family - d0001_Rev1.30

501

www.silabs.com

List of Tables

2.1.  Register  Access  Types  ............................................................................................................................   3
3.1.  Energy  Mode  Description  .........................................................................................................................   8
3.2.  EFM32G  Microcontroller  Series  .................................................................................................................   8
3.3. Minor Revision Number Interpretation .......................................................................................................  10
4.1.  Interrupt  Request  Lines  (IRQ)  ..................................................................................................................  12
5.1.  Memory  System  Core  Peripherals  ............................................................................................................   17
5.2. Memory System Low Energy Peripherals ................................................................................................... 18
5.3.  Memory  System  Peripherals  ....................................................................................................................  19
5.4.  Device  Information  Page  Contents  ...........................................................................................................   23
7.1.  MSC  Flash  Memory  Mapping  ..................................................................................................................   31
7.2.  Lock  Bits  Page  Structure  ........................................................................................................................   32
8.1. AHB bus transfer arbitration interval .........................................................................................................  44
8.2.  DMA  channel  priority  .............................................................................................................................   44
8.3.  DMA  cycle  types  ...................................................................................................................................   46
8.4. channel_cfg for a primary data structure, in memory scatter-gather mode .........................................................  49
8.5. channel_cfg for a primary data structure, in peripheral scatter-gather mode ......................................................  51
8.6. Address bit settings for the channel control data structure .............................................................................  54
8.7.  src_data_end_ptr  bit  assignments  ............................................................................................................   55
8.8.  dst_data_end_ptr  bit  assignments  ............................................................................................................   56
8.9.  channel_cfg  bit  assignments  ...................................................................................................................   56
8.10. DMA cycle of six words using a word increment ........................................................................................  59
8.11. DMA cycle of 12 bytes using a halfword increment ....................................................................................  60
9.1. RMU Reset Cause Register Interpretation .................................................................................................  81
10.1.  EMU  Energy  Mode  Overview  .................................................................................................................   89
10.2. EMU Entering a Low Energy Mode .........................................................................................................  90
10.3. EMU Wakeup Triggers from Low Energy Modes .......................................................................................  91
13.1.  Reflex  Producers  ...............................................................................................................................   129
13.2.  Reflex  Consumers  .............................................................................................................................   130
15.1.  I

2

C  Reserved  I

2

C  Addresses  ................................................................................................................   176

15.2. I

2

C High and Low Periods for Low CLKDIV ............................................................................................  178

15.3.  I

2

C  Clock  Mode  .................................................................................................................................   179

15.4. I

2

C Interactions in Prioritized Order .......................................................................................................  182

15.5.  I

2

C  Master  Transmitter  ........................................................................................................................  184

15.6.  I

2

C  Master  Receiver  ...........................................................................................................................   186

15.7.  I

2

C  STATE  Values  .............................................................................................................................   187

15.8.  I

2

C  Transmission  Status  ......................................................................................................................  187

15.9.  I

2

C  Slave  Transmitter  .........................................................................................................................   190

15.10.  I

2

C  -  Slave  Receiver  .........................................................................................................................   191

15.11.  I

2

C  Bus  Error  Response  ....................................................................................................................   192

16.1. USART Asynchronous vs. Synchronous Mode ........................................................................................  209
16.2.  USART  Pin  Usage  .............................................................................................................................   209
16.3.  USART  Data  Bits  ...............................................................................................................................  210
16.4.  USART  Stop  Bits  ...............................................................................................................................   210
16.5.  USART  Parity  Bits  .............................................................................................................................   211
16.6.  USART  Oversampling  .........................................................................................................................   211
16.7. USART Baud Rates @ 4MHz Peripheral Clock .......................................................................................  212
16.8.  USART  SPI  Modes  ............................................................................................................................   224
16.9.  USART  IrDA  Pulse  Widths  ..................................................................................................................   228
17.1.  UART  Limitations  ...............................................................................................................................   248
18.1.  LEUART  Parity  Bit  .............................................................................................................................   251
18.2.  LEUART  Baud  Rates  .........................................................................................................................   252
19.1. TIMER Counter Response in X2 Decoding Mode .....................................................................................  280
19.2. TIMER Counter Response in X4 Decoding Mode .....................................................................................  280
19.3.  TIMER  Events  ...................................................................................................................................   291
20.1.  RTC  Resolution  Vs  Overflow  ...............................................................................................................   312
21.1.  LETIMER  Repeat  Modes  .....................................................................................................................  321
21.2. LETIMER Underflow Output Actions ......................................................................................................  326
22.1. PCNT QUAD Mode Counter Control Function .........................................................................................  344
23.1.  Bias  Configuration  ..............................................................................................................................  356
24.1.  Bias  Configuration  ..............................................................................................................................  366
25.1.  ADC  Single  Ended  Conversion  .............................................................................................................   380
25.2.  ADC  Differential  Conversion  ................................................................................................................   381
25.3. Oversampling Result Shifting and Resolution ..........................................................................................  381
25.4.  ADC  Results  Representation  ................................................................................................................  382
25.5.  Calibration  Register  Effect  ...................................................................................................................   383
28.1.  Pin  Configuration  ...............................................................................................................................   426
29.1.  LCD  Mux  Settings  ..............................................................................................................................  448
29.2.  LCD  BIAS  Settings  ............................................................................................................................   448
29.3.  LCD  Wave  Settings  ............................................................................................................................  448
29.4.  LCD  Contrast  ....................................................................................................................................   460
29.5.  LCD  Contrast  Function  .......................................................................................................................   461

Summary of Contents for EFM32G

Page 1: ...he 8 to 32 bit market with a combination of unmatched performance and ultra low power consumption in both active and sleep modes EFM32G devices consume as little as 180 µA MHz in run mode and as little as 900 nA with a Real Time Counter running Brown out and full RAM and register retention EFM32G s low energy consumption outperforms any other available 8 16 and 32 bit solution The EFM32G includes ...

Page 2: ...get more out of the available energy in a variety of applications Ultra low energy EFM32G microcontrollers are perfect for Gas metering Energy metering Water metering Smart metering Alarm and security systems Health and fitness applications Industrial and home automation 0 1 2 3 4 1 2 EFM32G Development Because EFM32G use the Cortex M3 CPU embedded designers benefit from the largest development ec...

Page 3: ...ter where x denotes the port instance A B Bit Fields Registers contain one or more bit fields which can be 1 to 32 bits wide Multi bit fields are denoted with x y where x is the start bit and y is the end bit Address The address for each register can be found by adding the base address of the module found in the Memory Map and the offset address for the register found in module Register Map Access...

Page 4: ...isters denoted with X have an unknown reset value and need to be initialized before use Note that before these registers are initialized read modify write operations might result in undefined register values Pin Connections Pin connections are given as a module prefix followed by a short pin name USn_TX USARTn TX pin The pin locations referenced in this document are given in the device specific da...

Page 5: ... 3 V Sleep Mode 180 µA MHz 3 V Run Mode with code executed from flash 128 64 32 16 KB Flash 16 8 KB RAM Up to 90 General Purpose I O pins Configurable push pull open drain pull up down input filter drive strength Configurable peripheral I O locations 16 asynchronous external interrupts 8 Channel DMA Controller Alternate primary descriptors with scatter gather ping pong operation 8 Channel Peripher...

Page 6: ... sensor Single ended or differential operation Conversion tailgating for predictable latency 12 bit 500 ksamples s Digital to Analog Converter 2 single ended channels 1 differential channel 2 Analog Comparator Programmable speed current Capacitive sensing with up to 8 inputs Supply Voltage Comparator Ultra efficient Power on Reset and Brown Out Detector 2 pin Serial Wire Debug interface 1 pin Seri...

Page 7: ... I O Low Energy UART Watchdog Oscillator Memory Protection Unit ADC DAC DMA Controller Debug Interface External Interrupts Pin Reset USART I2 C UART AES Gecko 32 bit bus Peripheral Reflex System Figure 3 2 Energy Mode Indicator 0 1 2 3 4 Note In the energy mode indicator the numbers indicates Energy Mode i e EM0 EM4 3 4 Energy Modes There are five different Energy Modes EM0 EM4 in the EFM32G see T...

Page 8: ...Energy Mode 3 Stop Mode In EM3 the low frequency oscillator is disabled but there is still full CPU and RAM retention as well as Power on Reset Pin reset and Brown out Detection with a consumption of only 0 6 µA The low power ACMP asynchronous external interrupt PCNT and I 2 C can wake up the device Even in this mode the wake up time is a few microseconds 0 1 2 3 4 EM4 Energy Mode 4 Shutoff Mode I...

Page 9: ... 2 1 3 9 1 1 3 1 1 8 2 2 2 8 Y QFN64 840F128 128 16 56 4x24 3 2 1 3 9 1 1 3 1 1 8 2 2 2 8 Y QFN64 880F32 32 8 85 4x40 3 1 2 1 3 9 1 1 3 1 1 8 2 2 2 16 Y Y 1 LQFP100 880F64 64 16 85 4x40 3 1 2 1 3 9 1 1 3 1 1 8 2 2 2 16 Y Y 1 LQFP100 880F128 128 16 85 4x40 3 1 2 1 3 9 1 1 3 1 1 8 2 2 2 16 Y Y 1 LQFP100 890F32 32 8 90 4x40 3 1 2 1 3 9 1 1 3 1 1 8 2 2 2 16 Y Y 1 LFBGA112 890F64 64 16 90 4x40 3 1 2 1 ...

Page 10: ...Major Rev 5 0 PID3 0xE00FFFEC 31 8 7 4 3 0 Minor Rev 3 0 Fam 1 0 Fam 5 2 PID2 0xE00FFFE8 31 8 7 4 3 0 Minor Rev 7 4 For the latest revision of the Gecko family the chip family number is 0x00 and the major revision number is 0x01 The minor revision number is to be interpreted according to Table 3 3 p 10 Table 3 3 Minor Revision Number Interpretation Minor Rev 7 0 Revision 0x00 A 0x01 B 0x02 C 0x03 ...

Page 11: ...omputational performance and exceptional system response to interrupts while meeting low cost requirements and low power consumption The ARM Cortex M3 implemented is revision r2p0 4 2 Features Harvard Architecture Separate data and program memory buses No memory bottleneck as for a single bus system 3 stage pipeline Thumb 2 instruction set Enhanced levels of performance energy efficiency and code ...

Page 12: ...he EFM32G devices have up to 30 interrupt request lines IRQ which are connected to the Cortex M3 Each of these lines shown in Table 4 1 p 12 are connected to one or more interrupt flags in one or more modules The interrupt flags are set by hardware on an interrupt condition It is also possible to set clear the interrupt flags through the IFS IFC registers Each interrupt flag is then qualified with...

Page 13: ... 02 Gecko Family d0001_Rev1 30 13 www silabs com IRQ Source 10 TIMER1 11 TIMER2 12 USART1_RX 13 USART1_TX 14 USART2_RX 15 USART2_TX 16 UART0_RX 17 UART0_TX 18 LEUART0 19 LEUART1 20 LETIMER0 21 PCNT0 22 PCNT1 23 PCNT2 24 RTC 25 CMU 26 VCMP 27 LCD 28 MSC 29 AES ...

Page 14: ...data restore time penalty and the DMA ensures fast autonomous transfers with predictable response time 5 1 Introduction The EFM32G contains an AMBA AHB Bus system allowing bus masters to access the memory mapped address space A multilayer AHB bus matrix using a Round robin arbitration scheme connects the master bus interfaces to the AHB slaves Figure 5 1 p 15 The bus matrix allows several AHB slav...

Page 15: ... Figure 5 1 EFM32G Bus System Cortex AHB Multilayer Bus Matrix DCode System DMA Flash RAM EBI AHB APB Bridge ICode AES Peripheral 0 Peripheral n 5 2 Functional Description The memory segments are mapped together with the internal segments of the Cortex M3 into the system memory map shown by Figure 5 2 p 16 ...

Page 16: ...5 2 1 Bit banding The SRAM bit band alias and peripheral bit band alias regions are located at 0x22000000 and 0x42000000 respectively Read and write operations to these regions are converted into masked single bit reads and atomic single bit writes to the embedded SRAM and peripherals of the EFM32G The standard approach to modify a single register or SRAM bit in the aliased regions requires softwa...

Page 17: ...AHB peripheral AES does not support bit banding 5 2 2 Peripherals The peripherals are mapped into the peripheral memory segment each with a fixed size address range according to Table 5 1 p 17 Table 5 2 p 18 and Table 5 3 p 19 Table 5 1 Memory System Core Peripherals Core peripherals Address range Peripheral 0x400E0400 0x41FFFFFF Reserved 0x400E0000 0x400E03FF AES 0x400CC400 0x400FFFFF Reserved 0x...

Page 18: ...FFF Reserved 0x4008A000 0x4008A3FF LCD 0x40088400 0x40089FFF Reserved 0x40088000 0x400883FF WDOG 0x40086C00 0x40087FFF Reserved 0x40086800 0x40086BFF PCNT2 0x40086400 0x400867FF PCNT1 0x40086000 0x400863FF PCNT0 0x40084800 0x40085FFF Reserved 0x40084400 0x400847FF LEUART1 0x40084000 0x400843FF LEUART0 0x40082400 0x40083FFF Reserved 0x40082000 0x400823FF LETIMER0 0x40080400 0x40081FFF Reserved 0x40...

Page 19: ...0 0x40006FFF GPIO 0x40004400 0x40005FFF Reserved 0x40004000 0x400043FF DAC0 0x40002400 0x40003FFF Reserved 0x40002000 0x400023FF ADC0 0x40001800 0x40001FFF Reserved 0x40001400 0x400017FF ACMP1 0x40001000 0x400013FF ACMP0 0x40000400 0x40000FFF Reserved 0x40000000 0x400003FF VCMP 5 2 3 Bus Matrix The Bus Matrix connects the memory segments to the bus masters Code CPU instruction or data fetches from...

Page 20: ...roduced to allow the transfer to complete on the peripheral clock The number of wait cycles per access in addition to master arbitration is given by Memory Wait Cycles with Clock Slower than CPU Ncycles 2 Nslave cycles x fHFCORECLK fHFPERCLK 5 4 where Nslave cycles is the number of wait cycles introduced by the slave For general register access Nslave cycles 1 More details on clocks and prescaling...

Page 21: ...iple write access to a register which must be prevented It is not required to wait until the relevant flag in the SYNCBUSY register is cleared after writing a register E g EM2 can be entered immediately after writing a register Figure 5 3 Write operation to Low Energy Peripherals Register 0 Register 1 Register n Synchronizer 0 Synchronizer 1 Synchronizer n Register 0 Sync Register 1 Sync Register ...

Page 22: ...ed allowing the software to write multiple Low Energy registers before starting the synchronization process thus providing precise control of the module update process The synchronization process is started by clearing the REGFREEZE bit 5 4 Flash The Flash retains data in any state and typically stores the application code special user data and security information The Flash memory is typically pr...

Page 23: ... 6 0 Offset for 1V25 reference 0x0FE081B6 ADC0_CAL_2V5 14 8 Gain for 2V5 reference 6 0 Offset for 2V5 reference 0x0FE081B8 ADC0_CAL_VDD 14 8 Gain for VDD reference 6 0 Offset for VDD reference 0x0FE081BA ADC0_CAL_5VDIFF 14 8 Gain for 5VDIFF reference 6 0 Offset for 5VDIFF reference 0x0FE081BC ADC0_CAL_2XVDD 14 8 Reserved gain for this reference cannot be calibrated 6 0 Offset for 2XVDD reference 0...

Page 24: ...E 7 0 Flash page size in bytes coded as 2 MEM_INFO_PAGE_SIZE 10 0xFF Ie the value 0xFF 512 bytes 0x0FE081F0 UNIQUE_0 31 0 Unique number 0x0FE081F4 UNIQUE_1 63 32 Unique number 0x0FE081F8 MEM_INFO_FLASH 15 0 Flash size kbyte count as unsigned integer eg 128 0x0FE081FA MEM_INFO_RAM 15 0 Ram size kbyte count as unsigned integer eg 16 0x0FE081FC PART_NUMBER 15 0 EFM32 part number as unsigned integer e...

Page 25: ... pin serial wire debug SWD interface In addition there is also a Serial Wire Viewer pin which can be used to output profiling information data trace and software generated messages For more technical information about the debug interface the reader is referred to ARM Cortex M3 Technical Reference Manual ARM CoreSight Components Technical Reference Manual ARM Debug Interface v5 Architecture Specifi...

Page 26: ...s the current consumption in this mode is closer to EM1 and it is therefore important to disconnect the debugger before doing current consumption measurements 6 4 Debug Lock and Device Erase The debug access to the Cortex M3 is locked by clearing the Debug Lock Word DLW and resetting the device see Section 7 3 2 p 32 When debug access is locked the debug interface remains accessible but the connec...

Page 27: ...tion takes 40 ms to complete Note that the SRAM contents will also be deleted during a device erase while the UD page is not erased Even if the device is not locked the can device can be erased through the AAP using the above procedure during the AAP window This can be useful if the device has been programmed with code that e g disables the debug interface pins on start up or does something else t...

Page 28: ... 0 More information in Section 2 1 p 3 1 SYSRESETREQ 0 W1 System Reset Request A system reset request is generated when set to 1 This register is write enabled from the AAP_CMDKEY register 0 DEVICEERASE 0 W1 Erase the Flash Main Block SRAM and Lock Bits When set all data and program code in the main block is erased the SRAM is cleared and then the Lock Bit LB page is erased This also includes the ...

Page 29: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access R Name ERASEBUSY Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 ERASEBUSY 0 R Device Erase Command Status This bit is set when a device erase is executing 6 6 4 AAP_IDR AAP Identification Register Offset Bit Position 0x0FC 31 30 29 28 27 26 25 24...

Page 30: ...evel energy consumption and error handling capabilities to the requirements at hand How The MSC integrates a low energy Flash IP with a charge pump enabling minimum energy consumption while eliminating the need for external programming voltage to erase the memory An easy to use write and erase interface is supported by an internal fixed frequency oscillator and autonomous flash timing and control ...

Page 31: ...n block is device dependent The largest size available is 128 kB 256 pages The information block has 512 bytes available for user data The information block also contains chip configuration data located in a reserved area The main block is mapped to address 0x00000000 and the information block is mapped to address 0x0FE00000 Table 7 1 p 31 outlines how the Flash is mapped in the memory space All F...

Page 32: ... operation initiated from the Authentication Access Port AAP registers The AAP is described in more detail in Section 6 4 p 26 Note that the AAP is only accessible from the debug interface and cannot be accessed from the Cortex M3 core There are 32 page lock bits per page lock word PLW Bit 0 refers to the first page and bit 31 refers to the last page within a PLW Thus PLW 0 contains lock bits for ...

Page 33: ...en or not To optimize for low energy the MSC can be configured to cancel these speculative branch target prefetches With this configuration energy consumption is more optimal as the branch target instruction fetch is delayed until the branch condition is evaluated The performance penalty with this mode enabled is source code dependent but is normally less than 1 for core frequencies from 16 MHz an...

Page 34: ...SC_WDATA register and then set the WRITETRIG bit of the MSC_WRITECMD register DMA triggers when the WDATAREADY bit of the MSC_STATUS register is set It is possible to write words twice between each erase by keeping at 1 the bits that are not to be changed Let us take as an example writing two 16 bit values 0xAAAA and 0x5555 To safely write them in the same flash word this method can be used Write ...

Page 35: ...errupt Enable Register 0x03C MSC_LOCK RW Configuration Lock Register 7 5 Register Description 7 5 1 MSC_CTRL Memory System Control Register Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 1 Access RW Name BUSFAULT Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 M...

Page 36: ...energy by delaying the Cortex conditional branch target prefetches until the conditional branch instruction is in the execute stage When the instruction reaches this stage the evaluation of the branch condition is completed and the core does not perform a speculative prefetch of both the branch target address and the next sequential address With the SCBTP function enabled one instruction fetch is ...

Page 37: ... register must be set in order to use this command 0 LADDRIM 0 W1 Load MSC_ADDRB into ADDR Load the internal write address register ADDR from the MSC_ADDRB register The internal address register ADDR is incremented automatically by 4 after each word is written When ADDR is incremented past the page boundary ADDR is set to the base of the page 7 5 5 MSC_ADDRB Page Erase Write Address Buffer Offset ...

Page 38: ...bit is set MSC_WDATA was not written within the timeout The flash write operation timed out and access to the flash is returned to the AHB interface This bit is cleared when the ERASEPAGE WRITETRIG or WRITEONCE commands in MSC_WRITECMD are triggered 3 WDATAREADY 1 R WDATA Write Ready When this bit is set the content of MSC_WDATA is read by MSC Flash Write Controller and the register may be updated...

Page 39: ...tibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 WRITE 0 W1 Write Done Interrupt Set Set the write done bit and generate interrupt 0 ERASE 0 W1 Erase Done Interrupt Set Set the erase done bit and generate interrupt 7 5 10 MSC_IFC Interrupt Flag Clear Register Offset Bit Position 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6...

Page 40: ... interrupt 7 5 12 MSC_LOCK Configuration Lock Register Offset Bit Position 0x03C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name LOCKKEY Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 LOCKKEY 0x0000 RW Configuration Lock Wri...

Page 41: ...emory Access DMA controller performs memory operations independently of the CPU This has the benefit of reducing the energy consumption and the workload of the CPU and enables the system to stay in low energy modes for example when moving data from the USART to RAM or from the External Bus Interface EBI to the DAC The DMA controller uses the PL230 µDMA controller licensed from ARM 1 Each of the PL...

Page 42: ...errupts upon transfer completion Data transfer to from LEUART in EM2 is supported by the DMA providing extremely low energy consumption while performing UART communications 8 3 Block Diagram An overview of the DMA and the modules it interacts with is shown in Figure 8 1 p 42 Figure 8 1 DMA Block Diagram Interrupts APB block APB memory mapped registers AHB block AHB Lite master interface DMA contro...

Page 43: ... 53 In addition to the basic transfer mode the DMA Controller also supports two advanced transfer modes ping pong and scatter gather Ping pong transfers are ideally suited for streaming data for high speed peripheral communication as the DMA will be ready to retrieve the next incoming data bytes immediately while the processor core is still processing the previous ones and similarly for outgoing c...

Page 44: ...always performs sequences of 2 R transfers until N 2 R remain to be transferred The controller performs the remaining N transfers at the end of the DMA cycle You store the value of the R_power bits in the channel control data structure See Section 8 4 3 3 p 56 for more information about the location of the R_power bits in the data structure 8 4 2 2 Priority When the controller arbitrates it determ...

Page 45: ...polls all the DMA channels that are available Figure 8 2 p 45 shows the process it uses to determine which DMA transfer to perform next Figure 8 2 Polling flowchart Start polling Is there a channel request Are any channel requests using a high priority level Start DMA transfer Yes Yes Select channel that has the lowest channel number and is set to high priority level Select channel that has the lo...

Page 46: ...ller to use either the primary or the alternate data structure After you enable the channel C and the controller receives a request for this channel then the flow for this DMA cycle is as follows 1 The controller performs 2 R transfers If the number of transfers remaining becomes zero then the flow continues at step 3 p 46 2 The controller arbitrates if a higher priority channel is requesting serv...

Page 47: ...n Figure 8 3 Ping pong example Task A Request Request Task A Primary cycle_ctrl b011 2R 4 N 6 dma_done C Task B Request Request Task B Alternate cycle_ctrl b011 2R 4 N 12 dma_done C Request Task C Request Task C Primary cycle_ctrl b011 2R 2 N 2 dma_done C Task D Request Request Task D Alternate cycle_ctrl b011 2R 4 N 5 dma_done C Task E Request Task E Primary cycle_ctrl b011 2R 4 N 7 dma_done C En...

Page 48: ...receives a new request for the channel and it has the highest priority then task C commences Task C 13 The controller performs two DMA transfers 14 The controller sets dma_done C HIGH for one HFCORECLK cycle and enters the arbitration process After task C completes the host processor can configure the primary data structure for task E After the controller receives a new request for the channel and...

Page 49: ...rogram the alternate data structure Table 8 4 p 49 lists the fields of the channel_cfg memory location for the primary data structure that you must program with constant values and those that can be user defined Table 8 4 channel_cfg for a primary data structure in memory scatter gather mode Bit Field Value Description Constant value fields 31 30 dst_inc b10 Configures the controller to use word i...

Page 50: ...ate in memory scatter gather mode by setting cycle_ctrl to b100 Because a data structure for a single channel consists of four words then you must set 2 R to 4 In this example there are four tasks and therefore N is set to 16 2 The host processor writes the data structure for tasks A B C and D to the memory locations that the primary src_data_end_ptr specifies 3 The host processor enables the chan...

Page 51: ...ity then it performs another four DMA transfers using the primary data structure It then immediately starts a DMA cycle using the alternate data structure without re arbitrating The controller continues to switch from primary to alternate to primary until either the host processor configures the alternate data structure for a basic cycle it reads an invalid data structure Note After the controller...

Page 52: ... transfer that the alternate channel control data structure specifies 1 Configure primary to enable the copy A B C and D operations cycle_ctrl b110 2R 4 N 16 Initialization 2 Write the primary source data in memory using the structure shown in the following table cycle_ctrl b111 2R 4 N 3 cycle_ctrl b111 2R 2 N 8 cycle_ctrl b111 2R 8 N 5 cycle_ctrl b001 2R 4 N 4 src_data_end_ptr dst_data_end_ptr ch...

Page 53: ... priority then the process continues with Primary copy D 10 The controller performs four DMA transfers These transfers write the alternate data structure for task D 11 The controller sets the cycle_ctrl bits of the primary data structure to b000 to indicate that this data structure is now invalid Task D 12 The controller performs task D using a basic cycle 13 The controller sets dma_done C HIGH fo...

Page 54: ... elements in the structure and therefore the base address must be at 0xXXXXXX00 You can configure the base address for the primary data structure by writing the appropriate value in the DMA_CTRLBASE register You do not need to set aside the full 256 bytes if all dma channels are not used or if all alternate descriptors are not used If for example only 4 channels are used and they only need the pri...

Page 55: ...ointer Destination End Pointer Control Unused 0x0F0 0x0F4 0x0F8 0x00C 0x01C 0x07C 0x08C 0x09C 0x0FC Primary data structure Alternate data structure The controller uses the system memory to enable it to access two pointers and the control information that it requires for each channel The following subsections will describe these 32 bit memory locations and how the controller calculates the DMA tran...

Page 56: ...ansfer the channel_cfg memory location provides the control information for the controller Figure 8 8 p 56 shows the bit assignments for this memory location Figure 8 8 channel_cfg bit assignments 31 21 20 13 4 0 dst_inc src_prot_ctrl R_power n_minus_1 next_useburst 30 29 28 27 26 25 24 23 dst_size src_size src_inc dst_prot_ctrl 18 17 cycle_ctrl 3 14 2 Table 8 9 p 56 lists the bit assignments for ...

Page 57: ...ize of the source data b00 byte b01 halfword b10 word b11 reserved 23 21 dst_prot_ctrl Set the bits to control the state of HPROT when the controller writes the destination data Bit 23 This bit has no effect on the DMA Bit 22 This bit has no effect on the DMA Bit 21 Controls the state of HPROT as follows 0 HPROT is LOW and the access is non privileged 1 HPROT is HIGH and the access is privileged 2...

Page 58: ...value of the chnl_useburst_set C bit If the chnl_useburst_set C bit is 0 then for all the remaining DMA cycles in the peripheral scatter gather transaction the controller responds to requests on dma_req and dma_sreq when it performs a DMA cycle that uses an alternate data structure 1 the controller sets the chnl_useburst_set C bit to a 1 Therefore for the remaining DMA cycles in the peripheral sca...

Page 59: ...inc specifies and then subtracts the resulting value from the source data end pointer Similarly to calculate the destination address of a DMA transfer it performs a left shift operation on the n_minus_1 value by a shift amount that dst_inc specifies and then subtracts the resulting value from the destination end pointer Depending on the value of src_inc and dst_inc the source address and destinati...

Page 60: ...l 0 2 R_power b11 1 This value is the result of count being shifted left by the value of dst_inc 2 After the controller completes the DMA cycle it invalidates the channel_cfg memory location by clearing the cycle_ctrl field 8 4 4 Interaction with the EMU The DMA interacts with the Energy Management Unit EMU to allow transfers from e g the LEUART to occur in EM2 The EMU can wake up the DMA sufficie...

Page 61: ...e b01 halfword transfer size iii src_inc b11 no address increment for source iv src_size 01 halfword transfer size v dst_prot_ctrl 000 no cache buffer privilege vi src_prot_ctrl 000 no cache buffer privilege vii R_power b0000 arbitrate after each DMA transfer viii n_minus_1 d20 transfer 21 halfwords ix next_useburst b0 not applicable x cycle_ctrl b001 basic operating mode 3 Enable the DMA a Write ...

Page 62: ...8 DMA_CHENS RW1 Channel Enable Set Register 0x02C DMA_CHENC W1 Channel Enable Clear Register 0x030 DMA_CHALTS RW1 Channel Alternate Set Register 0x034 DMA_CHALTC W1 Channel Alternate Clear Register 0x038 DMA_CHPRIS RW1 Channel Priority Set Register 0x03C DMA_CHPRIC W1 Channel Priority Clear Register 0x04C DMA_ERRORC RW Bus Error Clear Register 0xE10 DMA_CHREQSTATUS R Channel Request Status 0xE18 D...

Page 63: ...alue Mode Description 0 IDLE Idle 1 RDCHCTRLDATA Reading channel controller data 2 RDSRCENDPTR Reading source data end pointer 3 RDDSTENDPTR Reading destination data end pointer 4 RDSRCDATA Reading source data 5 WRDSTDATA Writing destination data 6 WAITREQCLR Waiting for DMA request to clear 7 WRCHCTRLDATA Writing channel controller data 8 STALLED Stalled 9 DONE Done 10 PERSCATTRANS Peripheral sca...

Page 64: ...12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name CTRLBASE Bit Name Reset Access Description 31 0 CTRLBASE 0x00000000 RW Channel Control Data Base Pointer The base pointer for a location in system memory that holds the channel control data structure This register must be written to point to a location in system memory with the channel control data structure before the DMA can be used No...

Page 65: ...nel 4 Wait on Request Status Status for wait on request for channel 4 3 CH3WAITSTATUS 1 R Channel 3 Wait on Request Status Status for wait on request for channel 3 2 CH2WAITSTATUS 1 R Channel 2 Wait on Request Status Status for wait on request for channel 2 1 CH1WAITSTATUS 1 R Channel 1 Wait on Request Status Status for wait on request for channel 1 0 CH0WAITSTATUS 1 R Channel 0 Wait on Request St...

Page 66: ...S CH1USEBURSTS CH0USEBURSTS Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 CH7USEBURSTS 0 RW1H Channel 7 Useburst Set See description for channel 0 6 CH6USEBURSTS 0 RW1H Channel 6 Useburst Set See description for channel 0 5 CH5USEBURSTS 0 RW1H Channel 5 Useburst Set See description for channe...

Page 67: ...r this channel 6 CH6USEBURSTC 0 W1 Channel 6 Useburst Clear Write to 1 to disable useburst setting for this channel 5 CH5USEBURSTC 0 W1 Channel 5 Useburst Clear Write to 1 to disable useburst setting for this channel 4 CH4USEBURSTC 0 W1 Channel 4 Useburst Clear Write to 1 to disable useburst setting for this channel 3 CH3USEBURSTC 0 W1 Channel 3 Useburst Clear Write to 1 to disable useburst settin...

Page 68: ... disable peripheral requests for this channel 8 7 10 DMA_CHREQMASKC Channel Request Mask Clear Register Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 W1 W1 Name CH7REQMASKC CH6REQMASKC CH5REQMASKC CH4REQMASKC CH3REQMASKC CH2REQMASKC CH1REQMASKC CH0REQMASKC Bit Name Reset Access Descript...

Page 69: ... RW1 Channel 5 Enable Set Write to 1 to enable this channel Reading returns the enable status of the channel 4 CH4ENS 0 RW1 Channel 4 Enable Set Write to 1 to enable this channel Reading returns the enable status of the channel 3 CH3ENS 0 RW1 Channel 3 Enable Set Write to 1 to enable this channel Reading returns the enable status of the channel 2 CH2ENS 0 RW1 Channel 2 Enable Set Write to 1 to ena...

Page 70: ... or an ERROR occurs on the AHB Lite bus A read from this field returns the value of CH0ENS from the DMA_CHENS register 8 7 13 DMA_CHALTS Channel Alternate Set Register Offset Bit Position 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access RW1 RW1 RW1 RW1 RW1 RW1 RW1 RW1 Name CH7ALTS CH6ALTS CH5ALTS CH4ALTS CH3ALTS CH2ALTS CH1ALT...

Page 71: ...cture for this channel 5 CH5ALTC 0 W1 Channel 5 Alternate Clear Write to 1 to select the primary structure for this channel 4 CH4ALTC 0 W1 Channel 4 Alternate Clear Write to 1 to select the primary structure for this channel 3 CH3ALTC 0 W1 Channel 3 Alternate Clear Write to 1 to select the primary structure for this channel 2 CH2ALTC 0 W1 Channel 2 Alternate Clear Write to 1 to select the primary ...

Page 72: ...priority status 0 CH0PRIS 0 RW1 Channel 0 High Priority Set Write to 1 to obtain high priority for this channel Reading returns the channel priority status 8 7 16 DMA_CHPRIC Channel Priority Clear Register Offset Bit Position 0x03C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 W1 W1 Name CH7PRIC CH6PRIC CH5PRIC ...

Page 73: ...Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 CH7REQSTATUS 0 R Channel 7 Request Status When this bit is 1 it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel The controller services the request by performing the DMA cycle...

Page 74: ...vices the request by performing the DMA cycle using single DMA transfers 6 CH6SREQSTATUS 0 R Channel 6 Single Request Status When this bit is 1 it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service the DMA channel The controller services the request by performing the DMA cycle using single DMA transfers 5 CH5SREQSTATUS 0 R Channel 5 Sin...

Page 75: ...ansfer If the channel is disabled the flag is set when there is a request for the channel 3 CH3DONE 0 R DMA Channel 3 Complete Interrupt Flag Set when the DMA channel has completed its transfer If the channel is disabled the flag is set when there is a request for the channel 2 CH2DONE 0 R DMA Channel 2 Complete Interrupt Flag Set when the DMA channel has completed its transfer If the channel is d...

Page 76: ...ame ERR CH7DONE CH6DONE CH5DONE CH4DONE CH3DONE CH2DONE CH1DONE CH0DONE Bit Name Reset Access Description 31 ERR 0 W1 DMA Error Interrupt Flag Clear Set to 1 to clear DMA error interrupt flag Note that if an error happened the Bus Error Clear Register must be used to clear the DMA 30 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7...

Page 77: ...rrupt on this DMA channel Clear to disable the interrupt 4 CH4DONE 0 RW DMA Channel 4 Complete Interrupt Enable Write to 1 to enable complete interrupt on this DMA channel Clear to disable the interrupt 3 CH3DONE 0 RW DMA Channel 3 Complete Interrupt Enable Write to 1 to enable complete interrupt on this DMA channel Clear to disable the interrupt 2 CH2DONE 0 RW DMA Channel 2 Complete Interrupt Ena...

Page 78: ...Section 2 1 p 3 3 0 SIGSEL 0x0 RW Signal Select Select input signal to DMA channel Value Mode Description SOURCESEL 0b000000 NONE 0bxxxx OFF Channel input selection is turned off SOURCESEL 0b001000 ADC0 0b0000 ADC0SINGLE ADC0SINGLE 0b0001 ADC0SCAN ADC0SCAN SOURCESEL 0b001010 DAC0 0b0000 DAC0CH0 DAC0CH0 0b0001 DAC0CH1 DAC0CH1 SOURCESEL 0b001100 USART0 0b0000 USART0RXDATAV USART0RXDATAV REQ SREQ 0b0...

Page 79: ...TIMER1UFOF 0b0001 TIMER1CC0 TIMER1CC0 0b0010 TIMER1CC1 TIMER1CC1 0b0011 TIMER1CC2 TIMER1CC2 SOURCESEL 0b011010 TIMER2 0b0000 TIMER2UFOF TIMER2UFOF 0b0001 TIMER2CC0 TIMER2CC0 0b0010 TIMER2CC1 TIMER2CC1 0b0011 TIMER2CC2 TIMER2CC2 SOURCESEL 0b101100 UART0 0b0000 UART0RXDATAV UART0RXDATAV REQ SREQ 0b0001 UART0TXBL UART0TXBL REQ SREQ 0b0010 UART0TXEMPTY UART0TXEMPTY SOURCESEL 0b110000 MSC 0b0000 MSCWDA...

Page 80: ...r handling the reset functionality of the EFM32G 9 2 Features Reset sources Power on Reset POR Brown out Detection BOD RESETn pin reset Watchdog reset Software triggered reset SYSRESETREQ Core LOCKUP condition A software readable register indicates the cause of the last reset 9 3 Functional Description The RMU monitors each of the reset sources of the EFM32G If one or more reset sources go active ...

Page 81: ...MU_RSTCAUSE 1 Write a 1 to RCCLR in RMU_CMD 2 Write a 1 to bit 0 in EMU_AUXCTRL 3 Write a 0 to bit 0 in EMU_AUXCTRL RMU_RSTCAUSE should be interpreted according to Table 9 1 p 81 X bits are don t care Notice that it is possible to have multiple reset causes For example an external reset and a watchdog reset may happen simultaneously Table 9 1 RMU Reset Cause Register Interpretation Register Value ...

Page 82: ...nregulated 3 0 V power and one for the internal 1 8 V power The BODs are constantly monitoring the voltages Whenever the voltage is below the VBODthr value see Electrical Characteristics for details the corresponding active low BROWNOUTn line is held low The BODs also include hysteresis which prevents instability in the corresponding BROWNOUTn line when the supply is crossing the VBODthr limit or ...

Page 83: ...core being locked up because of an unrecoverable exception following the activation of the processor s built in system state protection hardware For more information about the Cortex M3 lockup conditions see the ARMv7 M Architecture Reference Manual The Lockup reset does not reset the Debug Interface Set the LOCKUPRDIS bit in the RMU_CTRL register in order to disable this reset source 9 3 7 System...

Page 84: ...l from the Cortex from resetting the device 9 5 2 RMU_RSTCAUSE Reset Cause Register Offset Bit Position 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 Access R R R R R R R Name SYSREQRST LOCKUPRST WDOGRST EXTRST BODREGRST BODUNREGRST PORST Bit Name Reset Access Description 31 7 Reserved To ensure compatibility with future devices alw...

Page 85: ...domain brown out detector reset has been performed Must be cleared by software Please see Table 9 1 p 81 for details on how to interpret this bit 0 PORST 0 R Power On Reset Set if a power on reset has been performed Must be cleared by software Please see Table 9 1 p 81 for details on how to interpret this bit 9 5 3 RMU_CMD Command Register Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21...

Page 86: ...agement Unit EMU manages all the low energy modes EM in EFM32G microcontrollers Each energy mode manages if the CPU and the various peripherals are available The energy modes range from EM0 to EM4 where EM0 also called run mode enables the CPU and all peripherals The lowest recoverable energy mode EM3 disables the CPU and most peripherals while maintaining wake up and RAM functionality EM4 disable...

Page 87: ...energy mode in which any peripheral function can be enabled and the Cortex M3 core is executing instructions EM1 through EM4 also called low energy modes provide a selection of reduced peripheral functionality that also lead to reduced energy consumption as described below Figure 10 2 p 88 shows the transitions between different energy modes After reset the EMU will always start in EM0 A transitio...

Page 88: ...triggered wakeup from EM4 No direct transitions between EM1 EM2 or EM3 are available as can also be seen from Figure 10 2 p 88 Instead a wakeup will transition back to EM0 in which software can enter any other low energy mode An overview of the supported energy modes and the functionality available in each mode is shown in Table 10 1 p 89 Most peripheral functionality indicated as On in a particul...

Page 89: ...On On I 2 C receive address recognition On On On On Watchdog On On On On 3 Pin interrupts On On On On RAM voltage regulator RAM retention On On On On Brown Out Reset On On On On Power On Reset On On On On On Pin Reset On On On On On 1 Energy Mode 0 Active Mode 2 Energy Mode 1 2 3 4 3 When the 1 kHz ULFRCO is selected The different Energy Modes are summarized in the following sections 10 3 1 1 EM0 ...

Page 90: ...Cortex M3 triggers the transition into a low energy mode The transition into a low energy mode can optionally be delayed until the lowest priority Interrupt Service Routine ISR is exited if the SLEEPONEXIT bit in the Cortex M3 System Control Register is set Entering the lowest energy mode EM4 is done by writing a sequence to the EM4CTRL bitfield in the EMU_CTRL register Writing a zero to the EM4CT...

Page 91: ...nabled interrupt Yes MSC Any enabled interrupt Yes DAC Any enabled interrupt Yes ADC Any enabled interrupt Yes AES Any enabled interrupt Yes PCNT Any enabled interrupt Yes Yes Yes 3 LCD Any enabled interrupt Yes Yes ACMP Any enabled edge interrupt Yes Yes Yes VCMP Any enabled edge interrupt Yes Yes Yes Pin interrupts Asynchronous Yes Yes Yes Pin Reset Yes Yes Yes Yes Power Cycle Off On Yes Yes Yes...

Page 92: ... Section 2 1 p 3 3 2 EM4CTRL 0x0 RW Energy Mode 4 Control This register is used to enter Energy Mode 4 in which the device only wakes up from an external pin reset or from a power cycle Energy Mode 4 is entered when the EM4 sequence is written to this bitfield 1 EM2BLOCK 0 RW Energy Mode 2 Block This bit is used to prevent the MCU to enter Energy Mode 2 or lower 0 EMVREG 0 RW Energy Mode Voltage R...

Page 93: ... Access RW Name LOCKKEY Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 LOCKKEY 0x0000 RW Configuration Lock Key Write any other value than the unlock code to lock all EMU registers except the interrupt registers from editing Write the unlock code to unlock When reading the register bit 0 i...

Page 94: ...endly microcontrollers 2014 07 02 Gecko Family d0001_Rev1 30 94 www silabs com Bit Name Reset Access Description Write to 1 and then 0 to clear the POR BOD and WDOG reset cause register bits See also the Reset Management Unit RMU ...

Page 95: ...ator start up times makes duty cycling between active mode and the different low energy modes EM2 EM4 very efficient The calibration feature ensures high accuracy RC oscillators Several interrupts are available to avoid CPU polling of flags 11 1 Introduction The Clock Management Unit CMU is responsible for controlling the oscillators and clocks on board the EFM32G The CMU provides the capability t...

Page 96: ...modules and all peripherals Selectable clocks can be output on two pins for use externally Auxiliary 14 MHz RC oscillator AUXHFRCO for flash programming and debug trace 11 3 Functional Description An overview of the CMU is shown in Figure 11 1 p 97 The number of peripheral modules that are connected to the different clocks varies from device to device ...

Page 97: ... Gate Clock Gate clock switch clock switch clock switch prescaler prescaler prescaler prescaler prescaler HFCORECLKLE CMU_HFCORECLKEN0 LE Clock Gate 2 HFCORECLK HFPERCLK Frame Rate Control ULFRCO PCNTnCLK PCNTn_S0 WDOG WDOG_CTRL CLKSEL CMU_LFCLKSEL LFB CMU_LFCLKSEL LFA CMU_LFBCLKEN0 LEUART1 CMU_LCDCTRL FDIV CMU_HFPERCLKDIV HFPERCLKDIV CMU_HFCORECLKDIV CMU_LFBPRESC0 LEUART1 CMU_LFBPRESC0 LEUART0 CM...

Page 98: ... takes effect immediately Note Note that if HFPERCLK runs faster than HFCORECLK the number of clock cycles for each bus access to peripheral modules will increase with the ratio between the clocks E g if a bus access normally takes three cycles it will take 9 cycles if HFPERCLK runs three times as fast as the HFCORECLK 11 3 1 4 LFACLK Low Frequency A Clock LFACLK is the selected clock for the Low ...

Page 99: ...et to indicated that the start up time has exceeded and that the clock is available The low start up time values can be used for an external clock source of already high quality while the higher start up times should be used when the clock signal is coming directly from a crystal The startup time for HFXO and LFXO can be set by configuring the HFXOTIMEOUT and LFXOTIMEOUT bitfields respectively Bot...

Page 100: ...t when the oscillator is ready This flag can also be configured to generate an interrupt Figure 11 2 CMU Switching from HFRCO to HFXO before HFXO is ready HFXO CMU_STATUS HFXORDY CMU_STATUS HFXOENS CMU_STATUS HFXOSEL HFRCO HFCLK HFXO time out period CMU_STATUS HFRCORDY CMU_STATUS HFRCOENS CMU_STATUS HFRCOSEL CMU_OSCENCMD HFXOEN CMU_OSCENCMD HFXODIS clocks CMU_CMD HFCLKSEL CMU_OSCENCMD HFRCOEN CMU_...

Page 101: ...e LFXTAL_N LFXTAL_P pins as shown in Figure 11 5 p 101 Figure 11 5 LFXO Pin Connection EFM32 LFXTAL_N LFXTAL_P 32 768kHz CL1 CL2 It is possible to connect an external clock source to HFXTAL_N LFXTAL_N pin of the HFXO or LFXO oscillator By configuring the HFXOMODE LFXOMODE fields in CMU_CTRL the HFXO LFXO can be bypassed 11 3 3 2 HFRCO LFRCO and AUXHFRCO It is possible to calibrate the HFRCO LFRCO ...

Page 102: ... support it is simple to write efficient calibration algorithms in software Figure 11 6 HW support for RC Oscillator Calibration 0 HFRCO LFRCO HFXO LFXO CALCLK Counter 20 bit up counter HFCLK start stop AUXHFRCO CMU_CMD CALSTART CMU_CALCTRL UPSEL Set CMU_IF CALRDY CALCLK CMU_CALCNT 20 bit down counter 11 3 4 Output Clock on a Pin It is possible to configure the CMU to output clocks on two pins Thi...

Page 103: ...x028 CMU_LFCLKSEL RW Low Frequency Clock Select Register 0x02C CMU_STATUS R Status Register 0x030 CMU_IF R Interrupt Flag Register 0x034 CMU_IFS W1 Interrupt Flag Set Register 0x038 CMU_IFC W1 Interrupt Flag Clear Register 0x03C CMU_IEN RW Interrupt Enable Register 0x040 CMU_HFCORECLKEN0 RW High Frequency Core Clock Enable Register 0 0x044 CMU_HFPERCLKEN0 RW High Frequency Peripheral Clock Enable ...

Page 104: ...ally output on the pin set CLKOUT0PEN in CMU_ROUTE Value Mode Description 0 HFRCO HFRCO directly from oscillator 1 HFXO HFXO directly from oscillator 2 HFCLK2 HFCLK 2 3 HFCLK4 HFCLK 4 4 HFCLK8 HFCLK 8 5 HFCLK16 HFCLK 16 6 ULFRCO ULFRCO directly from oscillator 19 18 LFXOTIMEOUT 0x3 RW LFXO Timeout Configures the start up delay for LFXO Value Mode Description 0 8CYCLES Timeout period of 8 cycles 1 ...

Page 105: ...nter has timed out glitches will not be detected 6 5 HFXOBUFCUR 0x1 RW HFXO Boost Buffer Current This value has been set during calibration and should not be changed 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 2 HFXOBOOST 0x3 RW HFXO Start up Boost Current Used to adjust start up boost current for HFXO Value Mode Description 0...

Page 106: ... Clock Division Register Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 1 0x0 Access RW RW Name HFPERCLKEN HFPERCLKDIV Bit Name Reset Access Description 31 9 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 8 HFPERCLKEN 1 RW HFPERCLK Enable Set to enable the HFPERCL...

Page 107: ...de Description 0 1MHZ 1 MHz band NOTE Also set the TUNING value bits 7 0 when changing band 1 7MHZ 7 MHz band NOTE Also set the TUNING value bits 7 0 when changing band 2 11MHZ 11 MHz band NOTE Also set the TUNING value bits 7 0 when changing band 3 14MHZ 14 MHz band NOTE Also set the TUNING value bits 7 0 when changing band 4 21MHZ 21 MHz band NOTE Also set the TUNING value bits 7 0 when changing...

Page 108: ...equency This field is updated with the production calibrated value during reset and the reset value might therefore vary between devices 11 5 7 CMU_CALCTRL Calibration Control Register Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 Access RW Name UPSEL Bit Name Reset Access Description 31 3 Reserved To ensure compatibility ...

Page 109: ...24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 Name LFXODIS LFXOEN LFRCODIS LFRCOEN AUXHFRCODIS AUXHFRCOEN HFXODIS HFXOEN HFRCODIS HFRCOEN Bit Name Reset Access Description 31 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 9 LFXODIS 0 W1 LFXO Disable ...

Page 110: ...escription 31 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 CALSTART 0 W1 Calibration Start Starts the calibration effectively loading the CMU_CALCNT into the down counter and start decrementing 2 0 HFCLKSEL 0x0 W1 HFCLK Select Selects the clock source for HFCLK Note that selecting an oscillator that is disabled will cause the s...

Page 111: ...Status Register Offset Bit Position 0x02C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 Access R R R R R R R R R R R R R R R Name CALBSY LFXOSEL LFRCOSEL HFXOSEL HFRCOSEL LFXORDY LFXOENS LFRCORDY LFRCOENS AUXHFRCORDY AUXHFRCOENS HFXORDY HFXOENS HFRCORDY HFRCOENS Bit Name Reset Access Description 31 15 Reserved To ensure co...

Page 112: ...t Bit Position 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 1 Access R R R R R R Name CALRDY AUXHFRCORDY LFXORDY LFRCORDY HFXORDY HFRCORDY Bit Name Reset Access Description 31 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 5 CALRDY 0 R Calibration Ready Interrupt Flag S...

Page 113: ...rrupt Flag 2 LFRCORDY 0 W1 LFRCO Ready Interrupt Flag Set Write to 1 to set the LFRCO Ready Interrupt Flag 1 HFXORDY 0 W1 HFXO Ready Interrupt Flag Set Write to 1 to set the HFXO Ready Interrupt Flag 0 HFRCORDY 0 W1 HFRCO Ready Interrupt Flag Set Write to 1 to set the HFRCO Ready Interrupt Flag 11 5 15 CMU_IFC Interrupt Flag Clear Register Offset Bit Position 0x038 31 30 29 28 27 26 25 24 23 22 21...

Page 114: ...me Reset Access Description 31 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 5 CALRDY 0 RW Calibration Ready Interrupt Enable Set to enable the Calibration Ready Interrupt 4 AUXHFRCORDY 0 RW AUXHFRCO Ready Interrupt Enable Set to enable the AUXHFRCO Ready Interrupt 3 LFXORDY 0 RW LFXO Ready Interrupt Enable Set to enable the LFXO ...

Page 115: ...I2C0 ADC0 VCMP GPIO DAC0 PRS ACMP1 ACMP0 TIMER2 TIMER1 TIMER0 UART0 USART2 USART1 USART0 Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 I2C0 0 RW I2C 0 Clock Enable Set to enable the clock for I2C0 14 ADC0 0 RW Analog to Digital Converter 0 Clock Enable Set to enable the clock for ADC0 13 VC...

Page 116: ...eserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 6 LFBPRESC0 0 R Low Frequency B Prescaler 0 Busy Used to check the synchronization status of CMU_LFBPRESC0 Value Description 1 CMU_LFBPRESC0 is busy synchronizing new value 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 4 ...

Page 117: ...e this bit to update several registers simultaneously Value Mode Description 0 UPDATE Each write access to a Low Frequency clock control register is updated into the Low Frequency domain as soon as possible 1 FREEZE The LE Clock Control registers are not updated with the new written value 11 5 21 CMU_LFACLKEN0 Low Frequency A Clock Enable Register 0 Async Reg Offset Bit Position 0x058 31 30 29 28 ...

Page 118: ...Async Reg Offset Bit Position 0x068 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x0 0x0 Access RW RW RW Name LCD LETIMER0 RTC Bit Name Reset Access Description 31 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 9 8 LCD 0x0 RW Liquid Crystal Display Controller Prescaler Configure L...

Page 119: ...LFACLKRTC LFACLK 32 6 DIV64 LFACLKRTC LFACLK 64 7 DIV128 LFACLKRTC LFACLK 128 8 DIV256 LFACLKRTC LFACLK 256 9 DIV512 LFACLKRTC LFACLK 512 10 DIV1024 LFACLKRTC LFACLK 1024 11 DIV2048 LFACLKRTC LFACLK 2048 12 DIV4096 LFACLKRTC LFACLK 4096 13 DIV8192 LFACLKRTC LFACLK 8192 14 DIV16384 LFACLKRTC LFACLK 16384 15 DIV32768 LFACLKRTC LFACLK 32768 11 5 24 CMU_LFBPRESC0 Low Frequency B Prescaler Register 0 A...

Page 120: ...Access Description 31 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 5 PCNT2CLKSEL 0 RW PCNT2 Clock Select This bit controls which clock that is used for the PCNT Value Mode Description 0 LFACLK LFACLK is clocking PCNT2 1 PCNT2S0 External pin PCNT2_S0 is clocking PCNT0 4 PCNT2CLKEN 0 RW PCNT2 Clock Enable This bit enables disables ...

Page 121: ...ion These bits control the voltage boost update frequency division Value Mode Description 0 DIV1 Voltage Boost update Frequency LFACLK 1 DIV2 Voltage Boost update Frequency LFACLK 2 2 DIV4 Voltage Boost update Frequency LFACLK 4 3 DIV8 Voltage Boost update Frequency LFACLK 8 4 DIV16 Voltage Boost update Frequency LFACLK 16 5 DIV32 Voltage Boost update Frequency LFACLK 32 6 DIV64 Voltage Boost upda...

Page 122: ...7 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name LOCKKEY Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 LOCKKEY 0x0000 RW Configuration Lock Key Write any other value than the unlock code to lock CMU_CTRL CMU_HFCORECLKDIV CMU_HFPERCLKDIV CMU_HFRCOCTRL CMU_LFRCOCTRL CM...

Page 123: ...bility The failure may e g be caused by an external event such as an ESD pulse or by a software failure 12 2 Features Clock input from selectable oscillators Internal 32 768 Hz RC oscillator Internal 1 kHz RC oscillator External 32 768 Hz XTAL oscillator Configurable timeout period from 9 to 256k watchdog clock cycles Individual selection to keep running or freeze when entering EM2 or EM3 Selectio...

Page 124: ... 3 3 Energy Mode Handling The watchdog timer can be configured to either keep on running or freeze when entering EM2 or EM3 The configuration is done individually for each energy mode in the EM2RUN and EM3RUN bits in WDOG_CTRL When the watchdog has been frozen and is re entering an energy mode where it is running the watchdog timer will continue counting where it left off For the watchdog there is...

Page 125: ...o 0 More information in Section 2 1 p 3 13 12 CLKSEL 0x0 RW Watchdog Clock Select Selects the WDOG oscillator i e the clock on which the watchdog will run Value Mode Description 0 ULFRCO ULFRCO 1 LFRCO LFRCO 2 LFXO LFXO 11 8 PERSEL 0xF RW Watchdog Timeout Period Select Select watchdog timeout period Value Description 0 Timeout period of 9 watchdog clock cycles 1 Timeout period of 17 watchdog clock...

Page 126: ...entered 4 LOCK 0 RW Configuration lock Set to lock the watchdog configuration This bit can only be cleared by reset Value Description 0 Watchdog configuration can be changed 1 Watchdog configuration cannot be changed 3 EM3RUN 0 RW Energy Mode 3 Run Enable Set to keep watchdog running in EM3 Value Description 0 Watchdog timer is frozen in EM3 1 Watchdog timer is running in EM3 2 EM2RUN 0 RW Energy ...

Page 127: ...0 UNCHANGED Watchdog timer is unchanged 1 CLEARED Watchdog timer is cleared to 0 12 5 3 WDOG_SYNCBUSY Synchronization Busy Register Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access R R Name CMD CTRL Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More i...

Page 128: ...are called producers The PRS routes these reflex signals to consumer peripherals which apply actions depending on the reflex signals received The format for the reflex signals is not given but edge triggers and other functionality can be applied by the PRS 13 2 Features 8 configurable interconnect channels Each channel can be connected to any producing peripheral Consumers can choose which channel...

Page 129: ...ning to the channel Figure 13 1 PRS Overview APB Interface Reg SIGSEL 2 0 APB bus Signals from producer peripherals Signals to consumer peripherals EDSEL 1 0 SWPULSE n SOURCESEL 5 0 SWLEVEL n 13 3 2 Producers Each PRS channel can choose between signals from several producers which is configured in SOURCESEL in PRS_CHx_CTRL Each of these producers outputs one or more signals which can be selected b...

Page 130: ...Level CC1 Output Level TIMER CC2 Output Level TX Complete Pulse UART RX Data Received Pulse TX Complete Pulse RX Data Received Pulse USART IrDA Decoder Output Level VCMP Comparator Output Level 13 3 3 Consumers Consumer peripherals listed in Table 13 2 p 130 can be set to listen to a PRS channel and perform an action based on the signal received on that channel Most consumers expect pulse input wh...

Page 131: ...channel 5 Set SOURCESEL in PRS_CH5_CTRL to 0b011100 to select TIMER0 as input to PRS channel 5 Set SIGSEL in PRS_CH5_CTRL to 0b001 to select the overflow signal from TIMER0 Configure ADC0 with the desired conversion set up Set SINGLEPRSEN in ADC0_SINGLECTRL to 1 to enable single conversions to be started by a high PRS input signal Set SINGLEPRSSEL in ADC0_SINGLECTRL to 0x5 to select PRS channel 5 ...

Page 132: ...on 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 W1 W1 Name CH7PULSE CH6PULSE CH5PULSE CH4PULSE CH3PULSE CH2PULSE CH1PULSE CH0PULSE Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 CH7PULSE 0 W1 Channel ...

Page 133: ...e bit 0 4 CH4LEVEL 0 RW Channel 4 Software Level See bit 0 3 CH3LEVEL 0 RW Channel 3 Software Level See bit 0 2 CH2LEVEL 0 RW Channel 2 Software Level See bit 0 1 CH1LEVEL 0 RW Channel 1 Software Level See bit 0 0 CH0LEVEL 0 RW Channel 0 Software Level The value in this register is XOR ed with the corresponding bit in the SWPULSE register and the selected PRS input signal to generate the channel o...

Page 134: ... 0b011100 TIMER0 Timer 0 0b011101 TIMER1 Timer 1 0b011110 TIMER2 Timer 2 0b101000 RTC Real Time Counter 0b101001 UART0 Universal Asynchronous Receiver Transmitter 0 0b110000 GPIOL General purpose Input Output 0b110001 GPIOH General purpose Input Output 15 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 0 SIGSEL 0x0 RW Signal Selec...

Page 135: ...1 TIMER2OF Timer 2 Overflow TIMER2OF 0b010 TIMER2CC0 Timer 2 Compare Capture 0 TIMER2CC0 0b011 TIMER2CC1 Timer 2 Compare Capture 1 TIMER2CC1 0b100 TIMER2CC2 Timer 2 Compare Capture 2 TIMER2CC2 SOURCESEL 0b101000 RTC 0b000 RTCOF RTC Overflow RTCOF 0b001 RTCCOMP0 RTC Compare 0 RTCCOMP0 0b010 RTCCOMP1 RTC Compare 1 RTCCOMP1 SOURCESEL 0b101001 UART0 0b001 UART0TXC USART 0 TX complete UART0TXC 0b010 UA...

Page 136: ...ped into the address bus of the Cortex M3 This enables seamless access from software without manually manipulating the IO settings each time a read or write is performed The data and address lines multiplexed in order to reduce the number of pins required to interface the external devices The bus timing is adjustable to meet specifications of the external devices The interface is limited to asynch...

Page 137: ... 8 bits of the EBI_AD lines while the data uses the lower 8 bits This mode is set by programming the MODE field in the EBI_CTRL register to D8A8 Read and write signals in 8 bit mode are shown in Figure 14 1 p 137 and Figure 14 2 p 137 respectively Figure 14 1 EBI Non multiplexed 8 bit Data 8 bit Address Read Operation ADDR 7 0 EBI_AD 15 8 RDSETUP 0 1 2 RDSTRB 1 2 3 EBI_CSn EBI_REn Z RDHOLD 0 1 2 Z...

Page 138: ...n the data is read or written according to operation Read and write signals are shown in Figure 14 4 p 138 and Figure 14 5 p 138 respectively Figure 14 4 EBI Multiplexed 16 bit Data 16 bit Address Read Operation ADDR 16 1 EBI_AD 15 0 EBI_ALE ADDRSETUP 1 2 3 Z DATA 15 0 EBI_CSn EBI_REn Z RDSETUP 0 1 2 RDSTRB 1 2 3 RDHOLD 0 1 2 Figure 14 5 EBI Multiplexed 16 bit Data 16 bit Address Write Operation A...

Page 139: ...ive for a number of internal clock cycles defined by ADDRSET bitfield in the EBI_ADDRTIMING register Similar timing can be defined by the RDSTRB bitfield in the EBI_RDTIMING register and WRSTRB in the EBI_WRTIMING register These parameters all have a minimum duration of 1 cycle which is set by HW in case the bitfield is programmed to 0 The setup and hold timing parameters are ADDRHOLD in the EBI_A...

Page 140: ...00000 0x7fffffff 0x12000000 EBI Region 1 32 MB EBI Region 2 32 MB 0x13ffffff 0x14000000 0x15ffffff 0x16000000 0x17ffffff 0x18000000 0x1fffffff EBI Region 3 128 MB EBI Region 0 64 MB 0x80000000 EBI Region 2 64 MB EBI Region 1 64 MB 0x83ffffff 0x84000000 0x87ffffff 0x88000000 0x8bffffff 0x8c000000 0x8fffffff EBI Region 3 64 MB EBI Regions 0x80000000 0xbfffffff 0xc0000000 0xffffffff 0x12000000 0x8fff...

Page 141: ...erpretation of the polarity of this signal can be configured with the ARDYPOL bit in EBI_POLARITY E g if the ARDYPOL is set to ACTIVELOW then the REn WEn cycle is extended while the ARDY line is kept low The ARDY functionality is enabled by setting the ARDYEN bit in the EBI_CTRL register It is also possible to enable a timeout check which generates a bus error if the ARDY is not deasserted within ...

Page 142: ... most energy friendly microcontrollers 2014 07 02 Gecko Family d0001_Rev1 30 142 www silabs com EBI_ALE pin is enabled by the ALEPEN bit and the EBI_ARDY pin is enabled by the ARDYPEN bit of the EBI_ROUTE register ...

Page 143: ..._RDTIMING3 RW Read Timing Register 3 0x040 EBI_WRTIMING3 RW Write Timing Register 3 0x044 EBI_POLARITY3 RW Polarity Register 3 0x048 EBI_PAGECTRL RW Page Control Register 0x04C EBI_NANDCTRL RW NAND Control Register 0x050 EBI_CMD W1 Command Register 0x054 EBI_STATUS R Status Register 0x058 EBI_ECCPARITY R ECC Parity register 0x05C EBI_TFTCTRL RW TFT Control Register 0x060 EBI_TFTSTATUS R TFT Status...

Page 144: ...bles the Byte Lane functionality for bank 2 Ignored when ITS 0 25 BL1 0 RW Byte Lane Enable for bank 1 Enables or disables the Byte Lane functionality for bank 1 Ignored when ITS 0 24 BL 0 RW Byte Lane Enable for bank 0 Enables or disables the Byte Lane functionality for bank 0 Applies to all banks when ITS 0 Applies to only bank 0 when ITS 1 23 ARDYTO3DIS 0 RW ARDY Timeout Disable for bank 3 Enab...

Page 145: ... bits can be enabled on EBI_A in the EBI_ROUTE register 3 D16 EBI_AD drives 16 bit data ALE not used Extended address bits can be enabled on EBI_A in the EBI_ROUTE register 5 4 MODE2 0x0 RW Mode 2 This field sets the access mode the EBI will use for interfacing devices on bank 2 Ignored when ITS 0 Value Mode Description 0 D8A8 EBI_AD drives 8 bit data 8 bit address ALE not used Extended address bi...

Page 146: ... To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 28 HALFALE 0 RW Half Cycle ALE Strobe Duration Enable Enables or disables half cycle duration of the ALE strobe in the last ADDRSETUP cycle 27 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 9 8 ADDRHOLD 0x3 RW Address Hold Time ...

Page 147: ... cycles the address setup before REn is asserted 14 5 4 EBI_WRTIMING Write Timing Register Offset Bit Position 0x00C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x3 0x3F 0x3 Access RW RW RW RW RW Name WBUFDIS HALFWE WRHOLD WRSTRB WRSETUP Bit Name Reset Access Description 31 30 Reserved To ensure compatibility with future devices always write bits...

Page 148: ...L 0 RW ARDY Polarity Sets the polarity of the EBI_ARDY line Value Mode Description 0 ACTIVELOW ARDY is active low 1 ACTIVEHIGH ARDY is active high 3 ALEPOL 0 RW Address Latch Polarity Sets the polarity of the EBI_ALE line Value Mode Description 0 ACTIVELOW ALE is active low 1 ACTIVEHIGH ALE is active high 2 WEPOL 0 RW Write Enable Polarity Sets the polarity of the EBI_WEn and EBI_NANDWEn lines Val...

Page 149: ...in Enable When set the EBI_DATAEN pin is enabled 24 TFTPEN 0 RW EBI_TFT Pin Enable When set the EBI_DCLK EBI_VSYNC and EBI_HSYNC pins are enabled 23 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 22 18 APEN 0x00 RW EBI_A Pin Enable Selects which non multiplexed address lines are enabled on EBI_A The lower bound L is set to 0 8 16 or ...

Page 150: ... EBI_BL 1 0 Pin Enable When set the EBI_BL 1 0 pins are enabled 6 ARDYPEN 0 RW EBI_ARDY Pin Enable When set the EBI_ARDY pin is enabled 5 ALEPEN 0 RW EBI_ALE Pin Enable When set the EBI_ALE pin is enabled 4 CS3PEN 0 RW EBI_CS3 Pin Enable When set the EBI_CS3 pin is enabled 3 CS2PEN 0 RW EBI_CS2 Pin Enable When set the EBI_CS2 pin is enabled 2 CS1PEN 0 RW EBI_CS1 Pin Enable When set the EBI_CS1 pin...

Page 151: ...Prefetch Enable Enables or disables prefetching of data from sequential address 28 HALFRE 0 RW Half Cycle REn Strobe Duration Enable Enables or disables half cycle duration of the REn strobe in the last RDSTRB cycle 27 18 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 17 16 RDHOLD 0x3 RW Read Hold Time Sets the number of cycles CSn i...

Page 152: ...ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 0 WRSETUP 0x3 RW Write Setup Time Sets the number of cycles the address setup before WEn is asserted 14 5 10 EBI_POLARITY1 Polarity Register 1 Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 Access RW RW RW RW RW RW ...

Page 153: ...t Access Description 31 29 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 28 HALFALE 0 RW Half Cycle ALE Strobe Duration Enable Enables or disables half cycle duration of the ALE strobe in the last address setup cycle 27 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3...

Page 154: ...ion in Section 2 1 p 3 1 0 RDSETUP 0x3 RW Read Setup Time Sets the number of cycles the address setup before REn is asserted 14 5 13 EBI_WRTIMING2 Write Timing Register 2 Offset Bit Position 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x3 0x3F 0x3 Access RW RW RW RW RW Name WBUFDIS HALFWE WRHOLD WRSTRB WRSETUP Bit Name Reset Access Descript...

Page 155: ...POL 0 RW ARDY Polarity Sets the polarity of the EBI_ARDY line Value Mode Description 0 ACTIVELOW ARDY is active low 1 ACTIVEHIGH ARDY is active high 3 ALEPOL 0 RW Address Latch Polarity Sets the polarity of the EBI_ALE line Value Mode Description 0 ACTIVELOW ALE is active low 1 ACTIVEHIGH ALE is active high 2 WEPOL 0 RW Write Enable Polarity Sets the polarity of the EBI_WEn and EBI_NANDWEn lines V...

Page 156: ...t to 0 1 cycle is inserted by HW 14 5 16 EBI_RDTIMING3 Read Timing Register 3 Offset Bit Position 0x03C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0x3 0x3F 0x3 Access RW RW RW RW RW RW Name PAGEMODE PREFETCH HALFRE RDHOLD RDSTRB RDSETUP Bit Name Reset Access Description 31 Reserved To ensure compatibility with future devices always write bits ...

Page 157: ...RSTRB cycle 27 18 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 17 16 WRHOLD 0x3 RW Write Hold Time Sets the number of cycles CSn is held active after the WEn is deasserted 15 14 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 13 8 WRSTRB 0x3F RW Write Strobe Time Sets ...

Page 158: ...nd EBI_NANDREn lines Value Mode Description 0 ACTIVELOW REn and NANDREn are active low 1 ACTIVEHIGH REn and NANDREn are active high 0 CSPOL 0 RW Chip Select Polarity Sets the polarity of the EBI_CSn line Value Mode Description 0 ACTIVELOW CSn is active low 1 ACTIVEHIGH CSn is active high 14 5 19 EBI_PAGECTRL Page Control Register Offset Bit Position 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 ...

Page 159: ...on 0x04C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 Access RW RW Name BANKSEL EN Bit Name Reset Access Description 31 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 5 4 BANKSEL 0x0 RW NAND Flash Bank This field sets the Memory Bank which is connected to a NAND Flash device Valu...

Page 160: ...bility with future devices always write bits to 0 More information in Section 2 1 p 3 13 TFTDDEMPTY 0 R EBI_TFTDD register is empty Indicates that EBI_TFTDD register is empty 12 DDACT 0 R EBI Busy with Direct Drive Transactions Indicates that EBI is busy with Direct Drive Transactions 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3...

Page 161: ...cess Description 31 25 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 24 RGBMODE 0 RW TFT RGB Mode This field sets TFT RGB Mode Value Mode Description 0 RGB565 RGB data is 565 1 RGB555 RGB data is 555 23 22 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 21 20 BANKSEL 0x...

Page 162: ...into an internal buffer Direct Drive address generation is based on the internal buffer Value Mode Description 0 VSYNC TFTFRAMEBASE is buffered on the vertical synchronization event EBI_VSYNC 1 HSYNC TFTFRAMEBASE is buffered on the horizontal synchronization event EBI_HSYNC 8 SHIFTDCLKEN 0 RW TFT EBI_DCLK Shift Enable When this bit is set EBI_DCLK edges are driven off the negative instead of the p...

Page 163: ...a frame initial line in vertical back porch has VCNT 0 15 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 0 HCNT 0x000 R Horizontal Count Contains the current pixel position within a line initial pixel in horizontal backporch has HCNT 0 14 5 26 EBI_TFTFRAMEBASE TFT Frame Base Register Offset Bit Position 0x064 31 30 29 28 27 26 ...

Page 164: ...6 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x000 0x000 Access RW RW Name VSZ HSZ Bit Name Reset Access Description 31 26 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 25 16 VSZ 0x000 RW Vertical Size excluding porches Sets the vertical size in lines Set to required size minus 1 15 10 Reserved To ensu...

Page 165: ...ion 2 1 p 3 6 0 HSYNC 0x00 RW Horizontal Synchronization Pulse Width Sets the horizontal synchronization pulse width Set to required width minus 1 Width is reduced in case HSYNCSTART 0 14 5 30 EBI_TFTVPORCH TFT Vertical Porch Register Offset Bit Position 0x074 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x00 0x00 Access RW RW RW Name VBPORCH VFP...

Page 166: ... information in Section 2 1 p 3 22 12 TFTSTART 0x000 RW TFT Direct Drive Transaction Start Sets the starting position of the External Direct Drive Transaction relative to the DCLK inactive edge 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 0 DCLKPERIOD 0x000 RW TFT Direct Drive Transaction EBI_DCLK Period Sets the Direct Drive...

Page 167: ... Sets the polarity of the EBI_CSTFT line Value Mode Description 0 ACTIVELOW CSTFT is active low 1 ACTIVEHIGH CSTFT is active high 14 5 33 EBI_TFTDD TFT Direct Drive Data Register Offset Bit Position 0x080 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name DATA Bit Name Reset Access Description 31 16 Reserved To ensure compatibility wit...

Page 168: ...Reset 0x0000 Access RW Name DATA Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 DATA 0x0000 RW RGB data Sets the RGB data value according to the format defined in RGBMODE 14 5 36 EBI_TFTPIXEL1 TFT Pixel 1 Register Offset Bit Position 0x08C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15...

Page 169: ...ation according to the format defined in RGBMODE 14 5 38 EBI_TFTMASK TFT Masking Register Offset Bit Position 0x094 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name TFTMASK Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 TFTMA...

Page 170: ...et Register Offset Bit Position 0x09C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 Name DDJIT DDEMPTY VFPORCH VBPORCH HSYNC VSYNC Bit Name Reset Access Description 31 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 5 DDJIT 0 W1 Direct Drive Jitter In...

Page 171: ...rch interrupt flag 1 HSYNC 0 W1 Horizontal Sync Interrupt Flag Clear Write to 1 to clear Horizontal Sync interrupt flag 0 VSYNC 0 W1 Vertical Sync Interrupt Flag Clear Write to 1 to clear Vertical Sync interrupt flag 14 5 42 EBI_IEN Interrupt Enable Register Offset Bit Position 0x0A4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 Access RW R...

Page 172: ...s 2014 07 02 Gecko Family d0001_Rev1 30 172 www silabs com Bit Name Reset Access Description Set to enable interrupt on Horizontal Sync interrupt flag 0 VSYNC 0 RW Vertical Sync Interrupt Enable Set to enable interrupt on Vertical Sync interrupt flag ...

Page 173: ...and slave and supports multi master buses Standard mode fast mode and fast mode plus speeds are supported allowing transmission rates all the way from 10 kbit s up to 1 Mbit s Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system The interface provided to software by the I 2 C module allows both fine grained control of the transmission process and cl...

Page 174: ...s collision detection and arbitration to resolve situations where multiple masters transmit data at the same time without data loss Figure 15 2 I 2 C Bus Example I2 C master 1 I2 C master 2 I2 C slave 1 I2 C slave 2 I2 C slave 3 SDA SCL VDD Rp Each device on the bus is addressable by a unique address and an I 2 C master can address all the devices on the bus including other masters Both the bus li...

Page 175: ...n Figure 15 2 p 174 Figure 15 4 I 2 C Bit Transfer on I 2 C Bus SCL SDA Data stable Data change allowed Data change allowed 15 3 1 2 Bus Transfer When a master wants to initiate a transfer on the bus it waits until the bus is idle and transmits a START condition on the bus The master then transmits the address of the slave it wishes to interact with and a single R W bit telling whether it wishes t...

Page 176: ...Figure 15 7 I 2 C Single Byte Write then Repeated Start and Single Byte Read R Sr ADDR DATA A N P W S ADDR DATA A A 15 3 1 3 Addresses I 2 C supports both 7 bit and 10 bit addresses When using 7 bit addresses the first byte transmitted after the START condition contains the address of the slave that the master wants to contact In the 7 bit address space several addresses are reserved These address...

Page 177: ... transmitted is shown in Figure 15 9 p 177 Figure 15 9 I 2 C Master Receiver Slave Transmitter with 10 bit Address R Sr DATA A N P W S A A ADDR 1st 7 bits Addr 2nd byte ADDR 1st 7 bits 15 3 1 5 Arbitration Clock Synchronization Clock Stretching Arbitration and clock synchronization are features aimed at allowing multi master buses Arbitration occurs when two devices try to drive the bus at the sam...

Page 178: ...high Nhigh CLKDIV 1 fHFPERCLK Tlow Nlow CLKDIV 1 fHFPERCLK 15 3 Equation 15 3 p 178 and Equation 15 2 p 178 does not apply for low clock division factors 0 1 and 2 because of synchronization For these clock division factors the formulas for computing high and low periods of the clock signal are given in Table 15 2 p 178 Table 15 2 I 2 C High and Low Periods for Low CLKDIV CLKDIV Standard 4 4 Asymm...

Page 179: ...sensed value is different than the value the I 2 C module tried to output it is interpreted as a simultaneous transmission by another device and that the I 2 C module has lost arbitration Whenever arbitration is lost the ARBLOST interrupt flag in I2Cn_IF is set any lines held are released and the I 2 C device goes idle If an I 2 C master loses arbitration during the transmission of an address anot...

Page 180: ...Otherwise the byte waits in the shift register until space becomes available in the buffer When a byte becomes available in the receive buffer the RXDATAV in I2Cn_STATUS and RXDATAV interrupt flag in I2Cn_IF are set The data can now be fetched from the buffer using I2Cn_RXDATA Reading from this register will pull a byte out of the buffer making room for a new byte and clearing RXDATAV in I2Cn_STAT...

Page 181: ... state machine ending the operation or continuing with a new operation when arriving at the right side of the state machine Branches in the path through the state machine are the results of bus events and choices made by software either directly or indirectly The dotted lines show where I 2 C specific interrupt flags are set along the path and the full drawn circles show places where interaction m...

Page 182: ...ossible from a given state the course of action using the highest priority interactions that first has everything it is waiting for is the one that is taken Table 15 4 I 2 C Interactions in Prioritized Order Interaction Priority Software action Automatically continues if STOP 1 Set the STOP command bit in I2Cn_CMD PSTOP is set STOP pending in I2Cn_STATUS ABORT 2 Set the ABORT command bit in I2Cn_C...

Page 183: ...s with little activity the time before the I 2 C module detects that the bus is idle can be significant There are two ways of assuring that the I 2 C module gets out of the busy state Use the ABORT command in I2Cn_CMD When the ABORT command is issued the I 2 C module is instructed that the bus is idle The I 2 C module can then initiate master operations Use the Bus Idle Timeout When SCL has been h...

Page 184: ...n this case the ARBLOST interrupt flag in I2Cn_IF is set If the arbitration was lost during the transfer of an address and SLAVE in I2Cn_CTRL is set the master then checks which address was transmitted If it was the address of the master then the master goes to slave mode After a master has transmitted a START and won any arbitration it owns the bus until it transmits a STOP After a STOP the bus i...

Page 185: ...e data register thus has to contain the 7 bit slave address in the 7 most significant bits of the byte and have the least significant bit set When the address has been transmitted the master receives an ACK or a NACK If an ACK is received the ACK interrupt flag in I2Cn_IF is set and if space is available in the receive shift register reception of a byte from the slave begins If the receive buffer ...

Page 186: ...when bus becomes idle ADDR R transmitted TXBL interrupt flag TXC interrupt flag None RXDATA Start receiving STOP STOP will be sent and the bus released START Repeated START will be sent 0x93 ADDR R transmitted ACK received ACK interrupt flag BUSHOLD STOP START STOP will be sent and the bus released Then a START will be sent when the bus becomes idle CONT RXDATA Continue start receiving STOP STOP w...

Page 187: ... been received ADDRACK 4 Address ACK NACK being transmitted or received DATA 5 Data being transmitted or received DATAACK 6 Data ACK NACK being transmitted or received Table 15 8 I 2 C Transmission Status Bit Description BUSY Set whenever there is activity on the bus Whether or not this module is responsible for the activity cannot be determined by this byte MASTER Set when operating as a master C...

Page 188: ...ergy modes except EM4 The slave address i e the address which the I 2 C module should be addressed with is defined in the I2Cn_SADDR register In addition to the address a mask must be specified telling the address comparator which bits of an incoming address to compare with the address defined in I2Cn_SADDR The mask is defined in I2Cn_SADDRMASK and for every zero in the mask the corresponding bit ...

Page 189: ...command The slave will in that case go to an idle state and wait for the next start condition To continue the transmission the slave must make sure data is loaded into the transmit buffer and send an ACK The loaded data will then be transmitted to the master and an ACK or NACK will be received from the master Data transmission can also continue after a NACK if a CONT command is issued along with t...

Page 190: ...n that the address transmitted by the master has the R W bit cleared W indicating that the master wishes to write to the slave The slave then goes into slave receiver mode To receive data from the master the slave should respond to the address with an ACK and make sure space is available in the receive buffer Transmission will then continue and the slave will receive a byte from the master If a NA...

Page 191: ...up to complete transfers with a minimal amount of interaction 15 3 10 1 DMA DMA can be used to automatically load data into the transmit buffer and load data out from the receive buffer When using DMA software is thus relieved of moving data to and from memory after each transferred byte 15 3 10 2 Automatic ACK When AUTOACK in I2Cn_CTRL is set an ACK is sent automatically whenever an ACK interacti...

Page 192: ... can be set in I2Cn_CMD to help resolve bus errors When the bus for some reason is locked up and the I 2 C module is in the middle of a transmission it cannot get out of or for some other reason the I 2 C wants to abort a transmission the ABORT command can be used Setting the ABORT command will make the I 2 C module discard any data currently being transmitted or received release the SDA and SCL l...

Page 193: ...meout BITO in I2Cn_CTRL can be used to detect situations where the bus goes idle in the middle of a transmission The timeout can be configured in BITO and when the bus has been idle for the given amount of time the BITO interrupt flag in I2Cn_IF is set The bus can also be set idle automatically on a bus idle timeout This is enabled by setting GIBITO in I2Cn_CTRL When the bus idle timer times out i...

Page 194: ...errupts generated by the I 2 C module are combined into one interrupt vector I2C_INT If I 2 C interrupts are enabled an interrupt will be made if one or more of the interrupt flags in I2Cn_IF and their corresponding bits in I2Cn_IEN are set 15 3 15 Wake up The I 2 C receive section can be active all the way down to energy mode EM3 and can wake up the CPU on address interrupt All address match mode...

Page 195: ...26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0x0 0x0 0 0 0 0 0 0 0 Access RW RW RW RW RW RW RW RW RW RW RW Name CLTO GIBITO BITO CLHR GCAMEN ARBDIS AUTOSN AUTOSE AUTOACK SLAVE EN Bit Name Reset Access Description 31 19 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 18 16 CLTO 0x0 RW Clock Low Tim...

Page 196: ...ts to 0 More information in Section 2 1 p 3 9 8 CLHR 0x0 RW Clock Low High Ratio Determines the ratio between the low and high parts of the clock signal generated on SCL as master Value Mode Description 0 STANDARD The ratio between low period and high period counters Nlow Nhigh is 4 4 1 ASYMMETRIC The ratio between low period and high period counters Nlow Nhigh is 6 3 2 FAST The ratio between low ...

Page 197: ...START Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 CLEARPC 0 W1 Clear Pending Commands Set to clear pending commands 6 CLEARTX 0 W1 Clear TX Set to clear transmit buffer and shift register Will not abort ongoing transfer 5 ABORT 0 W1 Abort transmission Abort the current transmission making t...

Page 198: ...the bus is currently being held by this I 2 C module 3 NACKED 0 R Nack Received Set if a NACK was received and STATE is ADDRACK or DATAACK 2 TRANSMITTER 0 R Transmitter Set when operating as a master transmitter or a slave transmitter When cleared the system may be operating as a master receiver a slave receiver or the current mode is not known 1 MASTER 0 R Master Set when operating as an I 2 C ma...

Page 199: ...ng and will be transmitted as soon as possible 2 PACK 0 R Pending ACK An acknowledge is pending and will be transmitted as soon as possible 1 PSTOP 0 R Pending STOP A stop condition is pending and will be transmitted as soon as possible 0 PSTART 0 R Pending START A start condition is pending and will be transmitted as soon as possible 15 5 5 I2Cn_CLKDIV Clock Division Register Offset Bit Position ...

Page 200: ...ed To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 1 MASK 0x00 RW Slave Address Mask Specifies the significant bits of the slave address Setting the mask to 0x00 will match all addresses while setting it to 0x7F will only match the exact address specified by ADDR 0 Reserved To ensure compatibility with future devices always write bits to 0 M...

Page 201: ...ess W Name TXDATA Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 TXDATA 0x00 W TX Data Use this register to write a byte to the transmit buffer 15 5 11 I2Cn_IF Interrupt Flag Register Offset Bit Position 0x028 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ...

Page 202: ...NACK 0 R Not Acknowledge Received Interrupt Flag Set when a NACK has been received 6 ACK 0 R Acknowledge Received Interrupt Flag Set when an ACK has been received 5 RXDATAV 0 R Receive Data Valid Interrupt Flag Set when data is available in the receive buffer Cleared automatically when the receive buffer is read 4 TXBL 1 R Transmit Buffer Level Interrupt Flag Set when the transmit buffer becomes e...

Page 203: ...t Not Acknowledge Received Interrupt Flag Write to 1 to set the NACK interrupt flag 6 ACK 0 W1 Set Acknowledge Received Interrupt Flag Write to 1 to set the ACK interrupt flag 5 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 TXC 0 W1 Set Transfer Completed Interrupt Flag Write to 1 to set the TXC interrupt flag 2 ADDR 0 W1 Set Ad...

Page 204: ...upt Flag Write to 1 to clear the NACK interrupt flag 6 ACK 0 W1 Clear Acknowledge Received Interrupt Flag Write to 1 to clear the ACK interrupt flag 5 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 TXC 0 W1 Clear Transfer Completed Interrupt Flag Write to 1 to clear the TXC interrupt flag 2 ADDR 0 W1 Clear Address Interrupt Flag ...

Page 205: ...rupt when not acknowledge is received 6 ACK 0 RW Acknowledge Received Interrupt Enable Enable interrupt on acknowledge received 5 RXDATAV 0 RW Receive Data Valid Interrupt Enable Enable interrupt on receive buffer full 4 TXBL 0 RW Transmit Buffer level Interrupt Enable Enable interrupt on transmit buffer level 3 TXC 0 RW Transfer Completed Interrupt Enable Enable interrupt on transfer completed 2 ...

Page 206: ...location of the I 2 C I O pins Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 7 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 SCLPEN 0 RW SCL Pin Enable When set the SCL pin of the I 2 C is enabled 0 SDAPEN 0 RW SDA Pin Enable When set the SDA pin of the I 2 C is enabled ...

Page 207: ... the MCU remains in EM1 16 1 Introduction The Universal Synchronous Asynchronous serial Receiver and Transmitter USART is a very flexible serial I O module It supports full duplex asynchronous UART communication as well as RS 485 SPI MicroWire and 3 wire It can also interface with ISO7816 SmartCards and IrDA devices 16 2 Features Asynchronous and synchronous SPI communication Full duplex and half ...

Page 208: ... UART Control and status Peripheral Bus Baud rate generator USn_CLK Pin ctrl USn_CS U S n_RX IrDA modulator IrDA demodulator RXBLOCK 16 3 1 Modes of Operation The USART operates in either asynchronous or synchronous mode In synchronous mode a separate clock signal is transmitted with the data This clock signal is generated by the bus master and both the master and slave sample and transmit data ac...

Page 209: ...Data in Data out Clock in Slave select 1 0 1 Data out Data in Clock out Auto slave select 1 1 0 Data out in Clock in Slave select 1 1 1 Data out in Clock out Auto slave select 16 3 2 Asynchronous Operation 16 3 2 1 Frame Format The frame format used in asynchronous mode consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error checking A frame sta...

Page 210: ...inverted by setting TXINV in USARTn_CTRL and the format expected by the receiver can be inverted by setting RXINV in USARTn_CTRL These bits affect the entire frame not only the data bits An inverted frame has a low idle state a high start bit inverted data and parity bits and low stop bits 16 3 2 1 1 Parity bit Calculation and Handling When parity bits are enabled hardware automatically calculates...

Page 211: ...w the USART clock to be controlled more accurately than what is possible with a standard integral divider The clock divider used in the USART is a 15 bit value with a 13 bit integral part and a 2 bit fractional part The fractional part is configured in the two LSBs of DIV in USART_CLKDIV The lowest achievable baud rate at 32 MHz is about 244 bauds sec Fractional clock division is implemented by di...

Page 212: ...o become available Transmission is enabled through the command register USARTn_CMD by setting TXEN and disabled by setting TXDIS in the same command register When the transmitter is disabled using TXDIS any ongoing transmission is aborted and any frame currently being transmitted is discarded When disabled the TX output goes to an idle state which by default is a high value Whether or not the tran...

Page 213: ...y Both the TXBL status flag and the TXBL interrupt flag are cleared automatically when their condition becomes false The transmit buffer including the transmit shift register can be cleared by setting CLEARTX in USARTn_CMD This will prevent the USART from transmitting the data in the buffer and shift register and will make them available for new data Any frame currently being transmitted will not ...

Page 214: ... the RXDATAV flag in USARTn_STATUS and the RXDATAV interrupt flag in USARTn_IF are set and when the buffer becomes full RXFULL in USARTn_STATUS and the RXFULL interrupt flag in USARTn_IF are set The status flags RXDATAV and RXFULL are automatically cleared by hardware when their condition is no longer true This also goes for the RXDATAV interrupt flag but the RXFULL interrupt flag must be cleared ...

Page 215: ...fer RXBLOCK must be cleared in the instant a frame is fully received by the receiver RXBLOCK is set by setting RXBLOCKEN in USARTn_CMD and disabled by setting RXBLOCKDIS also in USARTn_CMD There is one exception where data is loaded into the receive buffer even when RXBLOCK is set This is when an address frame is received when operating in multi processor mode See Section 16 3 2 8 p 221 for more i...

Page 216: ...ition 3 as shown in Figure 16 5 p 216 If the value of the start bit is found to be high the reception of the frame is aborted filtering out false start bits possibly generated by noise on the input Figure 16 5 USART Sampling of Start and Data Bits 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 Idle Start bit Bit 0 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 13 7 12 OVS 0 OVS 1 0 1 2 3 4 5 6 ...

Page 217: ...DOUBLEX or USARTn_RXDOUBLEXP registers If ERRSTX in USARTn_CTRL is set the transmitter is disabled on received parity and framing errors If ERRSRX in USARTn_CTRL is set the receiver is disabled on parity and framing errors 16 3 2 4 5 Framing Error and Break Detection A framing error is the result of an asynchronous frame where the stop bit was sampled to a value of 0 This can be the result of nois...

Page 218: ... also in USARTn_CMD must be set to enable transmitter output again Whether or not the output is tristated at a given time can be read from TXTRI in USARTn_STATUS If TXTRI is set when transmitting data the data is shifted out of the shift register but is not put out on U S n_TX When operating a half duplex data bus it is common to have a bus master which first transmits a request to one of the bus ...

Page 219: ...o be used for automatic chip slave select when in synchronous mode e g SPI 16 3 2 6 3 Two Data links Some limited devices only support half duplex communication even though two data links are available In this case software is responsible for making sure data is not transmitted when incoming data is expected 16 3 2 7 Large Frames As each frame in the transmit and receive buffers holds a maximum of...

Page 220: ...heral Bus 2 1 0 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 0 1 2 Figure 16 10 p 220 illustrates the order of the transmitted bits when an 11 bit frame is transmitted with MSBF set If MSBF is set and the frame is smaller than 10 bits only the contents of transmit buffer 0 will be transmitted When receiving a large frame BYTESWAP in USARTn_CTRL determines the order the way the large frame is split into the two...

Page 221: ...Tn_STATUS Multi processor mode is enabled by setting MPM in USARTn_CTRL and the value of the 9th bit in address frames can be set in MPAB Note that the receiver must be enabled for address frames to be detected The receiver can be blocked however preventing data from being loaded into the receive buffer while looking for address frames Example 16 1 p 221 explains basic usage of the multi processor...

Page 222: ...pports the ISO 7816 I O line T0 mode With exception of the stop bits guard time the 7816 data frame is equal to the regular asynchronous frame In this mode the receiver pulls the line low for one baud half a baud into the guard time to indicate a parity error This NAK can for instance be used by the transmitter to re transmit the frame SmartCard mode is a half duplex asynchronous mode so the trans...

Page 223: ...NACK ed frame The transmitter will retransmit the frame until it is ACK ed by the receiver This only works when the number of databits in a frame is configured to 8 Set SKIPPERRF in USARTn_CTRL to make the receiver discard frames with parity errors The PERR interrupt flag in USARTn_IF is set when a frame is discarded because of a parity error Figure 16 14 USART SmartCard Stop Bit Sampling 13 14 15...

Page 224: ... bit fractional part USART Synchronous Mode Bit Rate br fHFPERCLK 2 x 1 USARTn_CLKDIV 256 16 3 Given a desired baud rate brdesired the clock divider USARTn_CLKDIV can be calculated using Equation 16 4 p 224 USART Synchronous Mode Clock Division Factor USARTn_CLKDIV 256 x fHFPERCLK 2 x brdesired 1 16 4 When the USART operates in master mode the highest possible bit rate is half the peripheral clock...

Page 225: ...ter shifts bits out from the transmit shift register using the internal clock When there are no more frames in the transmit buffer and the transmit shift register is empty the clock stops and communication ends When the receiver is enabled it samples data using the internal clock when the transmitter transmits data Operation of the RX and TX buffers is as in asynchronous mode 16 3 3 3 1 Operation ...

Page 226: ...hen it is not transmitting data i e it must provide the slave with a clock to receive data To generate the bus clock the master should transmit data with the transmitter tristated i e TXTRI in USARTn_STATUS set when receiving data If 2 bytes are expected from the slave then transmit 2 bytes with the transmitter tristated and the slave uses the generated bus clock to transmit data to the master TXT...

Page 227: ...ng the transmission delay a transmission can be started when a frame is received and it is possible to make sure that the transmitter does not begin driving the output before the frame on the bus is completely transmitted TXDELAY in USARTn_CTRL only applies to asynchronous transmission 16 3 7 Interrupts The interrupts generated by the USART are combined into two interrupt vectors Interrupts relate...

Page 228: ...the IrDA modulator The width of the pulses generated by the IrDA modulator is set by configuring IRPW in USARTn_IRCTRL Four pulse widths are available each defined relative to the configured bit period as listed in Table 16 9 p 228 Table 16 9 USART IrDA Pulse Widths IRPW Pulse width OVS 0 Pulse width OVS 1 Pulse width OVS 2 Pulse width OVS 3 00 1 16 1 8 1 6 1 4 01 2 16 2 8 2 6 N A 10 3 16 3 8 N A ...

Page 229: ...EX W TX Buffer Double Data Extended Register 0x03C USARTn_TXDOUBLE W TX Buffer Double Data Register 0x040 USARTn_IF R Interrupt Flag Register 0x044 USARTn_IFS W1 Interrupt Flag Set Register 0x048 USARTn_IFC W1 Interrupt Flag Clear Register 0x04C USARTn_IEN RW Interrupt Enable Register 0x050 USARTn_IRCTRL RW IrDA Control Register 0x054 USARTn_ROUTE RW I O Routing Register 16 5 Register Description ...

Page 230: ...equests from the USART 1 DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set 21 BIT8DV 0 RW Bit 8 Default Value The default value of the 9th bit If 9 bit frames are used and an 8 bit write operation is done leaving the 9th bit unspecified the 9th bit is set to the value of BIT8DV 20 SKIPPERRF 0 RW Skip Parity Error Frames When set the receiver discards frames wit...

Page 231: ...is sent with the least significant bit first 1 Data is sent with the most significant bit first 9 CLKPHA 0 RW Clock Edge For Setup Sample Determines where data is set up and sampled according to the bus clock when in synchronous mode Value Mode Description 0 SAMPLELEADING Data is sampled on the leading edge and set up on the trailing edge of the bus clock in synchronous mode 1 SAMPLETRAILING Data ...

Page 232: ...tes in asynchronous mode 1 The USART operates in synchronous mode 16 5 2 USARTn_FRAME USART Frame Format Register Offset Bit Position 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x1 0x0 0x5 Access RW RW RW Name STOPBITS PARITY DATABITS Bit Name Reset Access Description 31 14 Reserved To ensure compatibility with future devices always write bits...

Page 233: ...ol register Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x0 Access RW RW RW Name TXTEN RXTEN TSEL Bit Name Reset Access Description 31 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 5 TXTEN 0 RW Transmit Trigger Enable When set the PRS channel selected by...

Page 234: ...TRIEN 0 W1 Transmitter Tristate Enable Tristates the transmitter output 7 RXBLOCKDIS 0 W1 Receiver Block Disable Set to clear RXBLOCK resulting in all incoming frames being loaded into the receive buffer 6 RXBLOCKEN 0 W1 Receiver Block Enable Set to set RXBLOCK resulting in all incoming frames being discarded 5 MASTERDIS 0 W1 Master Disable Set to disable master mode clearing the MASTER status bit...

Page 235: ...ransmit buffer is empty and if TXBIL is set TXBL is set whenever the transmit buffer is half full or empty 5 TXC 0 R TX Complete Set when a transmission has completed and no more data is available in the transmit buffer and shift register Cleared when data is written to the transmit buffer 4 TXTRI 0 R Transmitter Tristated Set when the transmitter is tristated and cleared when transmitter output i...

Page 236: ...ways write bits to 0 More information in Section 2 1 p 3 15 FERR 0 R Data Framing Error Set if data in buffer has a framing error Can be the result of a break condition 14 PERR 0 R Data Parity Error Set if data in buffer has a parity error asynchronous mode only 13 9 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 8 0 RXDATA 0x000 R R...

Page 237: ...p 3 24 16 RXDATA1 0x000 R RX Data 1 Second frame read from buffer 15 FERR0 0 R Data Framing Error 0 Set if data in buffer has a framing error Can be the result of a break condition 14 PERR0 0 R Data Parity Error 0 Set if data in buffer has a parity error asynchronous mode only 13 9 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 8 0 R...

Page 238: ...formation in Section 2 1 p 3 8 0 RXDATAP 0x000 R RX Data Peek Use this register to access data read from the USART 16 5 12 USARTn_RXDOUBLEXP RX Buffer Double Data Extended Peek Register Offset Bit Position 0x02C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x000 0 0 0x000 Access R R R R R R Name FERRP1 PERRP1 RXDATAP1 FERRP0 PERRP0 RXDATAP0 Bit Na...

Page 239: ...X After Transmission Set to enable reception after transmission 14 TXDISAT 0 W Clear TXEN After Transmission Set to disable transmitter and release data bus directly after transmission 13 TXBREAK 0 W Transmit Data As Break Set to send data as a break Recipient will see a framing error or a break condition depending on its configuration and the value of WDATA 12 TXTRIAT 0 W Set TXTRI After Transmis...

Page 240: ...ent will see a framing error or a break condition depending on its configuration and the value of USARTn_WDATA 28 TXTRIAT1 0 W Set TXTRI After Transmission Set to tristate transmitter by setting TXTRI after transmission 27 UBRXAT1 0 W Unblock RX After Transmission Set clear RXBLOCK after transmission unblocking the receiver 26 25 Reserved To ensure compatibility with future devices always write bi...

Page 241: ...bility with future devices always write bits to 0 More information in Section 2 1 p 3 12 CCF 0 R Collision Check Fail Interrupt Flag Set when a collision check notices an error in the transmitted data 11 SSM 0 R Slave Select In Master Mode Interrupt Flag Set when the device is selected as a slave when in master mode 10 MPAF 0 R Multi Processor Address Frame Interrupt Flag Set when a multi processo...

Page 242: ... Description 31 13 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 12 CCF 0 W1 Set Collision Check Fail Interrupt Flag Write to 1 to set the CCF interrupt flag 11 SSM 0 W1 Set Slave Select in Master mode Interrupt Flag Write to 1 to set the SSM interrupt flag 10 MPAF 0 W1 Set Multi Processor Address Frame Interrupt Flag Write to 1 to ...

Page 243: ...lag Write to 1 to clear the FERR interrupt flag 8 PERR 0 W1 Clear Parity Error Interrupt Flag Write to 1 to clear the PERR interrupt flag 7 TXUF 0 W1 Clear TX Underflow Interrupt Flag Write to 1 to clear the TXUF interrupt flag 6 TXOF 0 W1 Clear TX Overflow Interrupt Flag Write to 1 to clear the TXOF interrupt flag 5 RXUF 0 W1 Clear RX Underflow Interrupt Flag Write to 1 to clear the RXUF interrup...

Page 244: ...F 0 RW RX Underflow Interrupt Enable Enable interrupt on RX underflow 4 RXOF 0 RW RX Overflow Interrupt Enable Enable interrupt on RX overflow 3 RXFULL 0 RW RX Buffer Full Interrupt Enable Enable interrupt on RX Buffer full 2 RXDATAV 0 RW RX Data Valid Interrupt Enable Enable interrupt on RX data 1 TXBL 0 RW TX Buffer Level Interrupt Enable Enable interrupt on TX buffer level 0 TXC 0 RW TX Complet...

Page 245: ...WO IrDA pulse width is 2 16 for OVS 0 and 2 8 for OVS 1 2 THREE IrDA pulse width is 3 16 for OVS 0 and 3 8 for OVS 1 3 FOUR IrDA pulse width is 4 16 for OVS 0 and 4 8 for OVS 1 0 IREN 0 RW Enable IrDA Module Enable IrDA module and rout USART signals through it 16 5 22 USARTn_ROUTE I O Routing Register Offset Bit Position 0x054 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7...

Page 246: ... pin of the USART is enabled Value Description 0 The USn_CS pin is disabled 1 The USn_CS pin is enabled 1 TXPEN 0 RW TX Pin Enable When set the TX MOSI pin of the USART is enabled Value Description 0 The U S n_TX MOSI pin is disabled 1 The U S n_TX MOSI pin is enabled 0 RXPEN 0 RW RX Pin Enable When set the RX MISO pin of the USART is enabled Value Description 0 The U S n_RX MISO pin is disabled 1...

Page 247: ...EM1 17 1 Introduction The Universal Asynchronous serial Receiver and Transmitter UART is a very flexible serial I O module It supports full and half duplex asynchronous UART communication 17 2 Features Full duplex and half duplex Separate TX RX enable Separate receive transmit 2 level buffers with additional separate shift registers Programmable baud rate generated as an fractional division from t...

Page 248: ...HA in USARTn_CTRL and MASTEREN in USARTn_STATUS are always 0 Transmission direction Always LSB first MSBF in USARTn_CTRL is always 0 Chip select Not available AUTOCS in USARTn_CTRL is always 0 SmartCard mode Not available SCMODE in USARTn_CTRL is always 0 Frame size Limited to 8 9 databits Other configurations of DATABITS in USARTn_FRAME are not possible IrDA Not available IREN in USARTn_IRCTRL is...

Page 249: ...low energy mode EM2 with most core functionality turned off the LEUART can wait for an incoming UART frame while having an extremely low energy consumption When a UART frame is completely received the CPU can quickly be woken up Alternatively multiple frames can be transferred via the Direct Memory Access DMA module into RAM memory before waking up the CPU Received data can optionally be blocked u...

Page 250: ...one bit period This signals the start of a frame and is used for synchronization Following the start bit are 8 or 9 data bits and an optional parity bit The data is transmitted with the least significant bit first Finally a number of stop bits where the line is driven high end the frame The frame format is shown in Figure 18 2 p 250 Figure 18 2 LEUART Asynchronous Frame Format S 0 1 2 3 4 5 6 7 8 ...

Page 251: ...UART clock defines the transmission and reception data rate The clock generator employs a fractional clock divider to allow baud rates that are not attainable by integral division of the 32 768 kHz clock that drives the LEUART The clock divider used in the LEUART is a 12 bit value with a 7 bit integral part and a 5 bit fractional part The baud rate of the LEUART is given by LEUART Baud Rate Equati...

Page 252: ... is idle The TXC status flag is cleared when a new byte becomes available for transmission but the TXC interrupt flag must be cleared by software 18 3 4 1 Transmit Buffer Operation A frame can be loaded into the transmit buffer by writing to LEUARTn_TXDATA or LEUARTn_TXDATAX Using LEUARTn_TXDATA allows 8 bits to be written to the buffer If 9 bit frames are used the 9th bit will in that case be set...

Page 253: ...receiver is enabled after the frame has been fully transmitted It is enabled in time to detect a start bit directly after the last stop bit has been transmitted The transmission control bits in the LEUART cannot tristate the transmitter This is performed automatically by hardware however if AUTOTRI in LEUARTn_CTRL is set See Section 18 3 7 p 257 for more information on half duplex operation 18 3 4...

Page 254: ...ignificant bits of the received frame while LEUARTn_RXDATAX must be used to get access to the 9th most significant bit The latter register also contains status information regarding the frame When a frame is read from the receive buffer using LEUARTn_RXDATA or LEUARTn_RXDATAX the frame is removed from the buffer making room for a new one If an attempt is done to read more frames from the buffer th...

Page 255: ...hen space becomes available even if RXBLOCK is set at that time The overflow interrupt flag RXOF in LEUARTn_IF will be set if a frame in the receive shift register waiting to be loaded into the receive buffer is overwritten by an incoming frame even though RXBLOCK is set 18 3 5 3 Data Sampling The receiver samples each incoming baud as close as possible to the middle of the baud period Except for ...

Page 256: ... When a start frame is detected the block is cleared and frames received from that point including the start frame are loaded into the receive buffer An incoming start frame results in the STARTF interrupt flag in LEUARTn_IF being set regardless of the value of SFUBRX in LEUARTn_CTRL This allows an interrupt to be made when the start frame is detected When 8 data bit frame formats are used only th...

Page 257: ...tion on a correctly configured incoming frame An address frame with a parity error or a framing error is not detected as an address frame 18 3 6 Loopback The LEUART receiver samples LEUn_RX by default and the transmitter drives LEUn_TX by default This is not the only configuration however When LOOPBK in LEUARTn_CTRL is set the receiver is connected to the LEUn_TX pin as shown in Figure 18 5 p 257 ...

Page 258: ...st be controlled by a GPIO Figure 18 6 p 258 shows an example configuration using an external driver Figure 18 6 LEUART Half Duplex Communication with External Driver LEUART RX TX µC GPIO 18 3 7 3 Two Data links Some limited devices only support half duplex communication even though two data links are available In this case software is responsible for making sure data is not transmitted when incom...

Page 259: ... DMA controller still transfers bits to and from the LEUART in low energy modes these bits must thus be configured accordingly Note When RXDMAWU or TXDMAWU is set the system will not be able to go to EM2 EM3 before all related LEUART DMA requests have been processed This means that if RXDMAWU is set and the LEUART receives a frame the system will not be able to go to EM2 EM3 before the frame has b...

Page 260: ...cification The external IrDA device must generate pulses of sufficient length for successful two way communication 18 3 10 1 Interrupts The interrupts generated by the LEUART are combined into one interrupt vector If LEUART interrupts are enabled an interrupt will be made if one or more of the interrupt flags in LEUARTn_IF and their corresponding bits in LEUART_IEN are set 18 3 11 Register access ...

Page 261: ...ARTn_PULSECTRL RW Pulse Control Register 0x040 LEUARTn_FREEZE RW Freeze Register 0x044 LEUARTn_SYNCBUSY R Synchronization Busy Register 0x054 LEUARTn_ROUTE RW I O Routing Register 18 5 Register Description 18 5 1 LEUARTn_CTRL Control Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 262: ...Value Description 0 The 9th bit of incoming frames have no special function 1 An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set 8 SFUBRX 0 RW Start Frame UnBlock RX Clears RXBLOCK when the start frame is found in the incoming data The start frame is loaded into the receive buffer Value ...

Page 263: ... Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access W1 W1 W1 W1 W1 W1 W1 W1 Name CLEARRX CLEARTX RXBLOCKDIS RXBLOCKEN TXDIS TXEN RXDIS RXEN Bit Name Reset Access Description 31 8 Reserved To ensure compatibility w...

Page 264: ...ared when a new transmission starts 2 RXBLOCK 0 R Block Incoming Data When set the receiver discards incoming frames An incoming frame will not be loaded into the receive buffer if this bit is set at the instant the frame has been completely received 1 TXENS 0 R Transmitter Enable Status Set when the transmitter is enabled 0 RXENS 0 R Receiver Enable Status Set when the receiver is enabled The rec...

Page 265: ...et and if SFUBRX is set RXBLOCK is cleared The start frame is be loaded into the RX buffer 18 5 6 LEUARTn_SIGFRAME Signal Frame Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x000 Access RW Name SIGFRAME Bit Name Reset Access Descr...

Page 266: ... 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access R Name RXDATA Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 RXDATA 0x00 R RX Data Use this register to access data read from LEUART Buffer is cleared on read access Only the 8 LSB can be read using this register 1...

Page 267: ...0 1 The receiver is enabled setting RXENS after the frame has been transmitted 14 TXDISAT 0 W Disable TX After Transmission Set to disable transmitter directly after transmission has competed Value Description 0 1 The transmitter is disabled clearing TXENS after the frame has been transmitted 13 TXBREAK 0 W Transmit Data As Break Set to send data as a break Recipient will see a framing error or a ...

Page 268: ...information in Section 2 1 p 3 10 SIGF 0 R Signal Frame Interrupt Flag Set when a signal frame is detected 9 STARTF 0 R Start Frame Interrupt Flag Set when a start frame is detected 8 MPAF 0 R Multi Processor Address Frame Interrupt Flag Set when a multi processor address frame is detected 7 FERR 0 R Framing Error Interrupt Flag Set when a frame with a framing error is received while RXBLOCK is cl...

Page 269: ... the STARTF interrupt flag 8 MPAF 0 W1 Set Multi Processor Address Frame Interrupt Flag Write to 1 to set the MPAF interrupt flag 7 FERR 0 W1 Set Framing Error Interrupt Flag Write to 1 to set the FERR interrupt flag 6 PERR 0 W1 Set Parity Error Interrupt Flag Write to 1 to set the PERR interrupt flag 5 TXOF 0 W1 Set TX Overflow Interrupt Flag Write to 1 to set the TXOF interrupt flag 4 RXUF 0 W1 ...

Page 270: ... 1 to clear the RXOF interrupt flag 2 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 TXC 0 W1 Clear TX Complete Interrupt Flag Write to 1 to clear the TXC interrupt flag 18 5 15 LEUARTn_IEN Interrupt Enable Register Offset Bit Position 0x038 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res...

Page 271: ... 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0x0 Access RW RW RW Name PULSEFILT PULSEEN PULSEW Bit Name Reset Access Description 31 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 5 PULSEFILT 0 RW Pulse Filter Enable a one cycle pulse filter for pulse extender Value Description 0 Filter is disabled Pulses must be at least 2 cycles long for ...

Page 272: ... 0 0 0 Access R R R R R R R R Name PULSECTRL TXDATA TXDATAX SIGFRAME STARTFRAME CLKDIV CMD CTRL Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 PULSECTRL 0 R PULSECTRL Register Busy Set when the value written to PULSECTRL is being synchronized 6 TXDATA 0 R TXDATA Register Busy Set when the valu...

Page 273: ... write bits to 0 More information in Section 2 1 p 3 9 8 LOCATION 0x0 RW I O Location Decides the location of the LEUART I O pins Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 7 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 TXPEN 0 RW TX Pin Enable When set the TX pin of the LEUART is enabled Value...

Page 274: ... The Timer can also count events and control other peripherals through the PRS which offloads the CPU and reduce energy consumption 19 1 Introduction The 16 bit general purpose Timer has 3 compare capture channels for input capture and compare Pulse Width Modulation PWM output TIMER0 also includes a Dead Time Insertion module suitable for motor control applications 19 2 Features 16 bit auto reload...

Page 275: ...e Configurable to either run or stop when processor is stopped break Interrupts PRS output and or DMA request Underflow Overflow Compare Capture event Dead Time Insertion Unit TIMER0 only Complementary PWM outputs with programmable dead time Dead time is specified independently for rising and falling edge 10 bit prescaler 6 bit time value Outputs have configurable polarity Outputs can be set inact...

Page 276: ... Two input channels where one determines the count direction while the other pin triggers a clock event The counter value can be read or written by software at any time by accessing the CNT field in TIMERn_CNT 19 3 1 1 Events Overflow is set when the counter value shifts from TIMERn_TOP to the next value when counting up In up count mode the next value is 0 In up down count mode the next value is ...

Page 277: ...L Filter FILT ICEDGE Input Capture 0 Counter RISEA FALLA Start Stop Reload Start 19 3 1 3 Clock Source The counter can be clocked from several sources which are all synchronized with the peripheral clock HFPERCLK See Figure 19 3 p 277 Figure 19 3 TIMER Clock Selection Counter Controlled by TIMERn_CTRL Compare Capture channel 1 Controlled by TIMERn_CC1_CTRL TIMn_CC1 PRS channels PRSSEL INSEL Filter...

Page 278: ...the OSMEN bit is set in the TIMERn_CTRL register however the counter is disabled by hardware on the first update event Note that when the counter is running with CC1 as clock source 0b01 in CLKSEL in TIMERn_CTRL and OSMEN is set a CC1 capture event will not take place on the update event CC1 rising edge that stops the Timer 19 3 1 5 Top Value Buffer The TIMERn_TOP register can be altered either by...

Page 279: ... a counter reset from the interrupt service routine By connecting a periodic signal from another timer as input capture on Compare Capture Channel 2 it is also possible to calculate speed and acceleration Figure 19 7 TIMER Quadrature Decoder Configuration Counter Controlled by TIMERn_CTRL Compare Capture channel 1 Controlled by TIMERn_CC1_CTRL Compare Capture channel 0 Controlled by TIMERn_CC0_CTR...

Page 280: ...280 Table 19 2 TIMER Counter Response in X4 Decoding Mode Channel A Channel B Opposite Channel Rising Falling Rising Falling Channel A 0 Decrement Increment Channel A 1 Increment Decrement Channel B 0 Increment Decrement Channel B 1 Decrement Increment Figure 19 9 TIMER X4 Decoding Mode Channel A Channel B 3 4 5 6 7 8 9 10 11 3 4 5 6 7 8 9 10 11 2 2 CNT 19 3 1 6 3 TIMER Rotational Position To calc...

Page 281: ...are PWM the behavior of the Compare Capture registers TIMERn_CCx_CCV and buffer registers TIMERn_CCx_CCVB change depending on the mode the channel is set in 19 3 2 2 1 Input Capture mode When running in Input Capture mode TIMERn_CCx_CCV and TIMERn_CCx_CCVB form a FIFO buffer and new capture values are added on a capture event see Figure 19 11 p 282 The first capture can always be read from TIMERn_...

Page 282: ...TUS indicates whether the TIMERn_CCx_CCVB register contains data that have not yet been written to the TIMERn_CCx_CCV register Note that when writing 0 to TIMERn_CCx_CCVB the CCV value is updated when the timer counts from 0 to 1 Thus the compare match for the next period will not happen until the timer reaches 0 again on the way down Figure 19 12 TIMER Output Compare PWM Buffer Functionality CCV ...

Page 283: ...ture Channel should be set to capture on a falling edge of the input signal To start the measuring period on either a falling edge or measure the low pulse width of a signal opposite polarities should be chosen Figure 19 14 TIMER Period and or Pulse width Capture 0 Input CNT Clear Start Input Capture frequency capture Input Capture pulse width capture 19 3 2 4 Compare Each Compare Capture channel ...

Page 284: ...cted through PRSSEL INSEL and FILTSEL in TIMERn_CCx_CTRL for the CC channel will also be sampled on compare match and the result is found in the CCPOL bits in TIMERn_STATUS The COIST bit in TIMERn_CCx_CTRL is the initial state of the compare PWM output Also the resulting output can be inverted by setting OUTINV in TIMERn_CCx_CTRL It is recommended to turn off the CC channel before configuring the ...

Page 285: ...the counter is set to up count and the Compare Capture channel is put in PWM mode single slope PWM output will be generated see Figure 19 18 p 285 In up count mode the PWM period is TOP 1 cycles and the PWM output will be high for a number of cycles equal to TIMERn_CCx_CCV This means that a constant high output is achieved by setting TIMER_CCx to TOP 1 or higher The PWM resolution in bits is then ...

Page 286: ...ution Equation RPWMup down log TOP 1 log 2 19 6 The PWM frequency is given by Equation 19 7 p 286 TIMER Up Down count PWM Frequency Equation fPWMup down fHFPERCLK 2 PRESC 1 x TOP 19 7 The high duty cycle is given by Equation 19 8 p 286 TIMER Up Down count Duty Cycle Equation DSup down CCVx TOP 19 8 19 3 3 Dead Time Insertion Unit TIMER0 only The Dead Time Insertion Unit aims to make control of BLD...

Page 287: ...UL W V U For each of the 3 compare match outputs of TIMER0 an additional complementary output is provided by the DTI unit These outputs named TIM0_CDTI0 TIM0_CDTI1 and TIM0_CDTI2 are provided to make control of e g 3 channel BLDC or PMAC motors possible using only a single timer see Figure 19 22 p 287 Figure 19 22 TIMER Overview of Dead Time Insertion Block for a Single PWM channel Clock control C...

Page 288: ... the same time by the DTI unit The polarity of the outputs can be changed however if this is required by the application The active values of the primary and complementary outputs are set by two the TIMER0_DTCTRL register The DTIPOL bit of this register specifies the base polarity If DTIPOL 0 then the outputs are active high and if DTIPOL 1 they are active low The relative phase of the primary and...

Page 289: ...e PWM output from the timer The PRS channel to use is chosen by configuring DTPRSSEL in TIMER0_DTCTRL Note that the timer must be running even when PRS is used as DTI source The DTI prescaler set by DTPRESC in TIMER0_DTTIME determines with which accuracy the DTI can insert dead time into a PRS signal The maximum dead time error equals 2 DTPRESC clock cycles With zero prescaling the inserted dead t...

Page 290: ...rmined by TIMER0_DTFS is the debugger alone the outputs can optionally be re enabled when the debugger exits and the processor resumes normal operation The corresponding bit in TIMER0_DTFS will in that case be cleared by hardware The automatic start up functionality can be enabled by setting DTDAS in TIMER0_DTCTRL If more bits are still set in DTFS when the automatic start up functionality has cle...

Page 291: ...in TIMERn_CTRL the DMA request is cleared when the triggered DMA channel is active without having to access any timer registers Table 19 3 TIMER Events Event Acknowledge Underflow Overflow Read or write to TIMERn_CNT or TIMERn_TOPB CC 0 Read or write to TIMERn_CC0_CCV or TIMERn_CC0_CCVB CC 1 Read or write to TIMERn_CC1_CCV or TIMERn_CC1_CCVB CC 2 Read or write to TIMERn_CC2_CCV or TIMERn_CC2_CCVB ...

Page 292: ...ontrol Register 0x034 TIMERn_CC0_CCV RWH CC Channel Value Register 0x038 TIMERn_CC0_CCVP R CC Channel Value Peek Register 0x03C TIMERn_CC0_CCVB RWH CC Channel Buffer Register 0x040 TIMERn_CC1_CTRL RW CC Channel Control Register 0x044 TIMERn_CC1_CCV RWH CC Channel Value Register 0x048 TIMERn_CC1_CCVP R CC Channel Value Peek Register 0x04C TIMERn_CC1_CCVB RWH CC Channel Buffer Register 0x050 TIMERn_...

Page 293: ...e HFPERCLK is divided by 256 9 DIV512 The HFPERCLK is divided by 512 10 DIV1024 The HFPERCLK is divided by 1024 23 18 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 17 16 CLKSEL 0x0 RW Clock Source Select These bits select the clock source for the timer Value Mode Description 0 PRESCHFPERCLK Prescaled HFPERCLK 1 CC1 Compare Capture C...

Page 294: ...is set the Timer is started stopped reloaded by start stop reload commands in the other timers Value Description 0 Timer is not started stopped reloaded by other timers 1 Timer is started stopped reloaded by other timers 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 0 MODE 0x0 RW Timer Mode These bit set the counting mode for th...

Page 295: ...annel 1 These bits are cleared when CCMODE is written to 0b00 Off Value Mode Description 0 LOWRISE CC1 polarity low level rising edge 1 HIGHFALL CC1 polarity high level falling edge 24 CCPOL0 0 R CC0 Polarity In Input Capture mode this bit indicates the polarity of the edge that triggered capture in TIMERn_CC0_CCV In Compare PWM mode this bit indicates the polarity of the selected input to CC chan...

Page 296: ... Value Description 0 TIMERn_CC1_CCVB does not contain valid data 1 TIMERn_CC1_CCVB contains valid data which will be written to TIMERn_CC1_CCV on the next update event 8 CCVBV0 0 R CC0 CCVB Valid This field indicates that the TIMERn_CC0_CCVB registers contain data which have not been written to TIMERn_CC0_CCV These bits are only used in output compare pwm mode and are cleared when CCMODE is writte...

Page 297: ...UF 0 RW Underflow Interrupt Enable Enable disable underflow interrupt 0 OF 0 RW Overflow Interrupt Enable Enable disable overflow interrupt 19 5 5 TIMERn_IF Interrupt Flag Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Name ICBOF2 ICBOF1 ICBOF0 CC2 CC1 CC0 UF OF Bit Name Reset Acc...

Page 298: ...pture Buffer Overflow Interrupt Flag Set Writing a 1 to this bit will set Compare Capture channel 2 input capture buffer overflow interrupt flag 9 ICBOF1 0 W1 CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Set Writing a 1 to this bit will set Compare Capture channel 1 input capture buffer overflow interrupt flag 8 ICBOF0 0 W1 CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Set...

Page 299: ...re channel 0 input capture buffer overflow interrupt flag 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 6 CC2 0 W1 CC Channel 2 Interrupt Flag Clear Writing a 1 to this bit will clear Compare Capture interrupt flag 2 5 CC1 0 W1 CC Channel 1 Interrupt Flag Clear Writing a 1 to this bit will clear Compare Capture interrupt flag 1 4 ...

Page 300: ...PB 0x0000 RW Counter Top Value Buffer These bits hold the TOP buffer value 19 5 10 TIMERn_CNT Counter Value Register Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RWH Name CNT Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Se...

Page 301: ...l 2 output input connection to pin 1 CC1PEN 0 RW CC Channel 1 Pin Enable Enable disable CC channel 1 output input connection to pin 0 CC0PEN 0 RW CC Channel 0 Pin Enable Enable disable CC Channel 0 output input connection to pin 19 5 12 TIMERn_CCx_CTRL CC Channel Control Register Offset Bit Position 0x030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0...

Page 302: ... PRS Channel 0 selected as input 1 PRSCH1 PRS Channel 1 selected as input 2 PRSCH2 PRS Channel 2 selected as input 3 PRSCH3 PRS Channel 3 selected as input 4 PRSCH4 PRS Channel 4 selected as input 5 PRSCH5 PRS Channel 5 selected as input 6 PRSCH6 PRS Channel 6 selected as input 7 PRSCH7 PRS Channel 7 selected as input 15 14 Reserved To ensure compatibility with future devices always write bits to ...

Page 303: ...ure devices always write bits to 0 More information in Section 2 1 p 3 2 OUTINV 0 RW Output Invert Setting this bit inverts the output from the CC channel Output compare PWM 1 0 MODE 0x0 RW CC Channel Mode These bits select the mode for Compare Capture channel Value Mode Description 0 OFF Compare Capture channel turned off 1 INPUTCAPTURE Input capture 2 OUTPUTCOMPARE Output compare 3 PWM Pulse Wid...

Page 304: ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RWH Name CCVB Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 CCVB 0x0000 RWH CC Channel Value Buffer In Input Capture mode this field holds the last capture value if the TIMERn_CCx_CC...

Page 305: ...ed as input 3 DTCINV 0 RW DTI Complementary Output Invert Set to invert complementary outputs 2 DTIPOL 0 RW DTI Inactive Polarity Set inactive polarity for outputs 1 DTDAS 0 RW DTI Automatic Start up Functionality Configure DTI restart on debugger exit Value Mode Description 0 NORESTART No DTI restart on debugger exit 1 RESTART DTI restart on debugger exit 0 DTEN 0 RW DTI Enable Enable disable DTI...

Page 306: ... Bit Position 0x078 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0x0 0x0 0x0 Access RW RW RW RW RW RW RW Name DTLOCKUPFEN DTDBGFEN DTPRS1FEN DTPRS0FEN DTFA DTPRS1FSEL DTPRS0FSEL Bit Name Reset Access Description 31 28 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 27 DTLOCKUPFEN ...

Page 307: ... PRSCH1 PRS Channel 1 selected as fault source 0 2 PRSCH2 PRS Channel 2 selected as fault source 0 3 PRSCH3 PRS Channel 3 selected as fault source 0 4 PRSCH4 PRS Channel 4 selected as fault source 0 5 PRSCH5 PRS Channel 5 selected as fault source 0 6 PRSCH6 PRS Channel 6 selected as fault source 0 7 PRSCH7 PRS Channel 7 selected as fault source 0 19 5 19 TIMERn_DTOGEN DTI Output Generation Enable ...

Page 308: ...register can be used to clear fault bits 2 DTDBGF 0 R DTI Debugger Fault This bit is set to 1 if a debugger fault has occurred and DTDBGFEN is set to 1 The TIMER0_DTFAULTC register can be used to clear fault bits 1 DTPRS1F 0 R DTI PRS 1 Fault This bit is set to 1 if a PRS 1 fault has occurred and DTPRS1FEN is set to 1 The TIMER0_DTFAULTC register can be used to clear fault bits 0 DTPRS0F 0 R DTI P...

Page 309: ... 2 1 0 Reset 0x0000 Access RW Name LOCKKEY Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 LOCKKEY 0x0000 RW DTI Lock Key Write any other value than the unlock code to lock TIMER0_ROUTE TIMER0_DTCTRL TIMER0_DTTIME and TIMER0_DTFC from editing Write the unlock code to unlock When reading the...

Page 310: ...and EM1 the RTC is also available in EM2 This makes it ideal for keeping track of time since the RTC is enabled in EM2 where most of the device is powered down Two compare channels are available in the RTC These can be used to trigger interrupts and to wake the device up from a low energy mode They can also be used with the LETIMER to generate various output waveforms 20 2 Features 24 bit Real Tim...

Page 311: ...dable and writable and the RTC always starts counting from 0 when enabled The value of the counter can be read or modified using the RTC_CNT register 20 3 1 1 Clock Source The RTC clock source and its prescaler value are defined in the Register Description section of the Clock Management Unit CMU The clock used by the RTC has a frequency given by Equation 20 1 p 311 RTC Frequency Equation fRTC fLF...

Page 312: ...for the RTC and the timer is cleared on a compare match with compare channel 0 If using the COMP0TOP setting make sure to set this bit prior to or at the same time the EN bit is set Setting COMP0TOP after the EN bit is set may cause unintended operation i e if CNT COMP0 20 3 2 1 LETIMER Triggers A compare event on either of the compare channels can start the LETIMER See the LETIMER documentation f...

Page 313: ...g the DEBUGRUN bit in the RTC_CTRL register the RTC will continue to run even when the debugger is halted 20 3 5 Register access Since this module is a Low Energy Peripheral and runs off a clock which is asynchronous to the HFCORECLK special considerations must be taken when accessing registers Please refer to Section 5 3 1 1 p 21 for a description on how to perform register accesses to Low Energy...

Page 314: ...bout Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 Access RW RW RW Name COMP0TOP DEBUGRUN EN Bit Name Reset Access Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 COMP0TOP 0 RW Compare Cha...

Page 315: ...Value Register 0 Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x000000 Access RW Name COMP0 Bit Name Reset Access Description 31 24 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1...

Page 316: ...e as a PRS signal 20 5 5 RTC_IF Interrupt Flag Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 Access R R R Name COMP1 COMP0 OF Bit Name Reset Access Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 COMP1 0 R Compare Match 1 Interrup...

Page 317: ...scription 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 COMP1 0 W1 Clear Compare match 1 Interrupt Flag Write to 1 to clear the COMP1 interrupt flag 1 COMP0 0 W1 Clear Compare match 0 Interrupt Flag Write to 1 to clear the COMP0 interrupt flag 0 OF 0 W1 Clear Overflow Interrupt Flag Write to 1 to clear the OF interrupt flag 2...

Page 318: ...taneously Value Mode Description 0 UPDATE Each write access to an RTC register is updated into the Low Frequency domain as soon as possible 1 FREEZE The RTC is not updated with the new written value until the freeze bit is cleared 20 5 10 RTC_SYNCBUSY Synchronization Busy Register Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset ...

Page 319: ...ergy Timer is a 16 bit timer that is available in energy mode EM2 in addition to EM1 and EM0 Because of this it can be used for timing and output generation when most of the device is powered down allowing simple tasks to be performed while the power consumption of the system is kept at an absolute minimum The LETIMER can be used to output a variety of waveforms with minimal software intervention ...

Page 320: ... pin ctrl LETn_O0 Pulse Control Underflow UF interrupt flag REP0 Zero REP0 interrupt flag Buffer Written Repeat load logic pin ctrl LETn_O1 Pulse Control Top load logic 1 REP1 Zero REP1 interrupt flag COMP1 Match COMP1 interrupt flag COMP0 Match COMP0 interrupt flag 21 3 1 Timer The timer is started by setting command bit START in LETIMERn_CMD and stopped by setting the STOP command bit in the sam...

Page 321: ...around to the top value or 0xFFFF on each underflow and continues counting The repeat counters can be used to get more control of the operation of the timer including defining the number of times the counter should wrap around Four different repeat modes are available see Table 21 1 p 321 Table 21 1 LETIMER Repeat Modes REPMODE Mode Description 00 Free The timer runs until it is stopped 01 One sho...

Page 322: ... generated no output action is performed LETIMERn_REP0 LETIMERn_REP1 LETIMERn_COMP0 and LETIMERn_COMP1 are also left untouched 21 3 3 2 2 One shot Mode The one shot repeat mode is the most basic repeat mode In this mode the repeat register LETIMERn_REP0 is decremented every time the timer underflows and the timer stops when LETIMERn_REP0 goes from 1 to 0 In this mode the timer counts down LETIMERn...

Page 323: ... long as LETIMERn_REP1 is updated with a nonzero value before LETIMERn_REP0 is finished counting down If the timer is started when both LETIMERn_CNT and LETIMERn_REP0 are zero but LETIMERn_REP1 is non zero LETIMERn_REP1 is loaded into LETIMERn_REP0 and the counter counts the loaded number of times The state machine for the one shot repeat mode is shown in Figure 21 3 p 323 Used in conjunction with...

Page 324: ...h like the one shot repeat mode The difference is that where the one shot mode counts as long as LETIMERn_REP0 is larger than 0 the double mode counts as long as either LETIMERn_REP0 or LETIMERn_REP1 is larger than 0 As an example say LETIMERn_REP0 is 3 and LETIMERn_REP1 is 10 when the timer is started If no further interaction is done with the timer LETIMERn_REP0 will now be decremented 3 times a...

Page 325: ...FACKL_LETIMERn 32 768 2 LETIMERn 21 1 where the exponent LETIMERn is a 4 bit value in the CMU_LFAPRESC0 register To use this module the LE interface clock must be enabled in CMU_HFCORECLKEN0 in addition to the module clock 21 3 3 4 RTC Trigger The LETIMER can be configured to start on compare match events from the Real Time Counter RTC If RTCC0TEN in LETIMERn_CTRL is set the LETIMER will start on ...

Page 326: ...A0 and UFOA1 in LETIMERn_CTRL UFOA0 defines the action on output 0 and is connected to LETIMERn_REP0 while UFOA1 defines the action on output 1 and is connected to LETIMERn_REP1 The possible actions are defined in Table 21 2 p 326 Table 21 2 LETIMER Underflow Output Actions UF0A0 UF0A1 Mode Description 00 Idle The output is held at its idle value 01 Toggle The output is toggled on LETIMERn_CNT und...

Page 327: ...ETn_O0 UFOA0 01 LETn_O0 UFOA0 10 LETn_O0 UFOA0 00 3 0 UFIF 3 0 For the example in Figure 21 7 p 327 the One shot repeat mode has been selected and LETIMERn_REP0 has been written to 3 The resulting behavior is pretty similar to that shown in Figure 6 but in this case the timer stops after counting to zero LETIMERn_REP0 times By using LETIMERn_REP0 the user has full control of the number of pulses t...

Page 328: ...RTC and LETIMER can thus be combined to generate specific pulse trains at given intervals Software can update LETIMERn_COMP1 and LETIMERn_REP1 to change the number of pulses and pulse period in each train but if changes are not required software does not have to update the registers between each pulse train For the example in Figure 21 9 p 328 the initial values cause the LETIMER to generate two p...

Page 329: ...F UFIF UFIF UFIF UFIF Int flags set Stop final values Write COMP1 2 REP1 2 UFIF UFIF UFIF REP0IF 4 4 4 4 4u 4u 4u 2 2 2u 2u 2u 2u 2 2 1 1 2 2 0 1 2u 2u REP0IF LFACLKLETIMERn LETn_O0 UFOA0 01 LETn_O1 UFOA0 10 Pulse Seq 1 Pulse Seq 2 Pulse Seq 3 4 4 4 4 4 4 2 2 2 2 2 0 0 2u The first two sequences are loaded into the LETIMER before the timer is started LETIMERn_COMP0 is set to 2 cycles 1 and LETIMER...

Page 330: ...l ways of generating PWM output with the LETIMER but the most straight forward way is using the PWM output mode This mode is enabled by setting UFOA0 or OFUA1 in LETIMERn_CTRL to 3 In PWM mode the output is set idle on timer underflow and active on LETIMERn_COMP1 match so if for instance COMP0TOP 1 and OPOL0 0 in LETIMERn_CTRL LETIMERn_COMP0 determines the PWM period and LETIMERn_LETIMERn_COMP1 de...

Page 331: ...m 21 3 6 Register access Since this module is a Low Energy Peripheral and runs off a clock which is asynchronous to the HFCORECLK special considerations must be taken when accessing registers Please refer to Section 5 3 1 1 p 21 for a description on how to perform register accesses to Low Energy Peripherals ...

Page 332: ...4 LETIMERn_SYNCBUSY R Synchronization Busy Register 0x040 LETIMERn_ROUTE RW I O Routing Register 21 5 Register Description 21 5 1 LETIMERn_CTRL Control Register Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0x0 0x0 0x0 Access ...

Page 333: ... Defines the action on LETn_O1 on a LETIMER underflow Value Mode Description 0 NONE LETn_O1 is held at its idle value as defined by OPOL1 1 TOGGLE LETn_O1 is toggled on CNT underflow 2 PULSE LETn_O1 is held active for one LFACLKLETIMER0 clock cycle on CNT underflow The output then returns to its idle value as defined by OPOL1 3 PWM LETn_O1 is set idle on CNT underflow and active on compare match w...

Page 334: ... 0 W1 Clear Toggle Output 1 Set to drive toggle output 1 to its idle value 3 CTO0 0 W1 Clear Toggle Output 0 Set to drive toggle output 0 to its idle value 2 CLEAR 0 W1 Clear LETIMER Set to clear LETIMER 1 STOP 0 W1 Stop LETIMER Set to stop LETIMER 0 START 0 W1 Start LETIMER Set to start LETIMER 21 5 3 LETIMERn_STATUS Status Register Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19...

Page 335: ...read the current value of the LETIMER 21 5 5 LETIMERn_COMP0 Compare Value Register 0 Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name COMP0 Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with fut...

Page 336: ...lease see Section 5 3 p 20 Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RW Name REP0 Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 REP0 0x00 RW Repeat Counter 0 Optional repeat counter 21 5 8 LETIMERn_REP1 ...

Page 337: ... zero or when the REP1 interrupt flag is loaded into the REP0 interrupt flag 2 UF 0 R Underflow Interrupt Flag Set on LETIMER underflow 1 COMP1 0 R Compare Match 1 Interrupt Flag Set when LETIMER reaches the value of COMP1 0 COMP0 0 R Compare Match 0 Interrupt Flag Set when LETIMER reaches the value of COMP0 21 5 10 LETIMERn_IFS Interrupt Flag Set Register Offset Bit Position 0x024 31 30 29 28 27 ...

Page 338: ...o clear the REP1 interrupt flag 3 REP0 0 W1 Clear Repeat Counter 0 Interrupt Flag Write to 1 to clear the REP0 interrupt flag 2 UF 0 W1 Clear Underflow Interrupt Flag Write to 1 to clear the UF interrupt flag 1 COMP1 0 W1 Clear Compare Match 1 Interrupt Flag Write to 1 to clear the COMP1 interrupt flag 0 COMP0 0 W1 Clear Compare Match 0 Interrupt Flag Write to 1 to clear the COMP0 interrupt flag 2...

Page 339: ...et the update of the LETIMER is postponed until this bit is cleared Use this bit to update several registers simultaneously Value Mode Description 0 UPDATE Each write access to a LETIMER register is updated into the Low Frequency domain as soon as possible 1 FREEZE The LETIMER is not updated with the new written value 21 5 14 LETIMERn_SYNCBUSY Synchronization Busy Register Offset Bit Position 0x03...

Page 340: ...N OUT1PEN OUT0PEN Bit Name Reset Access Description 31 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 9 8 LOCATION 0x0 RW I O Location Decides the location of the LETIMER I O pins Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 3 LOC3 Location 3 7 2 Reserved To ensure compatibility with future devices ...

Page 341: ... keep track of incoming pulses or rotations 22 1 Introduction The Pulse Counter PCNT can be used for counting incoming pulses on a single input or to decode quadrature encoded inputs It can run from the internal LFACLK EM0 EM2 while counting pulses on the PCNTn_S0IN pin or using this pin as an external clock source EM0 EM3 that runs both the PCNT counter and register access 22 2 Features 8 bit cou...

Page 342: ...PCNTn_CTRL register Additionally the PCNTn_S0IN input may be inverted so that falling edges are counted by setting the EDGE bit in the PCNTn_CTRL register PCNTn_S0IN is the only observed input in this mode This input is sampled by the LFACLK and the number of detected positive or negative edges on PCNTn_S0IN appears in PCNTn_CNT The counter may be configured to count down by setting the CNTDIR bit...

Page 343: ... the direction of the counter register PCNTn_CNT is controlled automatically Figure 22 2 PCNT Quadrature Coding X X 1 cycle sector 4 states 01 11 10 00 X X 1 cycle sector 4 states 00 10 11 01 X sensor position Clockwise direction Counter clockwise direction PCNTn_S0IN PCNTn_S1IN PCNTn_S0IN PCNTn_S1IN PCNTn_CNT Reset 0 0 1 2 PCNTn_CNT 0 0 PCNTn_TOP PCNTn_TOP 1 If PCNTn_S0IN leads PCNTn_S1IN in phas...

Page 344: ...t restores the reset values in PCNTn_TOP PCNTn_CNT and other control registers in the PCNT clock domain Since this module is a Low Energy Peripheral and runs off a clock which is asynchronous to the HFCORECLK special considerations must be taken when accessing registers Please refer to Section 5 3 p 20 for a description on how to perform register accesses to Low Energy Peripherals Note PCNTn_TOP a...

Page 345: ... The EDGE bit in PCNTn_CTRL has no effect in EXTCLKSINGLE mode 22 3 6 PRS Sources The PCNT module does not generate or receive any PRS events 22 3 7 Interrupts The interrupt generated by PCNT uses the PCNTn_INT interrupt vector Software must read the PCNTn_IF register to determine which module interrupt that generated the vector invocation 22 3 7 1 Underflow and Overflow Interrupts The underflow i...

Page 346: ...NT Direction Change Interrupt DIRCNG Generation Standard async handshake interface PCNTn_S0IN PCNTn_S1IN Interrupt X X Invalid pulse generated when the shaft changes direction n 1 n 2 n 3 n 2 PCNTn_CNT n Delay from the shaft physically changed direction until the counter direction is changed and the interrupt is generated ...

Page 347: ...6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0x0 Access RW RW RW RW RW Name RSTEN FILT EDGE CNTDIR MODE Bit Name Reset Access Description 31 6 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 5 RSTEN 0 RW Enable PCNT Clock Domain Reset The PCNT clock domain is asynchronously held in reset when this bit is set The reset is sync...

Page 348: ... Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access W1 W1 Name LTOPBIM LCNTIM Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 LTOPBIM 0...

Page 349: ...d To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 CNT 0x0000 R Counter Value Gives read access to the counter 22 5 5 PCNTn_TOP Top Value Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00FF Access R Name TOP Bit Name Reset Access Description 31 16 Reserved To...

Page 350: ... extract the chip revision 22 5 7 PCNTn_IF Interrupt Flag Register Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 Access R R R Name DIRCNG OF UF Bit Name Reset Access Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 DIRCNG 0 R Direction Chan...

Page 351: ... UF Bit Name Reset Access Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 DIRCNG 0 W1 Direction Change Detect Interrupt Clear Write to 1 to clear the direction change detect interrupt flag 1 OF 0 W1 Overflow Interrupt Clear Write to 1 to clear the overflow interrupt flag 0 UF 0 W1 Underflow Interrupt Clear Write to ...

Page 352: ...cription 0 LOC0 Location 0 1 LOC1 Location 1 2 LOC2 Location 2 7 0 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 22 5 12 PCNTn_FREEZE Freeze Register Offset Bit Position 0x02C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access RW Name REGFREEZE Bit Name Reset Access Description 31 1 ...

Page 353: ... 4 3 2 1 0 Reset 0 0 0 Access R R R Name TOPB CMD CTRL Bit Name Reset Access Description 31 3 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 2 TOPB 0 R TOPB Register Busy Set when the value written to TOPB is being synchronized 1 CMD 0 R CMD Register Busy Set when the value written to CMD is being synchronized 0 CTRL 0 R CTRL Registe...

Page 354: ...n The Analog Comparator is used to compare the voltage of two analog inputs with a digital output indicating which input voltage is higher Inputs can either be one of the selectable internal references or from external pins Response time and thereby also the current consumption can be configured by altering the current supply to the comparator 23 2 Features 8 selectable external positive inputs 8 ...

Page 355: ...itch inputs while the comparator is enabled but all other configuration should only be changed while the comparator is disabled 23 3 1 Warm up Time The analog comparator is enabled by setting the EN bit in ACMPn_CTRL When this bit is set the comparator must stabilize before becoming active and the outputs can be used This time period is called the warm up time The warm up time is a configurable nu...

Page 356: ... FULLBIAS 1 HALFBIAS 0 0b0000 0 05 0 1 3 3 6 5 0b0001 0 1 0 2 6 5 13 0b0010 0 2 0 4 13 26 0b0011 0 3 0 6 20 39 0b0100 0 4 0 8 26 52 0b0101 0 5 1 0 33 65 0b0110 0 6 1 2 39 78 0b0111 0 7 1 4 46 91 0b1000 1 0 2 0 65 130 0b1001 1 1 2 2 72 143 0b1010 1 2 2 4 78 156 0b1011 1 3 2 6 85 169 0b1100 1 4 2 8 91 182 0b1101 1 5 3 0 98 195 0b1110 1 6 3 2 104 208 0b1111 1 7 3 4 111 221 23 3 3 Hysteresis In the an...

Page 357: ...s when the EN bit is toggled 23 3 5 Capacitive Sense Mode The analog comparator includes specialized hardware for capacitive sensing of passive push buttons Such buttons are traces on PCB laid out in a way that creates a parasitic capacitor between the button and the ground node Because a human finger will have a small intrinsic capacitance to ground the capacitance of the button will increase whe...

Page 358: ...ough the EDGE bit in ACMPn_IEN The edge interrupt can also be used to wake up the device from EM3 EM1 The analog comparator also includes an interrupt flag WARMUP in ACMPn_IF which is set when a warm up sequence has finished An interrupt request will be sent if the WARMUP interrupt flag in ACMPn_IF is set and enabled through the WARMUP bit in ACMPn_IEN The comparator output is also available as a ...

Page 359: ...nt Set this bit to 1 for full bias current in accordance with Table 23 1 p 356 30 HALFBIAS 1 RW Half Bias Current Set this bit to 1 to halve the bias current in accordance with Table 23 1 p 356 29 28 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 27 24 BIASPROG 0x7 RW Bias Configuration These bits control the bias current level in ac...

Page 360: ...is 2 HYST2 22 mV hysteresis 3 HYST3 29 mV hysteresis 4 HYST4 36 mV hysteresis 5 HYST5 43 mV hysteresis 6 HYST6 50 mV hysteresis 7 HYST7 57 mV hysteresis 3 GPIOINV 0 RW Comparator GPIO Output Invert Set this bit to 1 to invert the comparator alternate function output to GPIO Value Mode Description 0 NOTINV The comparator output to GPIO is not inverted 1 INV The comparator output to GPIO is inverted...

Page 361: ...w power mode for VDD and bandgap references Value Description 0 Low power mode disabled 1 Low power mode enabled 15 14 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 13 8 VDDLEVEL 0x00 RW VDD Reference Level Select scaling factor for VDD reference level VDD_SCALED VDD VDDLEVEL 63 7 4 NEGSEL 0x8 RW Negative Input Select Select negativ...

Page 362: ...rator Active Analog comparator active status 23 5 4 ACMPn_IEN Interrupt Enable Register Offset Bit Position 0x00C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access RW RW Name WARMUP EDGE Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 WARMUP ...

Page 363: ...DGE Bit Name Reset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 WARMUP 0 W1 Warm up Interrupt Flag Set Write to 1 to set warm up finished interrupt flag 0 EDGE 0 W1 Edge Triggered Interrupt Flag Set Write to 1 to set edge triggered interrupt flag 23 5 7 ACMPn_IFC Interrupt Flag Clear Register Offset Bit Po...

Page 364: ...ION ACMPPEN Bit Name Reset Access Description 31 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 9 8 LOCATION 0x0 RW I O Location Decides the location of the ACMP I O pin Value Mode Description 0 LOC0 Location 0 1 LOC1 Location 1 7 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Sec...

Page 365: ...ator is used to monitor the supply voltage from software An interrupt can be generated when the supply falls below or rises above a programmable threshold Note Note that VCMP comes in addition to the Power on Reset and Brown out Detector peripherals that both generate reset signals when the voltage supply is insufficient for reliable operation VCMP does not generate reset only interrupt Also note ...

Page 366: ... is called the warm up time The warm up time is a configurable number of HFPERCLK cycles set in WARMTIME which should be set to at least 10 µs When the comparator is enabled and warmed up the VCMPACT bit in VCMP_STATUS will be set to indicate that the comparator is active As long as the comparator is not enabled or not warmed up VCMPACT will be cleared and the comparator output value is set to the...

Page 367: ...uninteresting input fluctuations around zero and only show changes that are big enough to breach the hysteresis threshold Figure 24 2 VCMP 20 mV Hysteresis Enabled InNEG VCMPOUT with hysteresis InNEG 20mV InNEG 20mV VCMPOUT without hysteresis Time InPOS 24 3 4 Input Selection The positive comparator input is always connected to the scaled power supply input The negative comparator input is connect...

Page 368: ...mparator output respectively An interrupt request will be sent if the EDGE interrupt flag in VCMP_IF is set and enabled through the EDGE bit in VCMPn_IEN The edge interrupt can also be used to wake up the device from EM3 EM1 VCMP also includes an interrupt flag WARMUP in VCMP_IF which is set when a warm up sequence has finished An interrupt request will be sent if the WARMUP interrupt flag in VCMP...

Page 369: ...e information in Section 2 1 p 3 30 HALFBIAS 1 RW Half Bias Current Set this bit to 1 to halve the bias current Table 24 1 p 366 29 28 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 27 24 BIASPROG 0x7 RW VCMP Bias Programming Value These bits control the bias current level Table 24 1 p 366 23 18 Reserved To ensure compatibility with ...

Page 370: ...able voltage supply comparator 24 5 2 VCMP_INPUTSEL Input Selection Register Offset Bit Position 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x00 Access RW RW Name LPREF TRIGLEVEL Bit Name Reset Access Description 31 9 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 8 LPREF 0 RW ...

Page 371: ...eset Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 WARMUP 0 RW Warm up Interrupt Enable Enable disable interrupt on finished warm up 0 EDGE 0 RW Edge Trigger Interrupt Enable Enable disable edge triggered interrupt 24 5 5 VCMP_IF Interrupt Flag Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 2...

Page 372: ...g Set Write to 1 to set warm up finished interrupt flag 0 EDGE 0 W1 Edge Triggered Interrupt Flag Set Write to 1 to set edge triggered interrupt flag 24 5 7 VCMP_IFC Interrupt Flag Clear Register Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 Access W1 W1 Name WARMUP EDGE Bit Name Reset Access Description 31 2 Reserved To e...

Page 373: ...ty cycled to reduce the energy consumption 25 1 Introduction The ADC is a Successive Approximation Register SAR architecture with a resolution of up to 12 bits at up to one million samples per second The integrated input mux can select inputs from 8 external pins and 6 internal signals 25 2 Features Programmable resolution 6 8 12 bit 13 prescaled clock ADC_CLK cycles per conversion Maximum 1 MSPS ...

Page 374: ... flag set when overwriting unread results Hardware oversampling support 1st order accumulate and dump filter From 2 to 4096 oversampling ratio OSR Results in 16 bit representation Enabled individually for scan sequence and single sample mode Common OSR select Individually selectable voltage reference for scan and single mode Internal 1 25V reference Internal 2 5V reference VDD Internal 5 V differe...

Page 375: ...n during the approximation phase The acquisition time can be configured independently for scan and single conversions see Section 25 3 7 p 379 by setting AT in ADCn_SINGLECTRL ADCn_SCANCTRL The acquisition times can be set to any integer power of 2 from 1 to 256 ADC_CLK cycles Note For high impedance sources the acquisition time should be adjusted to allow enough time for the internal sample capac...

Page 376: ...d for scan mode can be kept warm If a different bandgap reference is selected for single mode the warm up time still applies NORMAL ADC and references are shut off when there are no samples waiting a in Figure 25 3 p 377 shows this mode used with an internal bandgap reference Figure d shows this mode when using VDD or an external reference FASTBG Bandgap warm up is eliminated but with reduced refe...

Page 377: ...NGLECTRL and ADCn_SCANCTRL For offset calibration purposes it is possible to internally short the differential ADC inputs and thereby measure a 0 V differential Differential 0 V is selected by writing the DIFF bit to 1 and INPUTSEL to 4 in ADCn_SINGLECTRL Calibration is described in detail in Section 25 3 10 p 382 Note When VDD 3 is sampled the acquisition time should be above a lower limit The re...

Page 378: ...r the device 25 3 5 Reference Selection The reference voltage can be selected from these sources 1 25 V internal bandgap 2 5 V internal bandgap VDD 5 V internal differential bandgap External single ended input from Ch 6 Differential input 2x Ch 6 Ch 7 Unbuffered 2xVDD The 2 5 V reference needs a supply voltage higher than 2 5 V The differential 5 V reference needs a supply voltage higher than 2 75...

Page 379: ...n samples 25 3 7 1 Single Sample Mode The single sample mode can be used to convert a single sample either once per trigger or repetitively The configuration of the single sample mode is done in the ADCn_SINGLECTRL register and the results are found in the ADCn_SINGLEDATA register The SINGLEDV bit in ADCn_STATUS is set high when there is valid data in the result register and is cleared when the da...

Page 380: ...eared The SINGLEACT and SCANACT bits in ADCn_STATUS are set high when the modes are actively converting or have pending conversions It is also possible to trigger conversions from PRS signals The system requires one HFPERCLK cycle pulses to trigger conversions Setting PRSEN in ADCn_SINGLECTRL ADCn_SCANCTRL enables triggering from PRS input Which PRS channel to listen to is defined by PRSSEL in ADC...

Page 381: ...dividually for each mode Set RES in ADCn_SINGLECTRL ADCn_SCANCTRL to 0x3 The oversampling rate OVSRSEL in ADCn_CTRL can be set to any integer power of 2 from 2 to 4096 and the configuration is shared between the scan and single sample mode OVSRSEL field in ADCn_CTRL With oversampling each selected input is sampled a number given by the OVSR of times and the results are filtered by a first order ac...

Page 382: ... have separate interrupt flags indicating finished conversions Setting one of these flags will result in an ADC interrupt if the corresponding interrupt enable bit is set in ADCn_IEN In addition to the finished conversion flags there is a scan and single sample result overflow flag which signalizes that a result from a scan sequence or single sample has been overwritten before being read A finishe...

Page 383: ...the ADCn_SINGLECTRL register to 16CYCLES 3 Set the INPUTSEL bitfield of the ADCn_SINGLECTRL register to DIFF0 and set the DIFF bitfield to 1 for enabling differential input Since the input voltage is 0 the expected ADC output is the half of the ADC code range as it is in differential mode 4 A binary search is used to find the offset calibration value Set the SINGLESTART bit in the ADCn_CMD registe...

Page 384: ...Calibration Register 0x03C ADCn_BIASPROG RW Bias Programming Register 25 5 Register Description 25 5 1 ADCn_CTRL Control Register Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x1F 0x00 0x0 0 0x0 Access RW RW RW RW RW RW Name OVSRSEL TIMEBASE PRESC LPFMODE TAILGATE WARMUPMODE Bit Name Reset Access Description 31 28 Reserve...

Page 385: ...ts to 0 More information in Section 2 1 p 3 5 4 LPFMODE 0x0 RW Low Pass Filter Mode These bits control the filtering of the ADC input Details on the filter characteristics can be found in the device datasheets Value Mode Description 0 BYPASS No filter or decoupling capacitor 1 DECAP On chip decoupling capacitor selected 2 RCFILT On chip RC filter selected 3 TAILGATE 0 RW Conversion Tailgating Enab...

Page 386: ...tes Value Mode Description 0 CH0 Single ended mode SCANDATA result originates from ADCn_CH0 Differential mode SCANDATA result originates from ADCn_CH0 ADCn_CH1 1 CH1 Single ended mode SCANDATA result originates from ADCn_CH1 Differential mode SCANDATA result originates from ADCn_CH2_ADCn_CH3 2 CH2 Single ended mode SCANDATA result originates from ADCn_CH2 Differential mode SCANDATA result originat...

Page 387: ...lect PRS trigger for single sample Value Mode Description 0 PRSCH0 PRS ch 0 triggers single sample 1 PRSCH1 PRS ch 1 triggers single sample 2 PRSCH2 PRS ch 2 triggers single sample 3 PRSCH3 PRS ch 3 triggers single sample 4 PRSCH4 PRS ch 4 triggers single sample 5 PRSCH5 PRS ch 5 triggers single sample 6 PRSCH6 PRS ch 6 triggers single sample 7 PRSCH7 PRS ch 7 triggers single sample 27 25 Reserved...

Page 388: ... input to ADC single sample mode in either single ended mode or differential mode DIFF 0 Mode Value Description CH0 0 ADCn_CH0 CH1 1 ADCn_CH1 CH2 2 ADCn_CH2 CH3 3 ADCn_CH3 CH4 4 ADCn_CH4 CH5 5 ADCn_CH5 CH6 6 ADCn_CH6 CH7 7 ADCn_CH7 TEMP 8 Temperature reference VDDDIV3 9 VDD 3 VDD 10 VDD VSS 11 VSS VREFDIV2 12 VREF 2 DAC0OUT0 13 DAC0 output 0 DAC0OUT1 14 DAC0 output 1 DIFF 1 Mode Value Description ...

Page 389: ...ess RW RW RW RW RW RW RW RW RW Name PRSSEL PRSEN AT REF INPUTMASK RES ADJ DIFF REP Bit Name Reset Access Description 31 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 30 28 PRSSEL 0x0 RW Scan Sequence PRS Trigger Select Select PRS trigger for scan sequence Value Mode Description 0 PRSCH0 PRS ch 0 triggers scan sequence 1 PRSCH1 PRS c...

Page 390: ...buffered 2xVDD 15 8 INPUTMASK 0x00 RW Scan Sequence Input Mask Set one or more bits in this mask to select which inputs are included the scan sequence in either single ended or differential mode DIFF 0 Mode Value Description CH0 00000001 ADCn_CH0 included in mask CH1 00000010 ADCn_CH1 included in mask CH2 00000100 ADCn_CH2 included in mask CH3 00001000 ADCn_CH3 included in mask CH4 00010000 ADCn_C...

Page 391: ... 6 ADCn_IEN Interrupt Enable Register Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 Access RW RW RW RW Name SCANOF SINGLEOF SCAN SINGLE Bit Name Reset Access Description 31 10 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 9 SCANOF 0 RW Scan Result Overfl...

Page 392: ...te when this bit is set 0 SINGLE 0 R Single Conversion Complete Interrupt Flag Indicates single conversion complete when this bit is set 25 5 8 ADCn_IFS Interrupt Flag Set Register Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 Access W1 W1 W1 W1 Name SCANOF SINGLEOF SCAN SINGLE Bit Name Reset Access Description 31 10 R...

Page 393: ...lag Clear Write to 1 to clear single result overflow interrupt flag 7 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 SCAN 0 W1 Scan Conversion Complete Interrupt Flag Clear Write to 1 to clear scan conversion complete interrupt flag 0 SINGLE 0 W1 Single Conversion Complete Interrupt Flag Clear Write to 1 to clear single conversio...

Page 394: ...Data The register holds the results from the last scan conversion Reading this field clears the SCANDV bit in the ADCn_STATUS register 25 5 12 ADCn_SINGLEDATAP Single Conversion Result Data Peek Register Offset Bit Position 0x02C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access R Name DATAP Bit Name Reset Access Description 31 0 DATAP 0x...

Page 395: ...lue for the 1V25 internal reference during reset hence the reset value might differ from device to device The field is unsigned Higher values lead to higher ADC results 23 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 22 16 SCANOFFSET 0x00 RW Scan Mode Offset Calibration Value This register contains the offset calibration value used...

Page 396: ...3 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x7 1 0x7 Access RW RW RW Name COMPBIAS HALFBIAS BIASPROG Bit Name Reset Access Description 31 12 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 11 8 COMPBIAS 0x7 RW Comparator Bias Value These bits are used to adjust the bias current to the ADC Comparator 7 Reserved ...

Page 397: ...onvert a digital value to an analog output voltage The DAC is fully differential rail to rail with 12 bit resolution It has two single ended output buffers which can be combined into one differential output The DAC may be used for a number of different applications such as sensor interfaces or sound output 26 2 Features 500 ksamples s operation Two single ended output channels Can be combined into...

Page 398: ...ode In sample hold mode the DAC core converts data on a triggered conversion and then holds the output in a sample hold element When not converting the DAC core is turned off between samples which reduces the power consumption Because of output voltage drift the sample hold element will only hold the output for a certain period without a refresh conversion The reader is referred to the electrical ...

Page 399: ...and the DAC_CLK should not be set higher than 1 MHz Normally the PRESCALER runs continuously when either of the channels are enabled When running with a prescaler setting higher than 0 there will be an unpredictable delay from the time the conversion was triggered to the time the actual conversion takes place This is because the conversions is controlled by the prescaled clock and the conversion c...

Page 400: ...le Ended Output When operating in single ended mode the channel 0 output is on DACn_OUT0 and the channel 1 output is on DACn_OUT1 The output voltage can be calculated using Equation 26 2 p 400 DAC Single Ended Output Voltage VOUT VDACn_OUTx VSS Vref x CHxDATA 4095 26 2 where CHxDATA is a 12 bit unsigned integer 26 3 4 2 Differential Output When operating in differential mode both DAC outputs are u...

Page 401: ...and that new data can be written to the data registers Setting one of these flags will result in a DAC interrupt if the corresponding interrupt enable bit is set in DACn_IEN All generated interrupts from the DAC will activate the same interrupt vector when enabled The DAC has two PRS outputs which will carry a one cycle HFPERCLK high pulse when the corresponding channel has finished a conversion 2...

Page 402: ...channel through the CHxOFFSET bit fields Gain is calibrated in one common register field GAIN The gain calibration is linked to the reference and when the reference is changed the gain must be re calibrated Gain and offset for the 1V25 2V5 and VDD references are calibrated during production and the calibration values for these can be found in the Device Information page During reset the gain and o...

Page 403: ... 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0x0 0x0 0 0 0x1 0x0 0 0 Access RW RW RW RW RW RW RW RW RW Name REFRSEL PRESC REFSEL CH0PRESCRST OUTENPRS OUTMODE CONVMODE SINEMODE DIFF Bit Name Reset Access Description 31 22 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 21 20 REFRSEL 0x0 RW Refresh Interval Select Select refresh ...

Page 404: ...l of DAC output enable Value Description 0 DAC output enable always on 1 DAC output enable controlled by PRS signal selected for CH1 5 4 OUTMODE 0x1 RW Output Mode Select output mode Value Mode Description 0 DISABLE DAC output to pin and ADC disabled 1 PIN DAC output to pin enabled DAC output to ADC disabled 2 ADC DAC output to pin disabled DAC output to ADC enabled 3 PINADC DAC output to pin and ...

Page 405: ...2 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0 0 0 0 Access RW RW RW RW Name PRSSEL PRSEN REFREN EN Bit Name Reset Access Description 31 7 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 6 4 PRSSEL 0x0 RW Channel 0 PRS Trigger Select Select Channel 0 PRS input channel Value Mode Description 0 PRSCH0 PRS ch 0 triggers channel 0 conversion 1 PRS...

Page 406: ...er Select Select Channel 1 PRS input channel Value Mode Description 0 PRSCH0 PRS ch 0 triggers channel 1 conversion 1 PRSCH1 PRS ch 1 triggers channel 1 conversion 2 PRSCH2 PRS ch 2 triggers channel 1 conversion 3 PRSCH3 PRS ch 3 triggers channel 1 conversion 4 PRSCH4 PRS ch 4 triggers channel 1 conversion 5 PRSCH5 PRS ch 5 triggers channel 1 conversion 6 PRSCH6 PRS ch 6 triggers channel 1 convers...

Page 407: ...hannel 1 conversion complete interrupt 0 CH0 0 RW Channel 0 Conversion Complete Interrupt Enable Enable disable channel 0 conversion complete interrupt 26 5 6 DACn_IF Interrupt Flag Register Offset Bit Position 0x014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 Access R R R R Name CH1UF CH0UF CH1 CH0 Bit Name Reset Access Description 31 6 Rese...

Page 408: ...omplete interrupt flag 0 CH0 0 W1 Channel 0 Conversion Complete Interrupt Flag Set Write to 1 to set channel 0 conversion complete interrupt flag 26 5 8 DACn_IFC Interrupt Flag Clear Register Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 Access W1 W1 W1 W1 Name CH1UF CH0UF CH1 CH0 Bit Name Reset Access Description 31 6...

Page 409: ...nel 1 Data Register Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x000 Access RW Name DATA Bit Name Reset Access Description 31 12 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 11 0 DATA 0x000 RW Channel 1 Data This register contains the value which will be con...

Page 410: ... compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 13 8 CH1OFFSET 0x00 RW Channel 1 Offset Calibration Value This register contains the offset calibration value used with channel 1 conversions This field is set to the production channel 1 offset calibration value for the 1V25 internal reference during reset hence the reset value might differ from device t...

Page 411: ...11 www silabs com Bit Name Reset Access Description Set this bit to halve the bias current 5 4 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 3 0 BIASPROG 0x7 RW Bias Programming Value These bits control the bias current level ...

Page 412: ...LK cycles with 256 bit keys The AES module is an AHB slave which enables efficient access to the data and key registers All write accesses to the AES module must be 32 bit operations i e 8 or 16 bit operations are not supported 27 2 Features AES hardware encryption decryption 128 bit key 54 HFCORECLK cycles 256 bit key 75 HFCORECLK cycles Efficient CPU DMA support Interrupt on finished encryption ...

Page 413: ...ss The AES module contains a 128 bit DATA State register and two 128 bit KEY registers defined as DATA3 DATA0 KEY3 KEY0 KEYL and KEY7 KEY4 KEYH In AES128 mode the 128 bit key is read from KEYL while both KEYH and KEYL are used in AES256 mode See Figure 27 2 p 413 The figure presents the key byte order for 256 bit keys In 128 bit mode a16 represents the first byte of the 128 bit key It is important...

Page 414: ...turned into the CipherKey during the encryption The opposite applies when decrypting where you have to re supply the CipherKey between each block However in AES128 mode KEY4 KEY7 can be used as a buffer register to hold an extra copy of the KEY3 KEY0 registers When KEYBUFEN is set in AES_CTRL the contents of KEY7 KEY4 are copied to KEY3 KEY0 when an encryption decryption is started This eliminates...

Page 415: ...orm Cipher Block Chaining with 128 bit keys Example 27 1 AES Cipher Block Chaining 1 Configure module to encryption key buffer enabled and XORSTART in AES_CTRL 2 Write 128 bit initialization vector to AES_DATA starting with least significant word 3 Write PlainKey to AES_KEYHn starting with least significant word 4 Write PlainText to AES_XORDATA starting with least significant word Encryption will ...

Page 416: ...egister 0x048 AES_KEYHC RW KEY High Register 0x04C AES_KEYHD RW KEY High Register 27 5 Register Description 27 5 1 AES_CTRL Control Register Offset Bit Position 0x000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 Access RW RW RW RW RW Name XORSTART DATASTART KEYBUFEN AES256 DECRYPT Bit Name Reset Access Description 31 6 Reserved To ensure com...

Page 417: ...t Access Description 31 2 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 1 STOP 0 W1 Encryption Decryption Stop Set to stop encryption decryption 0 START 0 W1 Encryption Decryption Start Set to start encryption decryption 27 5 3 AES_STATUS Status Register Offset Bit Position 0x008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14...

Page 418: ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access R Name DONE Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 DONE 0 R Encryption Decryption Done Interrupt Flag Set when an encryption decryption has finished 27 5 6 AES_IFS Interrupt Flag Set R...

Page 419: ...rmation in Section 2 1 p 3 0 DONE 0 W1 Encryption Decryption Done Interrupt Flag Clear Write to 1 to clear encryption decryption done interrupt flag 27 5 8 AES_DATA DATA Register Offset Bit Position 0x01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name DATA Bit Name Reset Access Description 31 0 DATA 0x00000000 RW Data Access Ac...

Page 420: ...22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name KEYLA Bit Name Reset Access Description 31 0 KEYLA 0x00000000 RW Key Low Access A Access the low key words through this register 27 5 11 AES_KEYLB KEY Low Register Offset Bit Position 0x034 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name K...

Page 421: ...y Low Access C Access the low key words through this register 27 5 13 AES_KEYLD KEY Low Register Offset Bit Position 0x03C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name KEYLD Bit Name Reset Access Description 31 0 KEYLD 0x00000000 RW Key Low Access D Access the low key words through this register 27 5 14 AES_KEYHA KEY High Reg...

Page 422: ...1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name KEYHB Bit Name Reset Access Description 31 0 KEYHB 0x00000000 RW Key High Access B Access the high key words through this register 27 5 16 AES_KEYHC KEY High Register Offset Bit Position 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name KE...

Page 423: ...27 5 17 AES_KEYHD KEY High Register Offset Bit Position 0x04C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name KEYHD Bit Name Reset Access Description 31 0 KEYHD 0x00000000 RW Key High Access D Access the high key words through this register ...

Page 424: ... locations thus solving congestion issues that may arise with multiple functions on the same pin Fully asynchronous interrupts can also be generated from any pin 28 1 Introduction In the EFM32G devices the General Purpose Input Output GPIO pins are organized into ports with up to 16 pins each These pins can individually be configured as either an output or input More advanced configurations like o...

Page 425: ... indicates the pin number 0 1 15 Fewer than 16 bits may be available on some ports depending on the total number of I O pins on the package After a reset both input and output is disabled for all pins on the device except for debug pins To use a pin the port GPIO_Px_MODEL GPIO_Px_MODEH registers must be configured for the pin to make it an input or output These registers can also do more advanced ...

Page 426: ...tection block against over voltage 28 3 1 Pin Configuration In addition to setting the pins as either outputs or inputs the GPIO_Px_MODEL and GPIO_Px_MODEH registers can be used for more advanced configurations GPIO_Px_MODEL contains 8 bit fields named MODEn n 0 1 7 which control pins 0 7 while GPIO_Px_MODEH contains 8 bit fields named MODEn n 8 9 15 which control pins 8 15 In some modes GPIO_Px_D...

Page 427: ...h pull up and filter MODEn determines which mode the pin is in at a given time Setting MODEn to 0b0000 disables the pin reducing power consumption to a minimum When the output driver is disabled the pin can be used as a connection for an analog module e g ADC LCD Input is enabled by setting MODEn to any value other than 0b0000 The pull up pull down and filter function can optionally be applied to ...

Page 428: ... all other output modes the drive strength is set to STANDARD 28 3 1 1 Configuration Lock GPIO_Px_MODEL GPIO_Px_MODEH GPIO_Px_CTRL GPIO_Px_PINLOCKN GPIO_EXTIPSELL GPIO_EXTIPSELH GPIO_INSENSE and GPIO_ROUTE can be locked by writing any other value than 0xA534 to GPIO_LOCK Writing the value 0xA534 to the GPIOx_LOCK register unlocks the configuration registers In addition to configuration lock GPIO_P...

Page 429: ...tate as enabled If you do disable the debug pins make sure you have at least a 3 second timeout at the start of your program code before you disable the debug pins This way the debugger will have time to halt the device after a reset before the pins are disabled The Serial Wire Viewer Output pin SWO can be enabled by setting the SWOPEN bit in GPIO_ROUTE This bit can also be routed to alternate loc...

Page 430: ...n which the output n should be taken is selected by the EXTIPSELn 3 0 bits in the GPIO_EXTIPSELL or the GPIO_EXTIPSELH registers 28 3 5 Synchronization To avoid metastability in synchronous logic connected to the pins all inputs are synchronized with double flip flops The flip flops for the input data run on the HFCORECLK Consequently when a pin changes state the change will have propagated to GPI...

Page 431: ...ta Out Toggle Register 0x040 GPIO_PB_DIN R Port Data In Register 0x044 GPIO_PB_PINLOCKN RW Port Unlocked Pins Register 0x048 GPIO_PC_CTRL RW Port Control Register 0x04C GPIO_PC_MODEL RW Port Pin Mode Low Register 0x050 GPIO_PC_MODEH RW Port Pin Mode High Register 0x054 GPIO_PC_DOUT RW Port Data Out Register 0x058 GPIO_PC_DOUTSET W1 Port Data Out Set Register 0x05C GPIO_PC_DOUTCLR W1 Port Data Out ...

Page 432: ... Port Select Low Register 0x104 GPIO_EXTIPSELH RW External Interrupt Port Select High Register 0x108 GPIO_EXTIRISE RW External Interrupt Rising Edge Trigger Register 0x10C GPIO_EXTIFALL RW External Interrupt Falling Edge Trigger Register 0x110 GPIO_IEN RW Interrupt Enable Register 0x114 GPIO_IF R Interrupt Flag Register 0x118 GPIO_IFS W1 Interrupt Flag Set Register 0x11C GPIO_IFC W1 Interrupt Flag...

Page 433: ...ODE0 11 8 MODE2 0x0 RW Pin 2 Mode Configure mode for pin 2 Enumeration is equal to MODE0 7 4 MODE1 0x0 RW Pin 1 Mode Configure mode for pin 1 Enumeration is equal to MODE0 3 0 MODE0 0x0 RW Pin 0 Mode Configure mode for pin 0 Value Mode Description 0 DISABLED Input disabled Pullup if DOUT is set 1 INPUT Input enabled Filter if DOUT is set 2 INPUTPULL Input enabled DOUT determines pull direction 3 I...

Page 434: ...0 Enumeration is equal to MODE8 7 4 MODE9 0x0 RW Pin 9 Mode Configure mode for pin 9 Enumeration is equal to MODE8 3 0 MODE8 0x0 RW Pin 8 Mode Configure mode for pin 8 Value Mode Description 0 DISABLED Input disabled Pullup if DOUT is set 1 INPUT Input enabled Filter if DOUT is set 2 INPUTPULL Input enabled DOUT determines pull direction 3 INPUTPULLFILTER Input enabled with filter DOUT determines ...

Page 435: ... on port 28 5 5 GPIO_Px_DOUTSET Port Data Out Set Register Offset Bit Position 0x010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access W1 Name DOUTSET Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 DOUTSET 0x0000 W1 Data Out Set Write...

Page 436: ... 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access W1 Name DOUTTGL Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 DOUTTGL 0x0000 W1 Data Out Toggle Write bits to 1 to toggle corresponding bits in GPIO_Px_DOUT Bits written to 0 will have no effect 28 5 8 GPIO_Px_DIN Port Data In Register Off...

Page 437: ...s Description 31 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 30 28 EXTIPSEL7 0x0 RW External Interrupt 7 Port Select Select input port for external interrupt 7 Value Mode Description 0 PORTA Port A pin 7 selected for external interrupt 7 1 PORTB Port B pin 7 selected for external interrupt 7 2 PORTC Port C pin 7 selected for exter...

Page 438: ...e information in Section 2 1 p 3 14 12 EXTIPSEL3 0x0 RW External Interrupt 3 Port Select Select input port for external interrupt 3 Value Mode Description 0 PORTA Port A pin 3 selected for external interrupt 3 1 PORTB Port B pin 3 selected for external interrupt 3 2 PORTC Port C pin 3 selected for external interrupt 3 3 PORTD Port D pin 3 selected for external interrupt 3 4 PORTE Port E pin 3 sele...

Page 439: ...d To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 30 28 EXTIPSEL15 0x0 RW External Interrupt 15 Port Select Select input port for external interrupt 15 Value Mode Description 0 PORTA Port A pin 15 selected for external interrupt 15 1 PORTB Port B pin 15 selected for external interrupt 15 2 PORTC Port C pin 15 selected for external interrupt 15...

Page 440: ...TB Port B pin 11 selected for external interrupt 11 2 PORTC Port C pin 11 selected for external interrupt 11 3 PORTD Port D pin 11 selected for external interrupt 11 4 PORTE Port E pin 11 selected for external interrupt 11 5 PORTF Port F pin 11 selected for external interrupt 11 11 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 10 8 ...

Page 441: ...10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access RW Name EXTIRISE Bit Name Reset Access Description 31 16 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 EXTIRISE 0x0000 RW External Interrupt n Rising Edge Trigger Enable Set bit n to enable triggering of external interrupt n on rising edge Value Description EXTIRISE n 0 Rising edge tri...

Page 442: ...compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 EXT 0x0000 RW External Interrupt n Enable Set bit n to enable external interrupt from pin n Value Description EXT n 0 Pin n external interrupt disabled EXT n 1 Pin n external interrupt enabled 28 5 15 GPIO_IF Interrupt Flag Register Offset Bit Position 0x114 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 443: ... EXT 0x0000 W1 External Interrupt Flag n Set Write bit n to 1 to set interrupt flag n Value Description EXT n 0 Pin n external interrupt flag unchanged EXT n 1 Pin n external interrupt flag set 28 5 17 GPIO_IFC Interrupt Flag Clear Register Offset Bit Position 0x11C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x0000 Access W1 Name EXT Bit Name Reset ...

Page 444: ... pin back to a default state as enabled If you disable this pin make sure you have at least a 3 second timeout at the start of you program code before you disable the pin This way the debugger will have time to halt the device after a reset before the pin is disabled 0 SWCLKPEN 1 RW Serial Wire Clock Pin Enable Enable Serial Wire Clock connection to pin WARNING When this pin is disabled the device...

Page 445: ...sure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 15 0 LOCKKEY 0x0000 RW Configuration Lock Key Write any other value than the unlock code to lock MODEL MODEH CTRL PINLOCKN EPISELL EIPSELH INSENSE and SWDPROUTE from editing Write the unlock code to unlock When reading the register bit 0 is set when the lock is enabled Mode Value Description Read Oper...

Page 446: ...exing modes make the EFM32G the optimal choice for battery driven systems with LCD panels 29 1 Introduction The LCD driver is capable of driving a segmented LCD display with up to 4x40 segments A voltage boost function enables it to provide the LCD display with higher voltage than the supply voltage for the device In addition an animation feature can run custom animations on the LCD display withou...

Page 447: ...y the LCD driver By default LCD_COM0 is driven whenever the LCD driver is enabled The LCD_SEGEN register determines which segment lines are enabled Segment lines can be Each LCD segment pin can also be individually disabled by setting the pin to any other state than DISABLED in the GPIO pin configuration Note that this feature is not available on EFM32G revisions A and B 29 3 2 Multiplexing Bias a...

Page 448: ... Half Bias 1 2 Bias 3 levels 10 Third Bias 1 3 Bias 4 levels 11 Fourth Bias 1 4 Bias 5 levels Table 29 3 LCD Wave Settings WAVE Mode Wave mode 0 LowPower Low power optimized waveform output 1 Normal Regular waveform output Figure 29 2 LCD Low power Waveform for LCD_COM0 in Quadruples Multiplex Mode 1 3 Bias VLC0 VLCD VLC1 2 3VLCD VLC3 VSS VLC2 1 3VLCD Frame Start Frame End Figure 29 3 LCD Normal W...

Page 449: ... Bias and Duplex Multiplexing In this mode each frame is divided into 4 periods LCD_COM 1 0 lines can be multiplexed with all segment lines Figures show 1 2 bias and duplex multiplexing waveforms show two frames Figure 29 5 LCD 1 2 Bias and Duplex Multiplexing LCD_COM0 VLC0 VLCD VLC1 1 2VLCD VLC3 VSS Frame Start Frame End Figure 29 6 LCD 1 2 Bias and Duplex Multiplexing LCD_COM1 VLC0 VLCD VLC1 1 2...

Page 450: ... duplex multiplexing LCD_SEG0 LCD_COM0 DC voltage 0 over one frame VRMS 0 79 VLCD_OUT The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be ON with this waveform Figure 29 9 LCD 1 2 Bias and Duplex Multiplexing LCD_SEG0 LCD_COM0 VLC0 VLCD VLC3 VSS VLC0 VLCD Frame Start Frame End VLC1 1 2VLCD VLC1 1 2VLCD 1 2 bias and duplex multiplexing LCD_SEG0 LCD_COM1 DC voltage 0 over one fr...

Page 451: ...multiplexing waveforms show two frames Figure 29 11 LCD 1 3 Bias and Duplex Multiplexing LCD_COM0 VLC0 VLCD VLC1 2 3VLCD VLC3 VSS VLC2 1 3VLCD Frame Start Frame End Figure 29 12 LCD 1 3 Bias and Duplex Multiplexing LCD_COM1 VLC0 VLCD VLC3 VSS Frame Start Frame End VLC1 2 3VLCD VLC2 1 3VLCD 1 3 bias and duplex multiplexing LCD_SEG0 The LCD_SEG0 waveform on the left is just an example to illustrate ...

Page 452: ...x multiplexing LCD_SEG0 LCD_COM0 DC voltage 0 over one frame VRMS 0 75 VLCD_OUT The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be ON with this waveform Figure 29 15 LCD 1 3 Bias and Duplex Multiplexing LCD_SEG0 LCD_COM0 VLC3 VSS VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD Frame Start Frame End 1 3 bias and duplex multiplexing LCD_SEG0 LCD_COM0 DC ...

Page 453: ... Figure 29 17 LCD 1 2 Bias and Triplex Multiplexing LCD_COM0 VLC0 VLCD VLC1 1 2VLCD VLC3 VSS Frame Start Frame End Figure 29 18 LCD 1 2 Bias and Triplex Multiplexing LCD_COM1 VLC0 VLCD VLC1 1 2VLCD VLC3 VSS Frame Start Frame End Figure 29 19 LCD 1 2 Bias and Triplex Multiplexing LCD_COM2 VLC0 VLCD VLC1 1 2VLCD VLC3 VSS Frame Start Frame End 1 2 bias and triplex multiplexing LCD_SEG0 The LCD_SEG0 w...

Page 454: ...MS 0 4 VLCD_OUT The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be OFF with this waveform Figure 29 22 LCD 1 2 Bias and Triplex Multiplexing LCD_SEG0 LCD_COM0 VLC0 VLCD VLC3 VSS VLC0 VLCD VLC1 1 2VLCD VLC1 1 2VLCD Frame Start Frame End 1 2 bias and triplex multiplexing LCD_SEG0 LCD_COM1 DC voltage 0 over one frame VRMS 0 7 VLCD_OUT The LCD display pixel that is connected to L...

Page 455: ...art Frame End 29 3 3 5 Waveforms with 1 3 Bias and Triplex Multiplexing In this mode each frame is divided into 6 periods LCD_COM 2 0 lines can be multiplexed with all segment lines Figures show 1 3 bias and triplex multiplexing waveforms show two frames Figure 29 25 LCD 1 3 Bias and Triplex Multiplexing LCD_COM0 VLC0 VLCD VLC3 VSS VLC1 2 3VLCD VLC2 1 3VLCD Frame Start Frame End Figure 29 26 LCD 1...

Page 456: ...C0 VLCD VLC3 VSS VLC1 2 3VLCD VLC2 1 3VLCD Frame Start Frame End Figure 29 29 LCD 1 3 Bias and Triplex Multiplexing LCD_SEG0 Connection com1 com2 com0 seg0 1 3 bias and triplex multiplexing LCD_SEG0 LCD_COM0 DC voltage 0 over one frame VRMS 0 33 VLCD_OUT The LCD display pixel that is connected to LCD_SEG0 and LCD_COM0 will be OFF with this waveform Figure 29 30 LCD 1 3 Bias and Triplex Multiplexin...

Page 457: ...connected to LCD_SEG0 and LCD_COM2 will be OFF with this waveform Figure 29 32 LCD 1 3 Bias and Triplex Multiplexing LCD_SEG0 LCD_COM2 VLC3 VSS VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD Frame Start Frame End 29 3 3 6 Waveforms with 1 3 Bias and Quadruplex Multiplexing In this mode each frame is divided into 8 periods All COM lines can be multiplexed with all segment l...

Page 458: ...ultiplexing LCD_COM3 VLC0 VLCD VLC1 2 3VLCD VLC3 VSS VLC2 1 3VLCD Frame Start Frame End 1 3 bias and quadruplex multiplexing LCD_SEG0 The LCD_SEG0 waveform on the left is just an example to illustrate how different segment waveforms can be multiplexed with the COM lines in order to turn on and off LCD pixels As illustrated in the figures below this wave form will turn ON pixels connected to LCD_CO...

Page 459: ...M0 VLC3 VSS VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD Frame Start Frame End 1 3 bias and quadruplex multiplexing LCD_SEG0 LCD_COM1 DC voltage 0 over one frame VRMS 0 33 VLCD_OUT The LCD display pixel that is connected to LCD_SEG0 and LCD_COM1 will be OFF with this waveform Figure 29 40 LCD 1 3 Bias and Quadruplex Multiplexing LCD_SEG0 LCD_COM1 VLC3 VSS VLC0 VLCD VLC1 ...

Page 460: ...29 3 4 LCD Contrast Different LCD panels have different characteristics and also temperature may affect the characteristics of the LCD panels To compensate for such variations the LCD driver has a programmable contrast that adjusts the VLCD_OUT The contrast is set by CONLEV in LCD_DISPCTRL and can be adjusted relative to either VDD VLCD or Ground using CONCONF in LCD_DISPCTRL See Table 29 4 p 460 ...

Page 461: ... VLCD R0 R1 Rx VLCD_OUT VLC0 VLC1 VLC3 VLCD R0 R1 Rx VLCD_OUT VLC0 VLC1 VLC3 VLCD R0 R1 VLCD_OUT Static VLC0 VLC3 VLCD R0 Rx VLCD_OUT VLC0 VLC3 R0 VLCD Rx VLCD_OUT VLC0 VLC3 VLCD VLCD_OUT R0 R1 R2 R3 in the figure while Rx is adjusted by changing the CONLEV bits 29 3 5 VLCD Selection By default the LCD driver runs on main external power VLCD VDD see Table 29 7 p 462 An internal boost circuit can b...

Page 462: ...RL see Table 29 8 p 462 It is possible to adjust the frequency to optimize performance for all kinds of LCD panels large capacitors may require less frequent updates while small capacitors may require more frequent updates A lower update frequency would in general lead to smaller current consumption Table 29 8 LCD VBOOST Frequency VBFDIV VBOOST Update Frequency 000 LFACLK 001 LFACLK 2 010 LFACLK 4...

Page 463: ...he LCD data and Control Registers are clocked on the HFCORECLK To avoid metastability and unpredictable behavior the data in the Segment Data SEGDn registers must be synchronized to the LCD driver logic Also it is important that data is updated at the beginning of an LCD frame since the segment waveform depends on the segment data and a change in the middle of a frame may lead to a DC component in...

Page 464: ...le 29 11 FCPRESC FCPRESC Mode Description General equation 00 Div1 CLKFRAME 1 01 Div2 CLKFRAME 2 10 Div4 CLKFRAME 4 11 Div8 CLKFRAME 8 CLKFC CLKFRAME 2 FCPRESC The top value for the Frame Counter is set by FCTOP in LCD_BACTRL Every time the frame counter reaches zero it is reloaded with the top value and at the same time an event which can cause an interrupt data update blink or an animation state...

Page 465: ...chronization of the blink feature The FC must be on for blink to work 29 3 11 2 Blank Setting BLANK in LCD_BACTRL will output the OFF waveform on all enabled segments effectively blanking the entire display Writing the BLANK bit to zero disables the blanking and segment data will be output as normal See Section 29 3 8 p 463 for details regarding synchronization of blank 29 3 11 3 Animation State M...

Page 466: ...te is displayed one CLKEVENT period see Section 29 3 9 p 464 By reading ASTATE in LCD_STATUS software can identify which state that is currently active in the state sequence Note that the shifting operation is performed on internal registers that are not accessible in SW when reading LCD_AREGA and LCD_AREGB the data that was original written will also be read back The SW must utilize the knowledge...

Page 467: ...imation pattern and frame counter AEN 1 FCEN 1 For updating data in the LCD while it is running an animation and the new animation data depends on the pattern visible on the LCD see the following example Example 29 3 LCD Animation Dependence Example Enable the LCD interrupt the interrupt will be triggered simultaneously as the Animation State machine changes state In the interrupt handler read bac...

Page 468: ...om 29 3 13 Register access Since this module is a Low Energy Peripheral and runs off a clock which is asynchronous to the HFCORECLK special considerations must be taken when accessing registers Please refer to Section 5 3 p 20 for a description on how to perform register accesses to Low Energy Peripherals ...

Page 469: ...D_SEGD1L RW Segment Data Low Register 1 0x048 LCD_SEGD2L RW Segment Data Low Register 2 0x04C LCD_SEGD3L RW Segment Data Low Register 3 0x050 LCD_SEGD0H RW Segment Data High Register 0 0x054 LCD_SEGD1H RW Segment Data High Register 1 0x058 LCD_SEGD2H RW Segment Data High Register 2 0x05C LCD_SEGD3H RW Segment Data High Register 3 0x060 LCD_FREEZE RW Freeze Register 0x064 LCD_SYNCBUSY R Synchroniza...

Page 470: ...s enabled and the driver will start outputting waveforms on the com segment lines 29 5 2 LCD_DISPCTRL Display Control Register Offset Bit Position 0x004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0x3 0 0 0x1F 0 0x0 0x0 Access RW RW RW RW RW RW RW RW Name MUXE VBLEV VLCDSEL CONCONF CONLEV WAVE BIAS MUX Bit Name Reset Access Description 31 23 Reserv...

Page 471: ...ese bits control the contrast setting according to this formula VLCD_OUT VLCD 0 5 1 CONLEV 31 Value Mode Description 0 MIN Minimum contrast 31 MAX Maximum contrast 7 5 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 4 WAVE 0 RW Waveform Selection This bit configures the output waveform Value Mode Description 0 LOWPOWER Low power wavef...

Page 472: ...on 0x00C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 0x0 0 0 0x0 0x0 0 0 0 Access RW RW RW RW RW RW RW RW RW Name FCTOP FCPRESC FCEN ALOGSEL AREGBSC AREGASC AEN BLANK BLINKEN Bit Name Reset Access Description 31 24 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 23 18 FCTOP 0x00 RW ...

Page 473: ...eforms are configured to blank the LCD display The Segment Data Registers are not affected when writing this bit Value Description 0 Display is not blanked 1 Display is blanked 0 BLINKEN 0 RW Blink Enable When this bit is set the Blink function is enabled Every ON segment will alternate between on and off at every Frame Counter Event 29 5 5 LCD_STATUS Status Register Offset Bit Position 0x010 31 3...

Page 474: ...gisters please see Section 5 3 p 20 Offset Bit Position 0x018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RW Name AREGB Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 AREGB 0x00 RW Animation Register B Data This register contains th...

Page 475: ... FC interrupt flag 29 5 10 LCD_IFC Interrupt Flag Clear Register Offset Bit Position 0x024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0 Access W1 Name FC Bit Name Reset Access Description 31 1 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 0 FC 0 W1 Frame Counter Interrupt Flag Clear W...

Page 476: ...0L Bit Name Reset Access Description 31 0 SEGD0L 0x00000000 RW COM0 Segment Data Low This register contains segment data for segment lines 0 31 for COM0 29 5 13 LCD_SEGD1L Segment Data Low Register 1 Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x044 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Page 477: ...Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x04C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name SEGD3L Bit Name Reset Access Description 31 0 SEGD3L 0x00000000 RW COM3 Segment Data Low This register contains segment data for segment lines 0 31 for COM3 29 5 16 LCD_SEGD0...

Page 478: ...ved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 SEGD1H 0x00 RW COM1 Segment Data High This register contains segment data for segment lines 32 39 for COM1 29 5 18 LCD_SEGD2H Segment Data High Register 2 Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x058 31 30 29 28 27 26 25...

Page 479: ...ture devices always write bits to 0 More information in Section 2 1 p 3 0 REGFREEZE 0 RW Register Update Freeze When set the update of the LCD is postponed until this bit is cleared Use this bit to update several registers simultaneously Value Mode Description 0 UPDATE Each write access to an LCD register is updated into the Low Frequency domain as soon as possible 1 FREEZE The LCD is not updated ...

Page 480: ...s being synchronized 10 SEGD2H 0 R SEGD2H Register Busy Set when the value written to SEGD2H is being synchronized 9 SEGD1H 0 R SEGD1H Register Busy Set when the value written to SEGD1H is being synchronized 8 SEGD0H 0 R SEGD0H Register Busy Set when the value written to SEGD0H is being synchronized 7 SEGD3L 0 R SEGD3L Register Busy Set when the value written to SEGD3L is being synchronized 6 SEGD...

Page 481: ...3 p 20 Offset Bit Position 0x0B8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00 Access RW Name SEGD5H Bit Name Reset Access Description 31 8 Reserved To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 SEGD5H 0x00 RW COM1 Segment Data High This register contains segment data for segment lines 3...

Page 482: ...d To ensure compatibility with future devices always write bits to 0 More information in Section 2 1 p 3 7 0 SEGD7H 0x00 RW COM3 Segment Data High This register contains segment data for segment lines 32 39 for COM3 29 5 26 LCD_SEGD4L Segment Data Low Register 4 Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x0CC 31 30 29 28 27 26 25 24...

Page 483: ...lines 0 23 for COM5 29 5 28 LCD_SEGD6L Segment Data Low Register 6 Async Reg For more information about Asynchronous Registers please see Section 5 3 p 20 Offset Bit Position 0x0D4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name SEGD6L Bit Name Reset Access Description 31 0 SEGD6L 0x00000000 RW COM6 Segment Data This register co...

Page 484: ...bs com Offset Bit Position 0x0D8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset 0x00000000 Access RW Name SEGD7L Bit Name Reset Access Description 31 0 SEGD7L 0x00000000 RW COM7 Segment Data This register contains segment data for segment lines 0 23 for COM7 ...

Page 485: ...rview section with new parts Updated HFXO LFXO startup description Updated the I2C Clock Mode table and added the Maximum Data Hold Time formula Added the minimum HFPERCLK requirement for I2C Slave Operation Added a new register access type RW1H Updated CMU_CALCNT description Updated DMA_CHENC register description Added LPFMODE recommendation for the ADC Input Filtering Updated WRITEONCE bitfield ...

Page 486: ...0 if AUTOTRI is set Updated general description of bus system Updated frequency limitations when clocking TIMER from external source Updated information on disabling of individual LCD segment lines 30 4 Revision 1 00 September 6th 2010 Changed PCNT_TOP reset value Parity bits not available for USART synchronous mode Corrected Scaled VDD equation in Section 23 3 4 p 357 DACOUT0 and DACOUT1 in ADCn_...

Page 487: ...dule the user does not have to issue LTOPBIM command to load TOPB to TOP so this bit has no effect Corrected AES 128 256 encryption decryption duration to 54 75 cycles Corrected description of AES byte order for data and key QEM in TIMERn_CTRL renamed to QDM Changed description of COIST in TIMERn_CCx_CTRL Changed DATA0 to CH0DATA and added COMBDATA in PRSEN field description in DACn_CH0CTRL Change...

Page 488: ...PUTSEL SINGLEREF in ADCn_SINGLECTRL renamed to REF SINGLEAT in ADCn_SINGLECTRL renamed to AT SINGLEPRSEN in ADCn_SINGLECTRL renamed to PRSEN SINGLEPRSSEL in ADCn_SINGLECTRL renamed to PRSSEL SCANREP in ADCn_SCANCTRL renamed to REP SCANDIFF in ADCn_SCANCTRL renamed to DIFF SCANADJ in ADCn_SCANCTRL renamed to ADJ SCANRES in ADCn_SCANCTRL renamed to RES SCANMASK in ADCn_SCANCTRL renamed to INPUTMASK ...

Page 489: ...VPEN in GPIO_ROUTE to SWOPEN Enumeration of MODE in PCNTn_CTRL changed Enumeration of REF in ADCn_SINGLECTRL ADCn_SCANCTRL changed Split DTOGEN in TIMER0_DTOGEN into single bits Split DTFSEN in TIMER0_DTFC into single bits Split DTFS in TIMER0_DTFAULT into single bits Split DTFSC in TIMER0_DTFAULTC into single bits DTPRSFSEL0 in TIMER0_DTFC renamed to DTPRS0FSEL DTPRSFSEL1 in TIMER0_DTFC renamed t...

Page 490: ...nterrupts removed from Chapter 10 p 86 ACMP wakeup triggering updated in Chapter 10 p 86 Internal reference added to note in Section 11 3 1 2 p 98 Figure 11 4 p 101 and Figure 11 5 p 101 added Section 15 3 7 p 180 updated Note added in Section 18 3 3 p 251 Section 25 3 6 p 378 added and ADCn_BIASPROG register added Section 26 3 3 p 399 added and DACn_BIASPROG register added Section 26 3 8 p 401 up...

Page 491: ...le AUXHFRCO Auxiliary High Frequency RC Oscillator CC Compare Capture CLK Clock CMD Command CMU Clock Management Unit CTRL Control DAC Digital to Analog Converter DBG Debug DMA Direct Memory Access DRD Dual Role Device DTI Dead Time Insertion EBI External Bus Interface EFM Energy Friendly Microcontroller EM Energy Mode EM0 Energy Mode 0 also called active mode EM1 to EM4 Energy Mode 1 to Energy Mo...

Page 492: ...Interrupt Controller OSR Oversampling Ratio OTG On the go PCNT Pulse Counter PHY Physical Layer PRS Peripheral Reflex System PWM Pulse Width Modulation RC Resistance and Capacitance RMU Reset Management Unit RTC Real Time Clock SAR Successive Approximation Register SOF Start of Frame SPI Serial Peripheral Interface SW Software UART Universal Asynchronous Receiver Transmitter USART Universal Synchr...

Page 493: ...o design or fabricate any integrated circuits The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories A Life Support System is any product or system intended to support or sustain life and or health which if it fails can be reasonably expected to result in significant personal injury or death Silicon Laboratories products are genera...

Page 494: ...Rev1 30 494 www silabs com C Contact Information Silicon Laboratories Inc 400 West Cesar Chavez Austin TX 78701 Please visit the Silicon Labs Technical Support web page http www silabs com support pages contacttechnicalsupport aspx and register to submit a technical support request ...

Page 495: ... 26 6 5 Register Map 28 6 6 Register Description 28 7 MSC Memory System Controller 30 7 1 Introduction 30 7 2 Features 30 7 3 Functional Description 31 7 4 Register Map 35 7 5 Register Description 35 8 DMA DMA Controller 41 8 1 Introduction 41 8 2 Features 41 8 3 Block Diagram 42 8 4 Functional Description 43 8 5 Examples 60 8 6 Register Map 62 8 7 Register Description 63 9 RMU Reset Management Un...

Page 496: ...ransmitter 249 18 1 Introduction 249 18 2 Features 249 18 3 Functional Description 250 18 4 Register Map 261 18 5 Register Description 261 19 TIMER Timer Counter 274 19 1 Introduction 274 19 2 Features 274 19 3 Functional Description 275 19 4 Register Map 292 19 5 Register Description 293 20 RTC Real Time Counter 310 20 1 Introduction 310 20 2 Features 310 20 3 Functional Description 310 20 4 Regi...

Page 497: ...General Purpose Input Output 424 28 1 Introduction 424 28 2 Features 424 28 3 Functional Description 425 28 4 Register Map 431 28 5 Register Description 432 29 LCD Liquid Crystal Display Driver 446 29 1 Introduction 446 29 2 Features 446 29 3 Functional Description 447 29 4 Register Map 469 29 5 Register Description 469 30 Revision History 485 30 1 Revision 1 30 485 30 2 Revision 1 20 485 30 3 Rev...

Page 498: ...ltiplexed 16 bit Data 16 bit Address Read Operation 138 14 5 EBI Multiplexed 16 bit Data 16 bit Address Write Operation 138 14 6 EBI Multiplexed 8 bit Data 24 bit Address Read Operation 139 14 7 EBI Multiplexed 8 bit Data 24 bit Address Write Operation 139 14 8 EBI Default Memory Map ALTMAP 0 140 14 9 EBI Alternative Memory Map ALTMAP 1 141 15 1 I 2 C Overview 174 15 2 I 2 C Bus Example 174 15 3 I...

Page 499: ...forms Output 327 21 7 LETIMER Repeated Counting 327 21 8 LETIMER Dual Output 328 21 9 LETIMER Triggered Operation 328 21 10 LETIMER Continuous Operation 329 21 11 LETIMER LETIMERn_CNT Not Initialized to 0 330 22 1 PCNT Overview 342 22 2 PCNT Quadrature Coding 343 22 3 PCNT Direction Change Interrupt DIRCNG Generation 346 23 1 ACMP Overview 355 23 2 20 mV Hysteresis Selected 357 23 3 Capacitive Sen...

Page 500: ...ltiplexing LCD_COM0 455 29 26 LCD 1 3 Bias and Triplex Multiplexing LCD_COM1 455 29 27 LCD 1 3 Bias and Triplex Multiplexing LCD_COM2 455 29 28 LCD 1 3 Bias and Triplex Multiplexing LCD_SEG0 456 29 29 LCD 1 3 Bias and Triplex Multiplexing LCD_SEG0 Connection 456 29 30 LCD 1 3 Bias and Triplex Multiplexing LCD_SEG0 LCD_COM0 456 29 31 LCD 1 3 Bias and Triplex Multiplexing LCD_SEG0 LCD_COM1 457 29 32...

Page 501: ...x Consumers 130 15 1 I 2 C Reserved I 2 C Addresses 176 15 2 I 2 C High and Low Periods for Low CLKDIV 178 15 3 I 2 C Clock Mode 179 15 4 I 2 C Interactions in Prioritized Order 182 15 5 I 2 C Master Transmitter 184 15 6 I 2 C Master Receiver 186 15 7 I 2 C STATE Values 187 15 8 I 2 C Transmission Status 187 15 9 I 2 C Slave Transmitter 190 15 10 I 2 C Slave Receiver 191 15 11 I 2 C Bus Error Resp...

Page 502: ... Contrast Adjustment for Different Bias Settings 461 29 7 LCD VLCD 462 29 8 LCD VBOOST Frequency 462 29 9 LCD Frame rate Conversion Table 463 29 10 LCD Update Data Control UDCTRL Bits 463 29 11 FCPRESC 464 29 12 LCD Animation Shift Register 466 29 13 LCD Animation Pattern 466 29 14 LCD Animation Example 466 A 1 Abbreviations 491 ...

Page 503: ... 19 1 TIMER DTI Example 1 288 19 2 TIMER DTI Example 2 288 21 1 LETIMER Triggered Output Generation 328 21 2 LETIMER Continuous Output Generation 329 21 3 LETIMER PWM Output 330 21 4 LETIMER PWM Output 330 27 1 AES Cipher Block Chaining 415 28 1 GPIO Interrupt Example 430 29 1 LCD Event Frequency Example 464 29 2 LCD Animation Enable Example 467 29 3 LCD Animation Dependence Example 467 ...

Page 504: ...T CLKDIV Equation 251 18 3 LEUART Optimal Sampling Point 255 18 4 LEUART Actual Sampling Point 255 19 1 TIMER Rotational Position Equation 280 19 2 TIMER Up count Frequency Generation Equation 285 19 3 TIMER Up count PWM Resolution Equation 285 19 4 TIMER Up count PWM Frequency Equation 285 19 5 TIMER Up count Duty Cycle Equation 285 19 6 TIMER Up Down count PWM Resolution Equation 286 19 7 TIMER ...

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