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2014-07-02 - Gecko Family - d0001_Rev1.30
220
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Figure 16.9. USART Transmission of Large Frames
Writ e CTRL
Writ e CTRL
Writ e CTRL
TX buffer elem ent 1
TX buffer elem ent 0
Shift regist er
Peripheral Bus
0
1
2
3
4
5
6
7
0
1
2
0
1
2
0
1
2
3
4
5
6
7
As shown in Figure 16.9 (p. 220) , frame transmission control bits are taken from the second element
in FIFO.
The two buffer elements can be written at the same time using the USARTn_TXDOUBLE or
USARTn_TXDOUBLEX register. The TXDATAX0 bitfield then refers to buffer element 0, and
TXDATAX1 refers to buffer element 1.
Figure 16.10. USART Transmission of Large Frames, MSBF
TX buffer elem ent 1
TX buffer elem ent 0
Shift regist er
Peripheral Bus
2
1
0
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
0
1
2
Figure 16.10 (p. 220) illustrates the order of the transmitted bits when an 11 bit frame is transmitted
with MSBF set. If MSBF is set and the frame is smaller than 10 bits, only the contents of transmit buffer
0 will be transmitted.
When receiving a large frame, BYTESWAP in USARTn_CTRL determines the order the way the large
frame is split into the two buffer elements. If BYTESWAP is cleared, the least significant 8 bits of the
received frame are loaded into the first element of the receive buffer, and the remaining bits are loaded
into the second element, as shown in Figure 16.11 (p. 221) . The first byte read from the buffer thus
contains the 8 least significant bits. Set BYTESWAP to reverse the order.
The status bits are loaded into both elements of the receive buffer. The frame is not moved from the
receive shift register before there are two free spaces in the receive buffer.
Summary of Contents for EFM32G
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