IP482 Industrial I/O Pack User’s Manual Counter Timer Module
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Pulse Width Modulation
Pulse width modulated waveforms may be generated at the counter
timer output. The pulse width modulated waveform is generated
continuously. Pulse Width Modulation generation is selected by setting
Counter Control Register bits 2 to 0 to logic “010”.
Counter Constant A value controls the time until the pulse goes active.
The duration of the pulse is set via the Counter Constant B register. Note
that a high pulse will be generated if active high output is selected while a
low pulse will be generated if active low output is selected.
The counter goes through a countdown sequence for each Counter
Constant value. When the 0 count is detected, the output toggles to the
opposite state. Then the second Counter Constant value is loaded into the
counter, and countdown resumes, decrementing by one for each rising edge
of the clock selected via Control Register bits 12, 11, and 10. For example,
a counter constant value of 3 will provide a pulse duration of 3 clock cycles
of the selected clock. Note, when the maximum internal clock frequency is
selected (8MHz or 32MHz), a delay of one extra clock cycle will be added to
the counter constant value.
InA can be used as a Gate-Off signal to stop and start the counter and
thus the pulse-width modulated output. When InA is enabled via bits 5 and
4 of the control register for active low Gate-Off input, a logic low input will
enable pulse-width modulation counting while a logic high will stop PWM
counting. When InA is enabled for active high Gate-Off operation, a logic
high will enable PWM counting while a logic low will stop PWM counting.
InB can be used to input an external clock for use in PWM. Bits 7 and 6
must be set to either logic “01” or “10”. Additionally, the clock source bits
12, 11, and 10 must be set to logic “101” to enable external clock input.
PWM can alternatively be internally clocked using control register bits 12,
11, and 10. Available frequencies vary depending on the carrier operational
frequency.
InC can be used to externally trigger Pulse Width Modulation generation.
Additionally PWM can be triggered internally via the Counter Trigger
Register at the base a offset 04H. An initial trigger, software or
external, causes the pulse width modulated signal to be generated. After an
initial trigger do not issue additional triggers. Triggers issued while running
will cause the Constant A and B values to load at the wrong time. In
addition, changing the Control register setting while running can also cause
the Constant A and B values to load at the wrong time.
COUNTER CONTROL
REGISTER
