IP482 Industrial I/O Pack User’s Manual Counter Timer Module
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Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com
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Input Pulse Width Measurement
Setting bits 2 to 0 of the Counter Control Register to logic “101”
configures the counter for pulse-width measurement. After pulse-width
measurement is triggered, the first input pulse is measured.
InA is used to input the pulse to be measured. An active low or high
pulse can be measured.
InB can be used to input an external clock for Pulse-Width Measurement.
Bits 7 and 6 must be set to either logic “01” or “10”. Additionally, the clock
source bits 12, 11, and 10 must be set to logic “101” to enable external clock
input. Pulse Width Measurement can alternatively be internally clocked
using control register bits 12, 11, and 10. Available frequencies vary
depending on carrier operational frequency.
InC can be used to externally trigger Pulse Width Measurement.
Additionally, Pulse Width Measurement can be triggered internally via the
Counter Trigger Register at the base a offset 04H. An initial trigger,
software or external, starts pulse width measurement at the beginning of the
next active pulse.
For pulse-width measurement, the pulse-width being measured serves
as an enable control for an up-counter whose value can be read from the
Counter Read Back Register. When triggered, the counter is reset and then
increments by one for each clock pulse while the input signal level remains
in the active state (high or low according to the programmed polarity of input
InA). The resultant pulse-width is equivalent to the count value read from
the Counter Read Back Register, multiplied by the clock period. An output
pulse will be generated at the counter output pin to signal the completion of
a given measurement. Note that the measured pulse may be in error by
1
clock cycle.
Reading a counter value of 0xFFFF hex indicates that the pulse duration
is longer than the current counter size and clock frequency can measure.
Upon reading of this overflow value you must select a slower frequency and
re-measure.
An interrupt can be generated upon completion of a given pulse width
measurement (the pulse has returned to the opposite polarity), if enabled via
the interrupt enable bit of the Counter Control Register (bit 15). The
interrupt will remain pending until released by setting the required bit of the
Interrupt Status/Clear
register at the base a offset 02H. A pending
interrupt can also be cleared, by setting the Counter Control register bit-15
to logic low.
COUNTER CONTROL
REGISTER
