IP482 Industrial I/O Pack User’s Manual Counter Timer Module
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Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com
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Frequency Measurement Operation
Frequency Measurement is selected by setting Counter Control Register
bits 2 to 0 to logic “100” and setting bits 12 to 10 to logic “111”. The counter
counts how many InB edges (low to high or high to low) are received during
the InA enable interval. The frequency is the number of counts divided by
the duration of the InA enable signal.
InA is used as an enable signal to start frequency measurement. The
InA signal must be a pulse of known width. When InA is configured (via bits
5 and 4 of the control register) as an active low enable input, a logic low
input will enable frequency measurement while a logic high will stop
frequency measurement. When InA is configured as an active high enable
signal, a logic high will enable frequency measurement while a logic low will
stop frequency measurement.
InB is used to input the signal whose frequency is to be measured. Input
pulses occurring at input InB of the counter are counted while the enable
signal present on InA is active. When the InA signal goes inactive, the
counter output will generate a 1.75
s output pulse and an optional interrupt.
InC can be used as an external trigger input. When control register bits
9 and 8 are set to logic “01” or “10”, the InC input functions as an external
trigger input. Frequency measurement may also be internally triggered (via
the Trigger Control Register at the base a offset 04H). An initial
trigger, software or external, starts frequency measurement upon the active
edge of the InA enable signal.
The Counter Constant A Register is not used for frequency
measurement. Do not write to this register while the counter is actively
counting since this will cause the counter to be loaded with the Constant A
value.
Reading the Counter Read Back Register will return the current count
(variable). A minimum event pulse width (InB) is required for correct pulse
detection with input debounce disabled. A carrier operating at 8MHz
requires an 125ns event pulse, while a carrier operating at 32MHz requires
an 31.25ns event pulse. With debounce enabled, a minimum event pulse
width of 2.5
s is required for correct pulse detection. Programmable clock
selection is not available for frequency measurement.
If the Interrupt Enable bit-15 of the Counter Control Register is set, an
interrupt is generated when the input InA enable pulse goes inactive. An
interrupt will remain pending until released by setting the required bit of the
Interrupt Status/Clear
register at the base a offset 02H. A pending
interrupt can also be cleared, by setting the Counter Control register bit-15
to logic low.
COUNTER CONTROL
REGISTER
