Hercules-EBX CPU User Manual V1.02
Page 102
15. PULSE-WIDTH MODULATION OPERATION
Hercules-EBX models that include Data Acquisition contain four PWM generators for automatic
generation of a regular pulse with independently-configurable duty cycle and frequency. These
output signals are present on DIO Header J8 pins 33-36 (PWM output channel 0-3) when
DIOCTR0 = 1.
Each PWM consists of two 24-bit down counters, CT0 and CT1. CT0 controls the frequency, and
CT1 controls the duty cycle, or length of the active pulse. Each counter is initially loaded with the
desired data, and desired clock frequencies are selected for each counter. CLK1 and CLK0 select
10MHz (0) or 100 KHz (1) for the clock source for their respective counters.
Each counter contains a 24-bit load register. The load registers are accessed by writing to Page 1
base + 24 to base + 26 followed by a load command (base + 27 bit 7 = 0 indicates a PWM
command) and may be written to at any time. When ENAB = 0, each counter is loaded from the
load register via the load command. When ENAB = 1, each counter is loaded from its load
register on the next clock after CT0 = 0.
When ENAB=1, both counters count down at the same time. While CT1 is running, the PWM
output is equal to the polarity selected by POL: 1 = the output is high during the active period
when CT1 is counting down, and 0 = the output is low during the active period. This causes the
output pulse to occur at the start of the cycle.
After CT1 reaches 0, it stops counting, and the output switches to the opposite inactive polarity on
the next clock. CT0 runs continuously. When it is 0, on the next clock, both counters will reload
from their load registers, and the cycle will repeat.
CT0 and CT1 may be reloaded while the PWM is running. The reload data is held in a separate
load register for each counter and is not loaded into the counter until CT0 = 0. This allows the
current cycle to complete without distortion. Note that this implies that a long PWM cycle duration
for the current cycle may cause a considerable update delay before the new settings are seen on
the PWM outputs: if the current PWM cycle period is several seconds in duration and the PWM
data is updated near the beginning of a cycle, then the output will not be updated with the new
settings until several seconds later.
ENAB controls the operation of the PWM. ENAB = 1 causes the PWM to run, and ENAB = 0
disables the PWM circuit. In the disabled state the PWM retains its current state but does not
count input clocks, and the output is set to the inactive state as determined by POL.
OUTEN controls the output signal. If OUTEN = 1 then the output is active, and if OUTEN = 0, the
output is equal to the inactive state determined by POL. When POL = 0, the inactive state is 0,
and when POL = 1 the inactive state is 1. The truth table is as follows:
CT1
output
POL OUTEN
Output
pin
Comments
0
0
0
1
Active low, active, disabled
0
0
1
0
Active low, active, enabled
0
1
0
0
Active high, inactive, disabled
0
1
1
0
Active high, inactive, enabled
1
0
0
1
Active low, inactive, disabled
1
0
1
1
Active low, inactive, enabled
1
1
0
0
Active high, active, disabled
1
1
1
1
Active high, active, enabled
Table 42: PWM Control Signal Truth Table
