Hercules-EBX CPU User Manual V1.02
Page 65
Base + 5
Write
D/A Channel Register
Bit
No.
7 6 5 4 3 2 1 0
Name
SU
DACH1
DACH0
SU Simultaneous
Update
0 = Transparent (written directly to the DAC’s) / Simultaneous Write
1 = Latch and hold data (DAC output not updated until “0” is written later)
DACH1-0 D/A channel number
Writing to this register updates the selected D/A channel with the data currently stored in Base +
6 and Base + 7. The high-order bit determines whether the data is transferred directly out to the
DAC’s (transparent mode) or is latched and held for a later simultaneous update.
Base + 6
Write
D/A LSB Register
Bit
No.
7 6 5 4 3 2 1 0
Name
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
DA7-0
D/A LSB data
Base + 7
Write
D/A MSB Register
Bit
No.
7 6 5 4 3 2 1 0
Name
DA15 DA14 DA12 DA12 DA11 DA10 DA9 DA8
DA15-8
D/A MSB data
Base + 8
Read/Write
FIFO Threshold Register LSB
Bit
No.
7 6 5 4 3 2 1 0
Name
FT7 FT6 FT5 FT4 FT3 FT2 FT1 FT0
FT7-0
FIFO threshold value LSB
Base + 9
Read/Write
FIFO Threshold Register MSB
Bit
No.
7 6 5 4 3 2 1 0
Name
FT10
FT9
FT8
FT11-8
FIFO threshold value MSB
When the FIFO depth is greater than or equal to the FIFO threshold, TF (threshold flag) = 1 and
an A/D interrupt request will be generated if FIFOEN = 1 and ADINTE = 1.
The FIFO size is 2048 samples. The threshold value may be anywhere from 1 to 2047 samples.
In most cases the threshold does not need to be larger than 1/2 the FIFO size, or 1024 samples.
On power-up or system reset, the FIFO threshold is reset to 1024 samples.
