Hercules-EBX CPU User Manual V1.02
Page 91
be configured and then updated simultaneously. This allows for a uniform transition time for all
A/D outputs.
To send the data to the D/A immediately, write the channel number to Page 0: Base+5 bits 1-0.
For Transparent mode, bit 8 should be set to “0”:
outp(Base + 5, Channel Number);
Where “Channel Number” is 0-3
To latch the data in preparation for more updates (not sending the data to the D/A until channel
data updates are completed), write the channel number to Page 0: Base+5 bits 1-0, with bit 8
should be set to “1”. :
outp(Base + 5, 0x80 + Channel Number);
Where “Channel Number” is 0-3
The D/A data will be held until a “0” is written to the Simultaneous Update bit, at which time all of
the latched data will be updated at the same time. So, if data has previously been latched with
the simultaneous update bit set to “1” and the data for the last channel involved in the
simultaneous update has just been written to Base + 6 and Base + 7, then the final channel
selection (which would send all of the latched data to the D/A) would look just like a “Transparent
Mode” write, i.e.:
outp(Base + 5, Channel Number);
Where “Channel Number” is 0-3
At this point, all of the latched data would be enabled through the D/A and the analog outputs
would begin the transition to the selected values at the same time.
13.4.5 WAIT FOR THE D/A TO UPDATE
Writing the channel number to Base + 5, regardless of the state of the “SU” bit, starts the D/A
update process for the selected channel(s). The update process requires approximately 30
microseconds to transmit the data to the D/A chip (and then update the D/A circuit in the chip, if
the data is to be passed through immediately). During this period, no attempt should be made to
write to any other channel in the D/A through addresses Base + 6 or Base + 7.
The status bit DABUSY (Page 0 : Base + 4 bit 5) indicates whether the D/A is busy updating (1)
or idle (0). After writing to the D/A, monitor this bit until it is zero before proceeding to the next D/A
operation.
Note that the time required to transfer data for a channel occurs whether the “Simultaneous
Update” bit is set or not: the data is transferred (and the DABUSY signal is active) regardless of
whether the data is to be immediately updated or is being latched in preparation for later
simultaneous update. The only difference in the two modes occurs after the Digital data is
transferred: in “Transparent mode” the data will immediately pass through the D/A whereas
“Simultaneous Update” mode will conclude with the D/A output data unchanged.
