Theory
of
Operation—
DM 5010
The
In Progress bit, when set high, informs the micro
processor
that
an A/D conversion is in process. The proces
sor, when controlling the conversion process, monitors this
data
bit
and, when it returns low, knows that the A/D con
version
is
complete and that the serial data may be read
onto
the
bus
via the
Data line.
The power module’
s external GPIB interface has 16 con
nections
that are used for three separate types of functions.
Each of these
signal lines is connected
directly to the
DM
5010
and function as
described by the IEEE 488-1978
Standard.
One additional signal
line TE (talk enable), is pro
vided
for
future use.
The 17-bit serial data representing an A/D
conversion is
buffered
one bit
at a time onto bit 7 of the buffered data bus.
The microprocessor, by executing a sequence of read, shift,
and
store commands,
re-assembles this serial data into the
parallel format it uses
most efficiently.
SWITCHES <9>
The primary function of the ESW (Enable Switches) sig
nal is to enable the microprocessor to read the settings of
the eight user-definable switches defining
the
GPIB and SA
(Signature
Analysis)
configuration of the DM 5010.
Though
also
used to reset the EXTRIG status bit as pre
viously
described,
a low ESW from
the Address Decode cir
cuitry turns
on buffer U1610. This buffers eight bits onto the
data
bus
corresponding to the switch closures of S1515, as
defined
by the user.
Switches S1515-2 through 8 define
GPIB
address and
mode data and will
be further discussed
in the GPIB description that follows. Switch S1515-1, when
closed,
causes
the
microprocessor to stop normal DMM op
eration
and
execute
a special SA stimulation routine.
GPIB
<9>
The GPIB provides a communication and control link so
that
multiple
instruments
may interface with
each other
un
der
the
direction of a system controller. The TM 5000-Series
power module provides the external GPIB connector as well
as
the internal interconnection to tie
a
GPIB-compatible
plug-in to the GPIB. All GPIB interface and control functions
of
the
DM 5010
and the TM 5000-Series power modules
adhere to
IEEE Standard 488-1978.
The
IEEE 488-1978 Standard
The
IEEE 488-1978 Standard defines a byte-serial, bit
parallel
interface
system
electrically,
functionally, and
me
chanically as well
as
specifying terminology and system
limitations.
This system implements a three-wire handshake
system
with each data
transfer from a ‘talker’’ to one or
more
“listeners". A ‘talker" is a GPIB device sending data
while a
"listener" is one that receives data from a “talker”.
All
GPIB information is transferred at standard TTL levels
using
negative
logic
(i.e.,
0 = true).
Inputs DI01
through DI08
(data input/output) are used
specifically
for
transfer of data between GPIB devices.
Five other lines are used to manage the flow of informa
tion
over
the
interface
lines. The ATN (Attention) line, when
active, disables the current talker
and listeners and makes
all devices
listen to the controller. IFC
(Interface Clear) line is
used
to put the interface system into a known quiescent
state.
The SRQ (Service Request)
line is
used to indicate to
the
controller that a device on the bus is in need of service
and
an interrupt is requested (the controller determines
which devices may talk or listen at any time). The REN (Re
mote
Enable) command selects either a remote or local
source
of device programming. The EOI (End Or Identify)
line
is
used to signal the end of a
multiple byte transfer.
The three
remaining
lines are associated with the hand
shake
process
and are
the DAV (Data Valid), NRFD (Not
Ready
For
Data)
and NDAC (Data Not
Accepted) lines. Their
timing
relationships
during the handshake process are
shown
in Fig.
4-14,
Each data
byte transferred by the inter
face system uses the handshake process to exchange data
between source (typically
a talker) and acceptor (typically a
listener). The following list of events is
related by
number to
the state
changes shown in Fig. 4-14
and the flowchart
shown
in
Fig. 4-15.
The
Handshake Process
1. The source (talker) initializes the active low DAV (Data
Valid)
to
a high level, indicating that data is not valid.
2. The
acceptors
(listeners) initialize the active low
NRFD
(Not Ready For Data) level to
a
low (none are ready
for data) and
set the active low NDAC (Data Not Accepted)
level to low
(none have accepted data).
3. The source checks for an error condition (both NRFD
and
NDAC
at
a high level) and then
sets a data byte on the
DIO (Data
In/Out)
lines.
After the data has been placed on
the
DIO lines, the source delays to allow the data to settie
on these lines.
4. When the
acceptors have all indicated readiness to
accept
the first data
byte, the NRFD level goes high.
ADD
JAN
1982
4-25
Summary of Contents for DM 5010
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