Synchronous DRAM Controller Module
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
7-5
7.3.1.2
DRAM Address and Control (DACR0) (Synchronous Mode)
The DRAM address and control register (DACR0), shown in
, contain the base address compare
value and the control bits for the memory block of the DRAM controller. Address and timing are also
controlled by bits in DACR0.
describes DACR0 fields.
11
IS
Initiate self-refresh command.
0
Take no action or issue a
SELFX
command to exit self refresh.
1
If DCR[COC] = 0, the DRAM controller sends a
SELF
command to the SDRAMv to put it in low-power, self-refresh
state where they remain until IS is cleared, at which point the controller sends a
SELFX
command for the SDRAM to
exit self-refresh. The refresh counter is suspended while the SDRAM is in self-refresh; the SDRAM controls the
refresh period.
10–9
RTIM
Refresh timing. Determines the timing operation of auto-refresh in the DRAM controller. Specifically, it determines the
number of clocks inserted between a
REF
command and the next possible
ACTV
command. This corresponds to t
RC
in the SDRAM specification.
00 3 clocks
01 6 clocks
1x 9 clocks
8–0
RC
Refresh count. Controls refresh frequency. The number of bus clocks between refresh cycles is (RC + 1) * 16. Refresh
can range from 16–8192 bus clocks to accommodate both standard and low-power DRAMs with bus clock operation
from less than 2 MHz to greater than 50 MHz.
The following example calculates RC for an auto-refresh period for 4096 rows to receive 64 mS of refresh every
15.625 µs for each row (625 bus clocks at 40 MHz).
# of bus clocks = 625 = (RC field + 1) * 16
RC = (625 bus clocks/16) -1 = 38.06, which rounds to 38; therefore, RC = 0x26.
Address MBAR+0x108 (DACR0)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15
14
13
12
11 10 9 8 7
6
5 4
3
2
1 0
R
BA
RE
CASL
CBM
IMRS PS IP PM
W
Reset –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
–
–
–
–
– – – –
0
– – –
–
– –
Figure 7-4. DRAM Address and Control Register (DACR0) (Synchronous Mode)
Table 7-5. DRAM Address and Control Register (DACR0) Field Descriptions (Synchronous Mode)
Field
Description
31–18
BA
Base address register. With DMR[BAM], determines the address range in which the associated DRAM block is
located. Each BA bit is compared with the corresponding address of the current bus cycle. If all unmasked bits match,
the address hits in the associated DRAM block.
17–16
Reserved, should be cleared.
Table 7-4. DRAM Control Register (DCR) Field Descriptions (Synchronous Mode) (continued)
Field
Description
Summary of Contents for MCF5253
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Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
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Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
