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NXP Semiconductors MCF5253, Reference Manual

The NXP Semiconductors MCF5253 is a powerful embedded microprocessor designed for a range of applications. Ensure proper utilization with the comprehensive Reference Manual available for free download on our website. Get the most out of your device by accessing the essential manual to guide you through its features and capabilities.

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IDE and Flash Media Interface

MCF5253 Reference Manual, Rev. 1

13-12

Freescale Semiconductor

 

2.

SecureDigital

 mode. In this mode it is possible to connect one SD card. The SD card has a 

command

 line and 1 or 4 

serial data

 lines. The interface shift register 1 will handle communication 

on the 

serial data

 lines, the interface shift register 2 will handle communication on the 

command

 

line. From a software point of view, the two interfaces operate independently.

13.5

Flash Media Interface Memory Map and Register Definitions

The Flash Media interface contains eight 32-bit registers.

.  

13.5.1

Flash Media Clock Generation and Configuration

Clock generation and selection of the card type is accomplished by programming the 

FLASHMEDIACONFIG

 register as shown in 

Figure 13-9

.

Table 13-8. Flash Media Registers

Address

Access

Size

Bits

Name

Description

MBAR2+ 0x460

RW

32

FLASHMEDIACONFIG

Clock and general configuration

MBAR2+ 0x464

RW

32

FLASHMEDIACMD1

Command register for interface 1

MBAR2+ 0x468

RW

32

FLASHMEDIACMD2

Command register for interface 2

MBAR2+ 0x46C

RW

32

FLASHMEDIADATA1

Data register for interface 1

MBAR2+ 0x470

RW

32

FLASHMEDIADATA2

Data register for interface 2

MBAR2+ 0x474

RW

32

FLASHMEDIASTATUS

Status register

MBAR2+ 0x478

RW

32

FLASHMEDIAINTEN

Interrupt enable register

MBAR2+ 0x47C

R

32

FLASHMEDIAINTSTAT

Interrupt status register

MBAR2+ 0x47C

W

32

FLASHMEDIAINTCLEAR

Interrupt clear register

Address MBAR2 + 0x460

Access: User read/write

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

R

CARDTYPE RECEIVEEDGE

STOPCLOCK

W

Reset

–

–

–

–

–

–

–

–

–

–

0

0

0

0

–

–

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R

CLOCKCOUNT1

CLOCKCOUNT0

W

Reset

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

Figure 13-9. Flash Media Configuration Register (FLASHMEDIACONFIG)

Summary of Contents for MCF5253

Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...

Page 2: ...ducts for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability...

Page 3: ...Controller Area Network CAN 2 0B Communication Unit 1 9 1 5 12 Real Time Clock 1 9 1 5 13 Serial Audio Interfaces 1 9 1 5 14 IEC958 Digital Audio Interfaces 1 9 1 5 15 Audio Bus 1 9 1 5 16 CD ROM Enco...

Page 4: ...tal Memory Stick Card Interface 2 10 2 16 Queued Serial Peripheral Interface QSPI 2 11 2 17 ATA Interface 2 11 2 18 Two Controller Area Network CAN Communication Modules 2 11 2 19 USB Controller 2 12...

Page 5: ...3 5 3 Illegal Instruction Exception 3 10 3 5 4 Divide By Zero 3 10 3 5 5 Privilege Violation 3 10 3 5 6 Trace Exception 3 10 3 5 7 Debug Interrupt 3 11 3 5 8 RTE and Format Error Exceptions 3 11 3 5...

Page 6: ...5 5 Instruction Cache Memory Map and Register Definitions 5 5 5 5 1 Instruction Cache Registers Memory Map 5 5 5 5 2 Instruction Cache Register 5 6 5 5 2 1 Cache Control Register 5 6 5 5 2 2 Access Co...

Page 7: ...Initialization 7 19 7 6 4 DMR Initialization 7 20 7 6 5 Mode Register Initialization 7 21 7 6 6 Initialization Code 7 22 Chapter 8 Bus Operation 8 1 Bus Features 8 1 8 2 Bus and Control Signals 8 1 8...

Page 8: ...3 Software Interrupts 9 16 9 4 4 Interrupt Monitor 9 16 9 5 System Protection and Reset Status Registers 9 17 9 5 1 Reset Status Register 9 17 9 5 2 Software Watchdog Timer 9 17 9 5 2 1 System Protect...

Page 9: ...1 11 2 Timer Features 11 1 11 3 Block Diagram 11 1 11 4 Timer Signal Output 11 2 11 5 Timer Operation 11 2 11 5 1 Selecting the Prescaler 11 2 11 5 2 Configuring the Timer for Reference Compare 11 2 1...

Page 10: ...ash Media Command Register 2 in Secure Digital Mode 13 16 13 5 3 Flash Media Data Registers 13 17 13 5 3 1 Flash Media Status Register 13 18 13 5 4 Flash Media Interrupt Register 13 18 13 5 5 Flash Me...

Page 11: ...Request Operation 14 16 14 7 2 2 Auto Alignment 14 16 14 7 2 3 Bandwidth Control 14 16 14 7 3 Channel Termination 14 17 14 7 3 1 Error Conditions 14 17 14 7 3 2 Interrupts 14 17 Chapter 15 UART Module...

Page 12: ...2 Transmitter Commands 15 21 15 4 5 2 1 No Action Taken 15 21 15 4 5 2 2 Transmitter Enable 15 22 15 4 5 2 3 Transmitter Disable 15 22 15 4 5 2 4 Do Not Use 15 22 15 4 5 3 Receiver Commands 15 22 15 4...

Page 13: ...Address Register QAR 16 12 16 4 6 QSPI Data Register QDR 16 12 16 4 7 Command RAM Registers QCR0 QCR15 16 13 16 4 8 Programming Example 16 14 Chapter 17 Audio Interface Module AIM 17 1 Audio Interface...

Page 14: ...ata Into IEC958 Transmit Data 17 26 17 7 Processor Interface Overview 17 26 17 7 1 Data Exchange Register Descriptions 17 27 17 7 2 Data Exchange Register Overview 17 28 17 7 2 1 Data In Selection 17...

Page 15: ...Registers MBDR 18 12 18 6 I2 C Programming Examples 18 12 18 6 1 Initialization Sequence 18 12 18 6 2 Generation of START 18 13 18 6 3 Post Transfer Software Response 18 14 18 6 4 Generation of STOP 1...

Page 16: ...en Branch PST 5 20 5 20 2 1 6 Begin Execution of RTE Instruction PST 7 20 6 20 2 1 7 Begin Data Transfer PST 8 B 20 6 20 2 1 8 Exception Processing PST C 20 6 20 2 1 9 Emulator Mode Exception Processi...

Page 17: ...6 Configuration Status Register CSR 20 36 20 5 7 BDM Address Attribute Register BAAR 20 39 20 5 8 Concurrent BDM and Processor Operation 20 39 20 5 9 Freescale Recommended BDM Pinout 20 40 Chapter 21...

Page 18: ...Advanced Technology Attachment Controller ATA 23 1 Features 23 1 23 2 Block Diagram 23 1 23 3 Overview 23 2 23 3 1 Modes of Operation 23 3 23 4 External Signal Description 23 4 23 4 1 Detailed Signal...

Page 19: ...19 TIME_DVH Register 23 24 23 5 2 2 20 TIME_DZFS Register 23 25 23 5 2 2 21 TIME_DVS Register 23 25 23 5 2 2 22 Time_CVH Register 23 25 23 5 2 2 23 TIME_SS Register 23 25 23 5 2 2 24 TIME_CYC Registe...

Page 20: ...24 6 2 6 Device Controller Capability Parameters DCCPARAMS Non EHCI 24 14 24 6 3 Operational Registers 24 15 24 6 3 1 USB Command Register USBCMD 24 15 24 6 3 2 USB Status Register USBSTS 24 18 24 6 3...

Page 21: ...Pointer List Plus 24 55 24 8 4 5 siTD Back Link Pointer 24 56 24 8 5 Queue Element Transfer Descriptor qTD 24 56 24 8 5 1 Next qTD Pointer 24 57 24 8 5 2 Alternate Next qTD Pointer 24 57 24 8 5 3 qTD...

Page 22: ...on Progress for Interrupt Transfers 24 97 24 9 12 2 5 Split Transaction Execution State Machine for Interrupt 24 97 24 9 12 2 6 Periodic Interrupt Do Start Split 24 98 24 9 12 2 7 Periodic Interrupt D...

Page 23: ...evice Operational Model For Packet Transfers 24 134 24 11 3 3 1 Priming Transmit Endpoints 24 134 24 11 3 3 2 Priming Receive Endpoints 24 135 24 11 3 4 Interrupt Bulk Endpoint Operational Model 24 13...

Page 24: ...Transaction Translators 24 152 24 12 2 Device Operation 24 152 24 12 3 Non Zero Fields the Register File 24 152 24 12 4 SOF Interrupt 24 152 24 12 5 Embedded Design 24 153 24 12 5 1 Frame Adjust Regis...

Page 25: ...4 Matching Process 25 24 25 6 5 Message Buffer Handling 25 24 25 6 5 1 Serial Message Buffers SMBs 25 24 25 6 5 2 Message Buffer Deactivation 25 24 25 6 5 3 Locking and Releasing Message Buffers 25 25...

Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...

Page 27: ...cribes the MCF5253 input and output signals organized into functional groups Chapter 3 ColdFire Core This chapter provides an overview of the MCF5253 microprocessor core The chapter describes the CFV2...

Page 28: ...bes the operation of the bus interface to IDE and Flash Media the interface setup timing and operation are provided as well as commonly used commands Chapter 14 DMA Controller This chapter provides th...

Page 29: ...he host mode of operation Chapter 25 FlexCAN Module This chapter discusses the modes of operation signals memory map register definitions and the functional and initialization sequence of the FlexCAN...

Page 30: ...ate like asynchronous DRAMs but with a synchronous clock a pipelined multiple bank architecture and faster speed SDRAM bank An internal partition in an SDRAM device For example a 64 MBIT SDRAM compone...

Page 31: ...or write row indicates that it can be read or written Register Field Types r Read only Writing this bit has no effect w Write only rw Standard read write bit Only software can change the bit s value o...

Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...

Page 33: ...V core power supply and on chip 128 Kbyte SRAM For additional information regarding software drivers and applications refer to the MCF5253 website http www freescale com coldfire 1 2 MCF5253 Feature...

Page 34: ...programmable interrupt priority DMA controller with 4 DMA channels On chip real time clock works with 32 768 kHz X tal Real time clock has tamper detection functionality Operates from crystal oscilla...

Page 35: ...ckdoor Interface Translator 16 Kbyte SRAM SPI Interface Audio Interfaces AD Logic ARB DMA Memory Stick SD Interface USB 2 0 OTG Controller ATA Controller Timer 5x08 Interrupt E bus SDRAM Interface E b...

Page 36: ...ddress pointers that can increment or remain constant 16 24 bit transfer counter Operand packing and unpacking support Auto alignment transfers supported for efficient block movement Supports bursting...

Page 37: ...ation of the Bosch CAN protocol specification 2 0B which supports both standard and extended message frames Real time Clock Works with 32 768 kHz X tal Anti tamper feature detects if clock was stopped...

Page 38: ...ster and slave modes support for multiple masters Automatic interrupt generation with programmable level System debug support Real time instruction trace for determining dynamic execution path Backgro...

Page 39: ...ller The MCF5253 provides four fully programmable DMA channels for quick data transfer Single and dual address mode is supported with the ability to program bursting and cycle stealing Data transfer i...

Page 40: ...mode non page mode and burst page mode and supports SDRAMs 1 5 7 System Interface The MCF5253 provides a glueless interface to 16 bit port size SRAM ROM and peripheral devices with independent program...

Page 41: ...ock 1 word clock 1 data in 1 data out the other two interfaces are 3 pin 1 bit clock 1 word clock 1 data in or 1 data out The serial interfaces have no limit on minimum sampling frequency Maximum samp...

Page 42: ...nctions in hardware Sector sync recognition Scrambling of sectors Insertion of the CRC checksum for Mode 1 Mode 2 Form 1 and Mode 2 Form 2 sectors Third layer error encoding needs to be done in softwa...

Page 43: ...e analog comparator and digital sections are integrated in the MCF5253 An external integrator circuit resistor capacitor is required which is driven by the ADC output A interrupt is provided when the...

Page 44: ...erred to as Joint Test Action Group or JTAG For more information refer to the IEEE 1149 1A standard Freescale provides BSDL files for JTAG testing 1 5 28 System Debug Interface The ColdFire processor...

Page 45: ...nts are maintained Sleep mode is exited by taking the external Wake up pin low Sleep mode is selected by software control of a bit in the PLL register When Sleep mode is exited code execution resumes...

Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...

Page 47: ...strobe SDRAS GPIO59 Row address strobe for external SDRAM Out Negated Synchronous column address strobe SDCAS GPIO39 Column address strobe for external SDRAM Out Negated SDRAM write enable SDWE GPIO38...

Page 48: ...IM TXD2 GPIO0 Transmit serial data output for UART Out Request To Send DDATA3 RTS0 GPIO4 DDATA1 RTS1 SDATA2_BS2 GPIO2 Signals sent from UART0 1 that it is ready to receive data Out Clear To Send DDATA...

Page 49: ...BUIN2 SCLKOUT GPIO13 Clock out for both MemoryStick interfaces and for Secure Digital In Out DDATA0 CTS1 SDATA0_SDIO1 GPIO1 SecureDigital serial data bit 0 MemoryStick interface 1 data I O In Out SCL0...

Page 50: ...In AD OUT ADREF ADOUT SCLK4 GPIO58 Analog to Digital Converter output signal connects to ADREF via integrator network In Out QSPI clock QSPICLK SUBR GPIO25 QSPI clock signal In Out QSPI data in RCK QS...

Page 51: ...g Data DDATA0 CTS1 SDATA0_SDIO1 GPIO1 DDATA1 RTS1 SDATA2_BS2 GPIO2 DDATA2 CTS0 GPIO3 DDATA3 RTS0 GPIO4 Display of captured processor data and break point statuses In Out Hi_Z Processor Status PST0 GPI...

Page 52: ...and size 2 3 5 Transfer Acknowledge The TA GPIO12 pin is the transfer acknowledge signal 2 4 SDRAM Controller Signals The following SDRAM signals provide a glueless interface to external SDRAM An SDRA...

Page 53: ...n insert wait states by pulling IDE_IORDY GPIO33 CS2 is associated with the IDE_DIOR and IDE_DIOW 2 7 Bus Buffer Signals As the MCF5253 has a quite complicated slave bus with the possibility of having...

Page 54: ...Description Receive Data The RXD0 GPIO46 SDA1 RXD1 GPIO44 and EF RXD2 GPIO6 are the inputs on which serial data is received by the UART Data is sampled on RxD 2 0 on the rising edge of the serial cloc...

Page 55: ...I Os or serial audio inputs As serial audio inputs the data is sent to interfaces 1and 3 respectively During reset the pins are configured as serial data inputs Serial audio data out SDATAO1 TOUT0 GPI...

Page 56: ...n by the divider network in stand by mode can be excessive Therefore it is possible to generate a VDD 2 voltage by selecting SCLK4 output mode and feeding this clock signal which is 50 duty cycle thro...

Page 57: ...Pin descriptions are given in Table 2 1 DDATAO CTS1 SDATA0_SDIO1 GPIO1 Secure Digital serial data bit 0 MemoryStick interface 1 data I O SCL0 SDATA1_BS1 GPIO41 Secure Digital serial data bit 1 MemoryS...

Page 58: ...the incoming digital audio signal 2 22 Clock Out The MCLK1 GPIO11 and QSPI_CS2 MCLK2 GPIO24 can serve as DAC clock outputs When programmed as DAC clock outputs these signals are directly derived from...

Page 59: ...Debug Data The debug data pins DDATA0 CTS1 SDATA0_SDIO1 GPIO1 DDATA1 RTS1 SDATA2_BS2 GPIO2 DDATA2 CTS0 GPIO3 and DDATA3 RTS0 GPIO4 are four bits wide This nibble wide bus displays captured processor d...

Page 60: ...crystal oscillator The crystal must be connected between CRIN and CROUT An externally generated clock signal can also be used and should be connected directly to the CRIN pin 2 26 Wake Up Signal To ex...

Page 61: ...core Three pins are associated with this function LININ LINOUT and LINGND Typically LININ would be fed by the I O PAD supply 3 3 V with separate filtering recommended to provide some isolation between...

Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...

Page 63: ...ocessor Pipelines Figure 3 1 shows a block diagram of the processor pipelines of a CF2 ColdFire core Figure 3 1 CF2 ColdFire Processor Core Pipelines The processor core is comprised of two separate pi...

Page 64: ...user mode or supervisor mode of the processor as defined by the S bit of the status register 3 2 1 User Memory Map and Register Description Figure 3 2 shows the user Memory Map The model is the same a...

Page 65: ...ring instruction execution and exception processing the processor automatically increments the contents of the PC or places a new value in the PC as appropriate For some addressing modes the PC can be...

Page 66: ...e 3 3 eMAC Instruction Summary Command Mnemonic Description Multiply Signed MULS ea y Dx Multiplies two signed operands yielding a signed result Multiply Unsigned MULU ea y Dx Multiplies two unsigned...

Page 67: ...d other control bits In the supervisor mode software can access the entire SR In user mode only the lower 8 bits are accessible CCR The control bits indicate the following states for the processor tra...

Page 68: ...time from the detection of the fault condition to the fetch of the first handler instruction has been initiated 1 The processor makes an internal copy of the SR and then enters supervisor mode by set...

Page 69: ...aligned on a 1 megabyte boundary This instruction address is generated by fetching an exception vector from the table located at the address defined in the vector base register The index into the exce...

Page 70: ...upt 13 034 Reserved 14 038 Fault Format error 15 03C Next Uninitialized interrupt 16 23 040 05C Reserved 24 060 Next Spurious interrupt 25 31 064 07C Next Level 1 7 autovectored interrupts 32 47 080 0...

Page 71: ...type of exception the programming model has not been altered by the instruction generating the access error If the access error occurs on an operand read the processor immediately aborts the current...

Page 72: ...A or line F opcode generates unique exception types vectors 10 and 11 respectively ColdFire processors do not provide illegal instruction detection on extension words of any instruction including MOV...

Page 73: ...format is not equal to 4 5 6 7 generates a format error The exception stack frame for the format error is created without disturbing the original RTE frame and the stacked PC pointing to the RTE inst...

Page 74: ...set is negated the core performs two longword read bus cycles The first longword at address 0 is loaded into the stack pointer and the second longword at address 4 is loaded into the program counter A...

Page 75: ...are aligned on the same byte boundary as the operand size i e 16 bit operands aligned on 0 modulo 2 addresses 32 bit operands aligned on 0 modulo 4 addresses If the operand alignment fails these guide...

Page 76: ...Times Source Destination Rx Ax Ax Ax d16 Ax d8 Ax Xi xxx wl Dn 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 An 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 An 2 1 0 2 1 1 2 1 1 2 1 1 2 1 1 3 1 1 2 1 1 An 2...

Page 77: ...l Dx 1 0 0 Scc Dx 1 0 0 swap Dx 1 0 0 tst b ea 1 0 0 3 1 0 3 1 0 3 1 0 3 1 0 4 1 0 3 1 0 1 0 0 tst w ea 1 0 0 3 1 0 3 1 0 3 1 0 3 1 0 4 1 0 3 1 0 1 0 0 tst l ea 1 0 0 2 1 0 2 1 0 2 1 0 2 1 0 3 1 0 2...

Page 78: ...1 0 23 1 0 20 0 0 DIVS L ea Dx 35 0 0 38 1 0 38 1 0 38 1 0 38 1 0 DIVU L ea Dx 35 0 0 38 1 0 38 1 0 38 1 0 38 1 0 eor l Dy ea 1 0 0 3 1 1 3 1 1 3 1 1 3 1 1 4 1 1 3 1 1 eori l imm Dx 1 0 0 lea ea Ax 1...

Page 79: ...i l imm Dx 1 0 0 subq l imm ea 1 0 0 3 1 1 3 1 1 3 1 1 3 1 1 4 1 1 3 1 1 subx l Dy Dx 1 0 0 Table 3 13 Miscellaneous Instruction Execution Times Opcode EA Effective Address Rn An An An d16 An d8 An Xn...

Page 80: ...the time required until the processor begins sampling continuously for interrupts 4 PEA execution times are the same for d16 PC 5 PEA execution times are the same for d8 PC Xn SF Table 3 14 General B...

Page 81: ...C Master clocks MCLK1 and MCLK2 are derived directly from CRIN The PLL is configured by writing to a configuration register The PLL Configuration Register must always be programmed to Bypass mode befo...

Page 82: ...4 2 Table 4 1 PLL Memory Map Address MBAR2BAS Access Size Bits Name Description Reset 180 RW 32 PllConfig PLL configuration register 0x02020088 Divide By CPUDIV VCXO Phase Frequency Comparator Divide...

Page 83: ...28 CLSEL MCLK1 and MCLK2 select 7 27 Reserved 26 24 CPUDIV CPU clock divider 8 9 23 CRSEL 0 Fin CRIN 1 Fin CRIN 2 3 22 AUDIOSEL If pull up on address pin A20 A24 Faudio LRCK3 AUDIOCLK GPIO43 If pull...

Page 84: ...ote 5 and vcxoout setting as shown in Table 4 3 7 Field determines frequency output on MCLK1 and MCLK2 pins When frequency is CRIN 2 or CRIN 4 duty cycle is 50 When frequency is CRIN 3 duty cycle is 3...

Page 85: ...s will result in the required 0 5 ms for the PLL to lock Other Fin frequencies can be used however the resulting lock time will be slightly longer In a second step this VCXO clock is divided by VCXOOU...

Page 86: ...derived directly from the CRIN pin Clock settings depend on CRSEL CLSEL and AUDIOSEL bits as explained in Table 4 7 As the table shows the AUDIO_CLOCK is completely derived from the AUDIOSEL bit and...

Page 87: ...nfigured with a power down bit This bit when set to 1 this sets the PLL to Sleep mode In Sleep mode the VCXO is turned off NOTE The PLL must go through the re locking procedure when it is re enabled 4...

Page 88: ...PIO function prior to entering Sleep mode 4 7 Selecting Audio_clock Input During power on reset the value on pin A20 A24 is sensed A 10 Kohm resistor should be connected between these pins and VDD GND...

Page 89: ...on Cache Hits Physically Located on the ColdFire Core High Speed Local Bus Nonblocking Design to Maximize Performance 16 Byte Line Fill Buffer Configurable Cache Miss Fetch Algorithm 5 2 Block Diagram...

Page 90: ...buffer is serviced in a single cycle Because the line fill buffer maintains valid bits on a longword basis hits in the buffer can be serviced immediately without waiting for the entire line to be fet...

Page 91: ...ries after modifying code segments The cache invalidation can be performed in two ways The assertion of bit 24 in the CACR forces the entire instruction cache to be marked as invalid The invalidation...

Page 92: ...ts corresponding cache location At the time of the miss the hardware indicator is set marking the fill buffer as most recently used If a subsequent access occurs to the cache location defined by bits...

Page 93: ...random values after reset The access column indicates if the corresponding register allows both read write functionality R W read only functionality R or write only functionality W If a read access t...

Page 94: ...che Control Register CACR Table 5 4 Cache Control Register Field Descriptions Bit Name Description 31 CENB The Cache Enable bit generally provides longword references used for sequential fetches If th...

Page 95: ...If DBWE 0 the termination of an operand write cycle on the processor s local bus is delayed until the external bus cycle is completed If DBWE 1 the write cycle on the local bus is terminated immediat...

Page 96: ...CM BWE WP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 3 Access Control Registers ACR0 ACR1 Table 5 6 Access Control Registers Field Descriptions Bit Name Description 31 24 BA The Base Address An...

Page 97: ...buffered writes provides higher system performance but recovery from access errors may be more difficult For the ColdFire CPU the reporting of access errors on operand writes is always imprecise and e...

Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...

Page 99: ...ing on configuration information instruction fetches may be sent to both the cache and the SRAM block simultaneously If the reference is mapped into the region defined by the SRAM the SRAM provides th...

Page 100: ...al control fields These fields are detailed in the following tables NOTE All unused bits in the RAMBAR register must be initialized to zero Address CPU C04 Access User read write 31 30 29 28 27 26 25...

Page 101: ...the ColdFire processor core 0 Allows read and write accesses to the SRAM module 1 Allows only read accesses to the SRAM module 7 6 Reserved should be cleared 5 1 C I SC SD UC UD Address Space Masks A...

Page 102: ...initialization functions 6 3 3 SRAM Initialization Code The following code segment describes how to initialize the SRAM The code sets the base address of the SRAM at 20000000 and then initializes the...

Page 103: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 Freescale Semiconductor 6 5 Table 6 2 Typical RAMBAR Setting Examples Data Contained in SRAM RAMBAR 7 0 Code Only 2B Data Only 35 Both Code And Data 21...

Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...

Page 105: ...standard synchronous dynamic random access memory SDRAM components Programmable SDRAS SDCAS and refresh timing Support for page mode Support for 16 wide SDRAM blocks 7 1 1 Block Diagram The basic com...

Page 106: ...Page hit logic Determines if the next DRAM access is in the same DRAM page as the previous one This information is passed on to the control logic Address multiplexing Multiplexes addresses to allow co...

Page 107: ...should be connected to the corresponding SDRAM SRAS SDCAS Synchronous column address strobe Indicates a valid column address is present and can be latched by the SDRAM SDCAS should be connected to the...

Page 108: ...us mode When in synchronous mode the DRAM controller can be switched to ADRAM mode only by resetting the MCF5253 0 Asynchronous DRAM Default at reset Do not use 1 Synchronous DRAM Note bit setting SO...

Page 109: ...0 3 clocks 01 6 clocks 1x 9 clocks 8 0 RC Refresh count Controls refresh frequency The number of bus clocks between refresh cycles is RC 1 16 Refresh can range from 16 8192 bus clocks to accommodate b...

Page 110: ...p 110 23 24 and up 111 24 25 and up This encoding and the address multiplexing scheme handle common SDRAM organizations Bank select lines include a base line and all address lines above for SDRAMs wit...

Page 111: ...The page stays open and only SDCAS needs to be asserted for sequential SDRAM accesses that hit in the same page regardless of whether the access is a burst 1 0 Reserved should be cleared Address MBAR...

Page 112: ...ans that when we program the A20 A24 pin to be A24 We no longer have A20 available to any memory device connected to the memory bus To use the tables find the one that corresponds to the number of col...

Page 113: ...ire memory space A20 must be sent to the D RAM To get this done the only way is to make sure the D RAM controller outputs A20 during the CAS phase on A21 and ensure address pin A21 is connected to a D...

Page 114: ...de and address incrementing during burst cycles are controlled by the MCF5253 DRAM controller Thus instead of the SDRAM enabling its internal burst incrementing capability the MCF5253 controls this fu...

Page 115: ...S to SCAS delay tRCD of 2 BCLK cycles NOTE Data is available upon SCAS assertion and a burst write cycle completes two cycles sooner than a burst read cycle with the same tRCD The next bus cycle is in...

Page 116: ...burst page mode except that it allows the processor core to handle successive bus cycles that hit the same page without having to close the page When the current bus cycle finishes the MCF5253 core in...

Page 117: ...us Page Mode Access Consecutive Reads Figure 7 9 shows a write followed by a read in continuous page mode Because the bus cycle is terminated with a WRITE command the second cycle begins sooner after...

Page 118: ...s the refresh request flag This refresh cycle includes a delay from any precharge to the auto refresh command the auto refresh command and then a delay until any ACTV command is allowed Any SDRAM acce...

Page 119: ...to maintain the integrity of the data stored in the SDRAM The DRAM controller supports self refresh with DCR IS When IS is set the SELF command is sent to the SDRAM When IS is cleared the SELFX comma...

Page 120: ...e to configure the operation of SDRAMs namely their burst operation and CAS latency through the SDRAM mode register CAS latency is a function of the speed of the SDRAM and the bus clock of the DRAM co...

Page 121: ...e 7 12 shows the MRS command which occurs in the first clock of the bus cycle Figure 7 12 Mode Register Set MRS Command 7 6 SDRAM Example This example interfaces a Samsung K4S641633 1M x 16 bit x 4 ba...

Page 122: ...10 CMD A11 BA0 BA1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field SO NAM COC IS RTIM RC Setting 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 hex 8 0 1 2 Figure 7 13 Initialization Values for DCR Table 7 14 DCR Initiali...

Page 123: ...12 11 10 9 8 7 6 5 4 3 2 1 0 Field RE CASL CBM IMRS PS IP PM Setting 0 01 010 0 10 0 1 hex 1 2 2 4 Figure 7 15 DACR Register Configuration Table 7 15 DACR Initialization Values Field Setting Descripti...

Page 124: ...been initiated 2 PM 1 Indicates continuous page mode 1 0 Reserved Don t care 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field BAM Setting 0 0 0 0 0 0 0 0 0 1 1 1 0 1 hex 0 0 7 4 15 14 13 12 11 10...

Page 125: ...the desired initialization setting 6 C I 1 Disable CPU space access 5 AM 1 Disable alternate master access 4 SC 1 Disable supervisor code accesses 3 SD 0 Enable supervisor data accesses 2 UC 1 Disable...

Page 126: ...nce move w 0x8012 d0 Initialize DCR move w d0 DCR move l 0xFF881220 d0 Initialize DACR0 move l d0 DACR0 move l 0x00740075 d0 Initialize DMR0 move l d0 DMR0 Precharge Sequence move l 0xFF881228 d0 Set...

Page 127: ...bit in DACR0 move l d0 DACR0 Mode Register Initialization Sequence move l 0x00600075 d0 Mask bit 19 of address move l d0 DMR0 move l 0xFF889260 d0 Enable DACR0 IMRS DACR0 RE remains set move l d0 DAC...

Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...

Page 129: ...e 16 bit data bus 16 bit port size Generates byte word longword and line size transfers Burst and burst inhibited transfer support Internal termination generation TA 8 2 Bus and Control Signals Althou...

Page 130: ...to immediately generate the TA input one or two wait states may be inserted in the bus access The TA signal function is not available after reset It must be enabled by configuring the appropriate pin...

Page 131: ...are selected When the address decode matches one of the chip select spaces the MCF5253 processor will pull low the appropriate chip select low indicating an external bus access CS2 is also available...

Page 132: ...he same speed as the bus clock rate where all bus operations are synchronous to the rising edge of BCLK and the bus chip selects are synchronous to the falling edge of the BCLK which is shown in Figur...

Page 133: ...3 1 DRAM Controller Registers Figure 8 3 shows the byte lanes that external chip select memory and DRAM should be connected to and the sequential transfers that would occur for each memory if a longwo...

Page 134: ...d clocks by delaying the assertion of TA This refers to internal transfers only and not the write cycles This is done by programming the relevant chip select registers If 0000 is programmed in the WS...

Page 135: ...he rising edge of BCLK the MCF5253 places a valid address on the address bus and drives RW high if it is not already high STATE 1 The appropriate CS and OE are asserted on the falling edge of BCLK STA...

Page 136: ...elect module STATE 5 CS and OE are negated on the falling edge of state 5 S5 The MCF5253 stops driving the address lines and RW on the rising edge of BCLK terminating the read cycle The external devic...

Page 137: ...alling edge of BCLK STATE 2 The data bus is driven out of high impedance as data is placed on the bus on the rising edge of BCLK STATE 3 During state 3 S3 the MCF5253 waits for a cycle termination sig...

Page 138: ...he cycle Through the chip select control registers users can enable bursting on reads bursting on writes or bursting on both reads and writes if desired 8 5 5 1 Line Transfers A line is defined as a 1...

Page 139: ...e cycle until the last cycle which can be held for a maximum of 2 BCLK past the TA assertion CS and OE remain asserted throughout the burst transfer Figure 8 8 shows a line access read with one wait s...

Page 140: ...TE The bus cycle begins similar to a basic write bus cycle with data being driven one clock after the address Also notice that the next pipelined burst data is driven one cycle after the write data ha...

Page 141: ...ur Unlike opcodes because operands can reside at any byte boundary they are allowed to be misaligned Although the MCF5253 does not enforce any alignment restrictions for data operands including progra...

Page 142: ...s one type of reset which resets the entire MCF5253 the external master reset input RSTI To perform a master reset an external device asserts the reset input pin RSTI When power is applied to the syst...

Page 143: ...y connected to CS0 Then CS0 is configured to address the external boot ROM Flash The configuration for CS0 at this time is hard wired inside the MCF5253 Configuration is summarized in Table 8 9 8 7 1...

Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...

Page 145: ...rces Address space masking to internal peripherals and SIM resources Interrupt Controller Two interrupt controllers Programmable interrupt level 1 7 for peripheral interrupts System Protection and Res...

Page 146: ...ee Chapter 20 Background Debug Mode BDM Interface for more details Table 9 1 MBAR Register Addresses Address Name Size Bytes Description CPU C0F MBAR 4 Module base address register CPU C0E MBAR2 4 Mod...

Page 147: ...mary Interrupt Control Reg ICR8 ICR9 ICR10 ICR11 MBAR2 000 GPIO 0 31 input reg GPIO READ READ ONLY MBAR2 004 GPIO 0 31 output reg GPIO OUT MBAR2 008 GPIO 0 31 output enable reg GPIO ENABLE MBAR2 00C G...

Page 148: ...CPU C0F Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 W Reset 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 149: ...nge 0 User data space access allowed 1 User data space access masked 0 V This bit defines when the base address is valid 0 MBAR address space not visible by CPU 1 MBAR address space visible by CPU Add...

Page 150: ...interrupt controller registers and their register descriptions The primary interrupt controller is centralized and services the following Software Watchdog Timer SWT Timer modules I2C0 module 7 1 LS I...

Page 151: ...11 0 IPR and IMR Table 9 5 gives the location and description of each ICR Primary interrupts are programmed to a level and priority All primary interrupts have a unique Interrupt Control Register ICR...

Page 152: ...set 0 0 0 0 0 0 Figure 9 4 Interrupt Control Register ICR Table 9 6 Interrupt Control Register ICR Field Descriptions Field Description 7 AVEC The Autovector Enable bit determines whether the interrup...

Page 153: ...1 1 Internal Module 5 101 1 0 Internal Module 5 101 0 1 Internal Module 5 101 0 0 Internal Module 4 100 1 1 Internal Module 4 100 1 0 Internal Module 4 100 0 1 Internal Module 4 100 0 0 Internal Modul...

Page 154: ...R Field Descriptions Field Description 31 18 Reserved 17 8 IMR Each Interrupt Mask bit corresponds to an interrupt source defined in the Interrupt Control Register ICR An interrupt is masked by settin...

Page 155: ...defined by the Interrupt Control Register At every clock this register samples the signal generated by the interrupting source The corresponding bit in this register reflects the state of the interrup...

Page 156: ...upts MBAR2 16B INTBASE 8 Interrupt base vector 00 R W MBAR2 167 SPURVEC 8 spurious vector 00 R W Table 9 12 Secondary Interrupt Level Programming Bit Assignment Address Name Bit 31 28 Bit 27 24 Bit 23...

Page 157: ...ned by adding the interrupt number to BASE For example Interrupt 23 vector is base 23 Address MBAR2 167 Access User read write 7 6 5 4 3 2 1 0 R spurvec 7 spurvec 6 spurvec 5 spurvec 4 spurvec 3 spurv...

Page 158: ...pt 33 GPI1 SIM gpio interrupt 32 GPI0 SIM gpio interrupt 31 IIS1TXUNOV AUDIO iis1 transmit FIFO under over 30 IIS1TXRESYN AUDIO iis1 transmit FIFO resync 29 IIS2TXUNOV AUDIO iis2 transmit FIFO under o...

Page 159: ...3 full 4 IIS1TXEMPTY AUDIO I2 S1 transmit FIFO empty 3 IIS2TXEMPTY AUDIO I2 S2 transmit FIFO empty 2 EBUTXEMPTY AUDIO EBU transmit FIFO empty 1 PDIR2 FULL AUDIO Processor data in 2 full 0 PDIR1 FULL A...

Page 160: ...buffer reg 2 full Read data 57 11 TX2EMPTY Interrupt set if transmit buffer reg 2 empty Write data 57 Table 9 16 Extraint Register Descriptions ExtraInt MBAR2 198 Bit Field Name Access Description Int...

Page 161: ...ssociated registers and descriptions 9 5 1 Reset Status Register The RSR contains a bit for each reset source to the SIM A bit set to 1 indicates the last type of reset that occurred The RSR is update...

Page 162: ...inating a locked bus is shown in Figure 9 10 Figure 9 10 MCF5253 Unterminated Access Recovery When the SWT times out and SWRI register bit is programmed for a software reset an internal reset will be...

Page 163: ...it in SYPCR 2 Service the SWSR write 55 then write AA to SWSR This action resets the counter 3 Re write new SWT 1 0 and SWP values to SYPCR register 4 Re enable SWT by writing a 1 to SWE bit in SYPCR...

Page 164: ...the timeout period for the SWT as shown in Table 9 19 At system reset the software watchdog timer is set to the minimum timeout period 2 SWTA Software Watchdog Transfer Acknowledge Enable 0 SWTA Tran...

Page 165: ...does not disable any system clocks 9 7 MCF5253 Bus Arbitration Control Registers This section contains the Default Bus Master Park register the internal arbitration operation and the configuration of...

Page 166: ...sfer and DMA channels 0 and 1 both set to BWC 010 are asserting an internal bus request signal then the DMA channel 0 would gain ownership of the bus after the core but after channel 0 finishes its tr...

Page 167: ...n between DMA and ColdFire Core 01 Park on master ColdFire Core 10 Park on master DMA Module 11 Park on current master Table 9 21 Round Robin PARK 1 0 00 Current Highest Priority Master Current Lowest...

Page 168: ...ontrols the BCR and address mapping for the DMA The bit allows the byte count register to be used as a 24 bit register See Section 14 4 DMA Memory Map and Register Definitions for memory maps and bit...

Page 169: ...26 RCK QSPIDIN QSPIDOUT GPIO26 GPIO1 READ 58 ADOUT SCLK4 GPIO58 GPIO READ 25 QSPICLK SUBR GPIO25 GPIO1 READ 57 ADIN5 GPI57 GPIO READ 24 QSPICS2 MCLK2 GPIO24 GPIO1 READ 56 ADIN4 GPI56 GPIO READ 23 LRCK...

Page 170: ...READ 6 0 have interrupt capability On every low to high edge transition of these inputs one of the bits 0 6 of register GPIO INT STAT is set On every high to low edge of the inputs one of the bits 8...

Page 171: ...ral purpose output GPIO35 by setting its controlling bit 35 in the GPIO1 FUNCTION register Table 9 28 GPIO INT STAT GPIO INT CLEAR and GPIO INT EN Interrupts Event GPIO INT STAT GPIO INT CLEAR GPIO IN...

Page 172: ...is driven low If 1 is programmed the pin is driven high Figure 9 15 General Purpose Pin Logic for Pin SCLK3 GPIO35 Table 9 29 General Purpose Output Register Bits to Pins Mapping GPIO Function GPIO E...

Page 173: ...cessary to set the appropriate GPIO FUNCTION bit to 0 to enable the primary or secondary function 16 QSPICS1 EBUOUT2 GPIO16 I O 48 PST2 INTMON2 GPIO48 I O 15 QSPICS0 EBUIN4 GPIO15 I O 47 PST3 INTMON1...

Page 174: ...3 SFSY SCLK4 TOUT0 RXD2 TXD2 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 9 16 Pin Configuration Register Table 9 30 Triple Multiplexed Pins Pin Bit Name Description J3 CS0 CS4 Function select with...

Page 175: ...1 23 24 DDATA1 RTS1 SDATA2BS2 GPIO2 24 23 0 0 DDATA1 0 1 SDATA2BS2 1 0 RTS1 1 1 RTS1 M7 25 CS1 QSPICS3 GPIO28 0 CS1 1 QSPICS3 N7 26 RCK QSPIDIN QSPIDOUT GPIO26 0 RCK 1 QSPIDIN QSPIDOUT Note QSPIDOUT i...

Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...

Page 177: ...ct Signals The MCF5253 provides three programmable chip selects that can directly interface with SRAM EPROM EEPROM and peripherals Chip select CS2 provides separate read and write strobes for an AT bu...

Page 178: ...pin However the registers for CS3 are available and can be used to enable the BUFENx outputs These BUFENx outputs could then be used as a physical CS3 This would require programming the CS3 registers...

Page 179: ...external chip select outputs the module contains one chip select CS2 for use with AT bus peripherals such as IDE drives and Flash Card interfaces Capabilities for CS2 are like CS1 but there are some e...

Page 180: ...global chip select are determined The reset state of CS0 is always auto acknowledge AA with 15 wait states and the port size is 16 bits Provided the required address range is first loaded into chip s...

Page 181: ...d R W MBAR 0x9C CSMR2 32 Chip Select Mask Register IDE Uninitialized except V 0 R W MBAR 0xA2 CSCR2 16 Chip Select Control Register IDE Uninitialized R W MBAR 0xA4 CSAR3 16 Chip Select Address Registe...

Page 182: ...et Address MBAR 0x80 CSAR0 MBAR 0x8C CSAR1 MBAR 0x98 CSAR2 MBAR 0xA4 CSAR3 MBAR 0xB0 CSAR4 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R BA31 BA30 BA29 BA28 BA27 BA26 BA25 B...

Page 183: ...r all CS are equal to 2n where n number of bits set in the base address mask field of the respective CSMR 16 For example if CSAR0 were set at 0000 and CSMR0 were set at 0008 then chip select CS0 would...

Page 184: ...ress space becomes a regular external bus access and no chip select is activated AM Alternate master access DMA C I Interrupt cycle access SC Supervisor code access SD Supervisor data access UC User c...

Page 185: ...sociated with each chip select It determines where data is driven during write cycles and where data is sampled during read cycles Port size should always be programmed to 16 bits 00 Reserved 01 Reser...

Page 186: ...l chip select is de activated by validating CS0 Program Chip Select 1 Registers move l 00000000 D0 CSAR1 base addresses 00000000 to 001FFFFF move l D0 CSAR1 and 80000000 to 801FFFFF move w 09B0 D0 CSC...

Page 187: ...er appropriately NOTE The maximum system clock SYSCLK is 1 2 CPU clock 11 2 Timer Features Each of the general purpose 16 bit timers provide the following features Maximum period of 3 83 seconds at 70...

Page 188: ...The CLK bits of the corresponding Timer Mode Register TMR select the clock input source The prescaler is programmed to divide the clock input by values from 1 to 256 The prescalar output is used as an...

Page 189: ...er This register programs the various timer modes and is cleared by reset Table 11 1 Memory Map for General Purpose Timers Timer 0 Address Timer 1 Address Timer Module Registers MBAR 140 MBAR 180 Time...

Page 190: ...Timer count is reset immediately after reaching the reference value 0 Free run Timer count continues to increment after reaching the reference value 2 1 CLK Input Clock Source for the Timer 11 Invali...

Page 191: ...t the bit value more than one bit can be cleared at a time The REF and CAP bits must be cleared before the timer will negate the IRQ to the interrupt controller Reset clears this register Address MBAR...

Page 192: ...ANNOT provide interrupt vectors only autovectors Autovectors and ICRs have been set up as follows The interrupt levels and priorities were chosen by random for demonstrative purposes Users should defi...

Page 193: ...onents 12 1 Overview The ADC functionality is based on the sigma delta concept using 12 bit resolution with a measurement frequency of ADCLK 4096 12 1 1 Block Diagram The ADC block diagram and externa...

Page 194: ...buffer 9 The feed back loop 1 7 8 9 will keep the voltage on the external integrator capacitor close to ADIN0 and in this way the voltage on ADIN0 is proportional to the duty cycle of the signal on A...

Page 195: ...has no affect 0 No ADC interrupt pending 1 ADC Interrupt pending 6 INTEN ADC interrupt enable 0 Interrupt disabled 1 Interrupt enabled 5 4 ADOUT_DRIVE 00 ADOUT drives Vdd for Hi GND for low 01 ADOUT...

Page 196: ...r See Section 17 5 Serial Audio Interface I2S EIAJ Register Descriptions The ADC uses the sigma delta modulation principle The ADC external components required are an integrator circuit comprising of...

Page 197: ...and this affects the accuracy of the measurement For a correct measurement the voltage over C should be equal to the input voltage during the entire measurement cycle 1024 ADC clocks Therefore for th...

Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...

Page 199: ...th both an IDE device and a SmartMedia device connected although both cannot be supported simultaneously as the IDE_DIOR and IDE_DIOW signals can only be used to interface to one or the other NOTE Sma...

Page 200: ...so prevents the SDRAM and Flash ROM signals from going to from the IDE SmartMedia interfaces In some systems where the Flash ROM load may be excessively high or there is the requirement for additional...

Page 201: ...e on CS1 or CS2 The extra bus signals and their configuration are detailed in the following section 13 1 1 Buffer Enables BUFENB1 BUFENB2 and Associated Logic Buffer enables BUFENB1 and BUFENB2 allow...

Page 202: ...lock post drive 11 3 clock post drive 0 7 5 cs1pre Pre drive for CS0 CS4 000 No predrive 001 1 clock 010 2 clocks 011 3 clocks 100 4 clocks 101 5 clocks 0 9 8 cs1post Post drive for CS1 00 No post dri...

Page 203: ...ENB2 active on CS1 cycles 0 20 bufen2cs2en 0 BUFENB2 inactive on IDE_DIOR IDE_DIOW cycles 1 BUFENB2 active on IDE_DIOR IDE_DIOW cycles 0 21 bufen2cs3en 0 BUFENB2 inactive on CS3 cycles 1 BUFENB2 activ...

Page 204: ...wn in Figure 13 4 Table 13 3 IDEConfig2 Register Address Access Size Bits Name Description MBAR2 0x190 RW 32 IDE config2 Configuration of TA generation on CS2 Table 13 4 IDEConfig2 Register Field Desc...

Page 205: ...53 IDE_DIOR output WE input connect to MCF5253 IDE_DIOW output D0 7 connect to MCF5253 data bus wires 31 24 CE connect to always low ALE connect to general purpose output CLE connect to general purpos...

Page 206: ...ycles 2 Program the IDE config1 register Only fields CS2PRE CS2POST BUFEN1CS2EN BUFEN2CS2EN The values required for the buffer enable signals BUFEN1CS2EN and BUFEN2CS2EN depend on the hardware configu...

Page 207: ...by IDECONFIG2 register logic WS 3 0 not relevant PS 1 0 10 16 bit port size BSTR BSTW 00 no burst read write cycles 2 Program the IDE config1 register Fields CS2PRE CS2POST BUFEN1CS2EN BUFEN2CS2EN an...

Page 208: ...OW low period To meet 70 nS t2 period waitCount2 must be set to 3 t5a 50 WAITCOUNT2 WAITCOUNT2 3 5 T t5a tio tbuf tio Input output delay of device Typ 10 nS tbuf External buffer delay Typ 15 nS To mee...

Page 209: ...edia interface there are four blocks 1 The clock generator generates the clock to the flash device 2 The Processor interface handles interrupts and processor I O 3 Interface shift register 1 4 Interfa...

Page 210: ...as shown in Figure 13 9 Table 13 8 Flash Media Registers Address Access Size Bits Name Description MBAR2 0x460 RW 32 FLASHMEDIACONFIG Clock and general configuration MBAR2 0x464 RW 32 FLASHMEDIACMD1...

Page 211: ...d timing however Memory Stick specs stipulate it should be 0 0 18 Reserved 0 17 16 STOPCLOCK Stop Clock3 00 Normal operation 01 Freeze clock low 10 Freeze clock high 01 15 8 CLOCKCOUNT1 CLOCKCOUNT1 12...

Page 212: ...full data is transferred to the RxBUFFERREG If the receive buffer register is full the interface shift register will stop the SCLKOUT clock and wait until the RxBUFFERREG is read If the number of bits...

Page 213: ...egisters 1 2 Field Description MemoryStick Mode Field Description 31 22 Reserved 21 SENDCRC 0 No CRC inserted 1 Packet bits 0 15 will be replaced with CRC 20 NEXT BS Next value to output on BS pin Mem...

Page 214: ...d 4 bit wide FLASHMEDIACMD1 22 16 0x04 wait for read 1 bit wide FLASHMEDIACMD1 22 16 0x66 write data 4 bit wide FLASHMEDIACMD1 22 16 0x26 write data 1 bit wide FLASHMEDIACMD1 22 16 0x00 receive handsh...

Page 215: ...cmd line after receiving flash status Drive data line after sending command FLASHMEDIACMD2 23 16 0xC0 Receive status for write data command from SD FLASHMEDIACMD2 23 16 0x06 Send non data command to...

Page 216: ...0_2 INT_LEVEL1 SHIFT_BUSY1 CRC_IS_0_1 W Reset 0 0 0 0 Figure 13 15 Flash Media Status Register FLASHMEDIASTAT Table 13 14 Flash Media Status Register Field Descriptions Field Description 31 6 Reserved...

Page 217: ...d Interrupt 31 12 Reserved 11 TX2EMPTY Interrupt set if transmit buffer reg 2 empty Write data 57 10 RCV2FULL Interrupt set if receive buffer reg 2 full Read data 57 9 TX1EMPTY Interrupt set if transm...

Page 218: ...implemented as a 16 bit read There is no specific handshake command NOTE The Flash Media interface can handle two Memory Stick cards One is attached to the primary interface the other to the secondar...

Page 219: ...lock which prevents data overrun write cmd_reg 19 16 0001 write cmd_reg 15 0 no of bits to read from stick write cmd_reg 20 new value on BS pin write cmd_reg 21 0 cmd_reg 15 0 0 or fall edge on shiftB...

Page 220: ...errun Figure 13 20 Writing Data to Memory Stick Timing write cmd_reg 19 16 0010 write cmd_reg 15 0 no of bits to write to stick write cmd_reg 20 new value on BS pin write cmd_reg 21 0 no crc will be i...

Page 221: ...mentary operations There are three elementary operations in SD mode Send command to card write cmd_reg 19 0 80000h write cmd_reg 20 new value on BS pin write cmd_reg 21 0 end wait for 5 sclk clock per...

Page 222: ...umber of bits bytes longwords corresponding with CMDBITCOUNT must be written to FLASHMEDIADATA2 during the command transmission All words except the first word contain 32 bits of data The first word c...

Page 223: ...4 bit wide bus wideShiftMask is 0x400000 CRC length is 64 bits For 1 bit wide bus wideShiftMask 0 CRC length is 16 bits Note 2 If read data packet followed by another read data packet block read set...

Page 224: ...g last write to FLASHMEDIACMD2 Writing 0x3 to FLASHMEDIACMD1 must take place after SHIFTBUSY1 has gone high One or more write packets can be sent to the card using this timing diagram Figure 13 26 Rea...

Page 225: ...ultiple block and write multiple block commands 13 5 7 1 Send Command to Card No Data This sequence is intended for commands that require status response from the card but no data transfer between hos...

Page 226: ...t_mask while CMDBITCOUNT 0 if FLASHMEDIADATA2 empty write FLASHMEDIADATA2 CMDBITCOUNT CMDBITCOUNT 32 wait until FLASHMEDIACMD2 0xFFFF 0 OR wait until SHIFTBUSY2FALL event start receiving data and stat...

Page 227: ...HMEDIACMD2 0xC60000 CMDBITCOUNT while CMDBITCOUNT 0 if FLASHMEDIADATA2 empty write data to FLASHMEDIADATA2 CMDBITCOUNT CMDBITCOUNT 32 one of the two waits need to be done First one is more suitable fo...

Page 228: ...til SHIFTBUSY1RISE event OR wait until FLASHMEDIASTATUS 2 0 FLASHMEDIACMD1 3 wait until FLASHMEDIADATA1 full CRC status 0x7 FLASHMEDIADATA1 FLASHMEDIACMD1 0x80000 wait for interrupt now On rising edge...

Page 229: ...nt programmable DMA controller module channels Auto alignment feature for source or destination accesses Dual address transfer capability Channels 0 and 1 request signals may be connected to the audio...

Page 230: ...e internal signals are asserted by a peripheral device to request an operand transfer between that peripheral and memory MUX ARBITRATION INTERFACE DATAPATH CONTROL INTERNAL INTERNAL CURRENT CHANNEL CH...

Page 231: ...A channels support continuous and cycle steal transfer modes The DMA controller supports dual address transfers In dual address mode the DMA channel supports 32 bits of address and 32 bits of data Dua...

Page 232: ...rce Selection The routing control register DMAroute controls where the non processor DMA request for the four DMA channels is coming from Table 14 1 Memory Map DMA Channels DMA Channel Address 31 24 2...

Page 233: ...for DMA3 Block 0x00 DMA3 ATA ATA 0x80 DMA3 UART1 UART1 Table 14 5 DMA2REQ Field Definition DMA2req 7 0 Field Value Request Source for DMA2 Block 0x00 DMA2 ATA ATA 0x80 DMA2 UART0 UART0 Table 14 6 DMA...

Page 234: ...User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R SAR31 SAR30 SAR29 SAR28 SAR27 SAR26 SAR25 SAR24 SAR23 SAR22 SAR21 SAR20 SAR19 SAR18 SAR17 SAR16 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 235: ...module See Table 14 6 for the bit locations NOTE If the BCR24BIT 1 the upper 8 bits are loaded with zeros The BCR decrements on the successful completion of the address phase of a write transfer in du...

Page 236: ...tus Register for more details 14 4 5 DMA Control Register The DMA control register DCR sets the configuration of the DMA controller module Depending on the state of the BCR24BIT in the MPARK register...

Page 237: ...ables peripheral request to initiate transfer Internal request is always enabled It is initiated by writing a 1 to the START bit 29 CS Cycle steal 0 DMA continuous make read write transfers until the...

Page 238: ...000 The bus is relinquished after transferring 232 bytes because the BCR is at 32768 which is a multiple of 16384 24 DAA Dual address access 0 The DMA channel is in dual address mode 1 Reserved 23 S_R...

Page 239: ...the detailed structure of the DMA status register 18 17 DSIZE The Destination Size field determines the data size of the destination bus cycle for the DMA controller module Table 14 11 shows the encod...

Page 240: ...rtion of a transfer 3 Reserved 2 REQ Request 0 There is no request pending or the channel is currently active The bit is cleared when the channel is selected 1 The DMA channel has a transfer remaining...

Page 241: ...programmed to 000 Then the active DMA channel continues until the BCR decrements to zero or the DONE bit is set A limited rate can be achieved by programming the BWC field to any value other than 000...

Page 242: ...that the source size SSIZE DSC 21 20 and destination size DSIZE DSR 18 17 for dual address access are consistent with the source address and destination address The CE bit is also set if inconsistenc...

Page 243: ...ress is the starting address of the data block This address can be any byte address The DAR should contain the destination write address If the transfer is from a peripheral device to memory or memory...

Page 244: ...e greater than 16 the address will determine the size of the transfer Single byte word or longword transfers will occur until the address is aligned to the programmed size boundary at which time the p...

Page 245: ...nditions When the bus encounters a read or write cycle that terminates with an error condition the appropriate bit of the DSR is set depending on whether the bus cycle was a read BES or a write BED Th...

Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...

Page 247: ...for addressing differences Each UART module shown in Figure 15 1 consists of the following functional areas Serial Communication Channel 16 Bit Baud Rate Timer Internal Channel Control Logic Interrupt...

Page 248: ...serts the appropriate start stop and optional parity bits then outputs a composite serial data stream on the channel transmitter serial data output TxD Refer to Section 15 3 2 1 Transmitter for additi...

Page 249: ...tive high signals The term assert or assertion indicates that a signal is active or true independent of the level represented by a high or low voltage The term negate or negation indicates that a sign...

Page 250: ...Clear To Send The multiplexed signals DDATA2 CTS0 GPIO3 and DDATA0 CTS1 SDATA0_SDIO1 GPIO1 can be programmed as general purpose inputs or Clear To Send inputs When programmed as CTS this active low in...

Page 251: ...3 Baud Rate Timer Generator Diagram 15 3 1 1 Calculating Baud Rates The system clock goes through a divide by 32 prescaler and then passes through the 16 bit divider of the concatenated UBG1n and UBG...

Page 252: ...r output on the falling edge of the clock source After the transmission of the stop bits if a new character is not available in the transmitter holding register the TxD output remains in the high mark...

Page 253: ...ogrammed to operate in this mode RTS must be manually asserted before a message is transmitted In applications where the transmitter is disabled after transmission is complete and RTS is appropriately...

Page 254: ...ising edge of the programmed clock source The least significant bit is received first The data is then transferred to a receiver holding register and the RxRDY bit in the USR is set If the character l...

Page 255: ...e status bits parity error PE framing error FE and received break RB are appended to each data character in the FIFO overrun error OE is not appended By programming the error mode bit ERR in the chann...

Page 256: ...e enabled 15 3 3 Looping Modes The UART can be configured to operate in various looping modes as shown in Figure 15 7 These modes are useful for local and remote system diagnostic functions The modes...

Page 257: ...te Loopback Mode In this mode the channel automatically transmits received data on the TxD output on a bit by bit basis The local CPU to transmitter link is disabled This mode is useful for testing re...

Page 258: ...e RxRDY bit in the USR and generating an interrupt if programmed to do so Each slave station CPU then compares the received address to its station address and enables its receiver if it wants to recei...

Page 259: ...e operation of the bus during read write and interrupt acknowledge cycles to the UART module All UART module registers must be accessed as bytes 15 3 5 1 Read Cycles The CPU accesses the UART module w...

Page 260: ...nd is accessed when the mode register pointer points to UMR1 The pointer is set to UMR1 by RESET or by a set pointer command using the control register After reading or writing UMR1 the pointer points...

Page 261: ...abled for both because such a configuration is incorrect Note Not available on UART2 6 RxIRQ RxIRQ Receiver Interrupt Select 1 FFULL is the source that generates IRQ 0 RxRDY is the source that generat...

Page 262: ...a 0 parity bit Force parity high forces a 1 parity bit 1 0 B C The Bits per Character bits select the number of data bits per character to be transmitted The character length listed in Table 15 4 doe...

Page 263: ...f stop bits Note Not available on UART2 4 TxCTS Transmitter clear to send If both TxCTS and TxRTS are enabled TxCTS controls the operation of the transmitter 0 CTS has no effect on the transmitter 1 E...

Page 264: ...onding character in the FIFO was received with incorrect parity When the multidrop mode is programmed this bit stores the received A D bit This bit is valid only when the RxRDY bit is set 0 No parity...

Page 265: ...iver buffer FIFO 0 The CPU has read the receiver buffer and no characters remain in the FIFO after this read Address MBAR 1C4 USCR0 MBAR 204 USCR1 MBAR2 C04 USCR2 Access User write only 7 6 5 4 3 2 1...

Page 266: ...eceiver The reset receiver command resets the receiver The receiver is immediately disabled the FFULL and RxRDY bits in the USR are cleared and the receiver FIFO pointer is reinitialized All other reg...

Page 267: ...the break conditions can be delayed by as much as two bit times If the transmitter is active the break begins when transmission of the character is complete If a character is in the transmitter shift...

Page 268: ...Taken The no action taken command causes the receiver to stay in its current mode If the receiver is enabled it remains enabled if disabled it remains disabled 15 4 5 3 2 Receiver Enable The receiver...

Page 269: ...ing additional characters until the shift register is ready to accept more data When the shift register is empty it checks the holding register for a valid character to be sent TxRDY bit cleared If a...

Page 270: ...ield Descriptions Field Description 7 5 3 1 Reserved 4 COS Change of State 1 A change of state high to low or low to high transition lasting longer than 25 50 s has occurred at the CTS input When this...

Page 271: ...le reset clears the contents of UISR Address MBAR 1D0 UACR0 MBAR 210 UACR1 MBAR2 C10 UACR2 Access User write only 7 6 5 4 3 2 1 0 R W IEC Reset 0 0 0 0 0 0 0 0 Figure 15 16 Auxiliary Control Register...

Page 272: ...ted the beginning or end of a received break 0 No new break change condition to report Refer to Section 15 4 5 Command Registers UCRn for more information on the reset break change interrupt command 1...

Page 273: ...R registers contain the 8 bit vector number of the internal interrupt 15 4 15 Input Port Registers UIPn The UIP registers show the current state of the CTS input 1 FFULL FIFO Full 1 Enable interrupt 0...

Page 274: ...nput is logic one 0 The current state of the CTS input is logic zero The information contained in this bit is latched and reflects the state of the input pin at the time that the UIP is read This bit...

Page 275: ...e actual checks as called from the SINIT routine When called SINIT places the UART in the local loopback mode and checks for the following errors Transmitter Never Ready Receiver Never Ready Parity Er...

Page 276: ...ister UACR Initialize the Input Enable Control IEC bit Clock Select Register UCSR Select the receiver and transmitter internal clock Mode Register 1 UMR1 1 If required program operation of Receiver Re...

Page 277: ...l Rev 1 Freescale Semiconductor 15 31 Figure 15 23 UART Software Flowchart 1 of 5 SERIAL MODULE INITIATE CHANNEL INTERRUPTS CALL CHCHK SAVE CHANNEL STATUS ANY ERRORS ASSERT REQUEST TO SEND RETURN Yes...

Page 278: ...IN LOCAL LOOPBACK MODEL ENABLE TRANSMITTER CLEAR STATUS WORD IS TRANSMITTER READY WAITED TOO LONG SEND CHARACTER TO TRANXMITTER SET TRANSMITTER NEVER READY FLAG A B HAS CHARACTER BEEN RECEIVED WAITED...

Page 279: ...ware Flowchart 3 of 5 HAVE FRAMING ERROR SET FRAMING ERROR FLAG HAVE PARITY ERROR SET PARITY ERROR FLAG DISABLE TRANSMITTER RESTORE TO ORIGINAL MODE RETURN A B GET CHARACTER FROM RECEIVER SAME AS TRAN...

Page 280: ...LACE RETURN ADDRESS ON SYSTEM STACK AND MONITOR WARM START ADDRESS SIRQ IRQ CAUSED BY BEGINNING OF A BREAK CLEAR CHANGE IN BREAK STATUS BIT HAS END OF BREAK IRQ ARRIVED YET CLEAR CHANGE IN BREAK STATU...

Page 281: ...UART Modules MCF5253 Reference Manual Rev 1 Freescale Semiconductor 15 35 Figure 15 27 UART Software Flowchart 5 of 5 OUTCH IS TRANSMITTER READY SEND CHARACTER TO TRANSMITTER RETURN Yes No...

Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...

Page 283: ...paround mode for continuous transfers 16 2 QSPI Module Overview The QSPI module communicates with the core using internal memory mapped registers starting at MBAR 400 See Section 16 4 QSPI Memory Map...

Page 284: ...ons The RAM is divided into three segments as follows 16 command control bytes command RAM Table 16 1 QSPI Input and Output Signals and Functions Signal Name Hi_Z or Actively Driven Function QSPI Data...

Page 285: ...3 The internal pointer is incremented Execution continues at the internal pointer address unless the QWR NEWQP value is changed After each command is executed QWR ENDQP and QWR CPTQP are compared When...

Page 286: ...he command and data RAM in the QSPI is indirectly accessible with QDR and QAR as 48 separate locations that comprise 16 words of transmit data 16 words of receive data and 16 bytes of commands A write...

Page 287: ...s that detail serial communication modules such as the QSPI that supports variable length data units To simplify this issue the functional unit is referred to as a word regardless of length QWR CPTQP...

Page 288: ...to clock delay enable DSCK bit in command RAM QCR DSCK enables the programmable delay period from QSPI_CS assertion until the leading edge of QSPI_CLK QDLYR QCD determines the period of delay before...

Page 289: ...her the default value BITSE 0 or the BITS 3 0 value BITSE 1 is used QMR BITS gives the required number of bits to be transferred 16 3 5 Data Transfer Operation is initiated by setting QDLYR SPE Shortl...

Page 290: ...DLYR SPE can be cleared 16 4 QSPI Memory Map and Register Definitions The programming model for the QSPI consists of six registers They are the QSPI mode register QMR QSPI delay register QDLYR QSPI wr...

Page 291: ...0 1011 11 1100 12 1101 13 1110 14 1111 15 9 CPOL Clock polarity Defines the clock polarity of QSPI_CLK 0 The inactive state value of QSPI_CLK is logic level 0 1 The inactive state value of QSPI_CLK is...

Page 292: ...the delay from assertion of the chip selects to valid QSPI_CLK transition 7 0 DTL Delay after transfer When the DT bit in the command RAM sets this field it determines the length of delay after the s...

Page 293: ...I Interrupt Register QIR Table 16 6 QSPI Interrupt Register QIR Field Descriptions Field Description 15 WCEFB Write collision access error enable A write collision occurs during a data transfer when t...

Page 294: ...reads and writes all data from and to the QSPI RAM through this register 3 WCEF Write collision error flag Indicates that an attempt has been made to write to the RAM entry that is currently being ex...

Page 295: ...dress QAR ADDR Access User write only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W CONT BITSE DT DSCK QSPI_CS Reset Figure 16 10 Command RAM Registers QCR0 QCR15 Table 16 7 Command RAM Registers QCRn Fie...

Page 296: ...external device for serial data transfer More than one chip select may be active at once and more than one device can be connected to each chip select 7 0 Reserved should be cleared 1 To keep the chip...

Page 297: ...0x7E00 0x7E00 0x7D00 0x7D00 0x7D00 0x7D00 0x7B00 0x7B00 0x7B00 0x7B00 0x7700 0x7700 0x7700 and 0x7700 to set up four transfers for each chip select The chip selects are active low in this example 7 Wr...

Page 298: ...Queued Serial Peripheral Interface QSPI Module MCF5253 Reference Manual Rev 1 16 16 Freescale Semiconductor...

Page 299: ...sional C channel and one for consumer C channel The audio interface module allows the direct retransmission of an audio signal received on one receiver to another transmitter without CPU intervention...

Page 300: ...EBU c channel Clock Select ebuTxUChannelStream 6 fields 6 fields 6 fields 1 2 3 4 5 6 8 9 10 11 12 13 14 15 18 19 22 23 24 25 26 27 28 29 30 31 iis4RcvData 39 0 IIS3 clock gen IIS3 Receive IIS3 Contr...

Page 301: ...his FIFO gives the data source some freedom when data is generated The FIFOs compensate for phase shifts when a transmitter takes data from another receiver In the case that the transmitter sends out...

Page 302: ...on registers Phase Configuration register and the XTrim register 17 3 Audio Interface Memory Map All of the Audio Interface registers listed in Table 17 1 have already been shown in the various parts...

Page 303: ...PDOR2 R 32 W MBAR2 0x74 MBAR2 0x78 MBAR2 0x7C MBAR2 0x80 Processor data out 3 left right PDOR3 32 W MBAR2 0x74 MBAR2 0x78 MBAR2 0x7C MBAR2 0x80 Processor data in 2 left right PDIR2 32 R MBAR2 0x84 U...

Page 304: ...W MBAR2 0xE0 MBAR2 0xE3 InterruptStat3 32 Interrupt status register R MBAR2 0xE0 MBAR2 0xE3 InterruptClear3 32 Interrupt clear register W Table 17 3 Interrupt Register Description Bit Interrupt Name...

Page 305: ...y 4 write to FIFO 3 IIS2TXEMPTY I2 S 2 transmit FIFO empty 3 write to FIFO 2 EBUTXEMPTY EBU transmit FIFO empty 2 write to FIFO 1 PDIR2 FULL Processor data in 2 full 1 read from PDIR2 0 PDIR1 FULL Pro...

Page 306: ...CK clock only operates correctly on a slave receiver therefore IIS3 If IIS1 is being used for transmit and receive in master mode then LRCK will be inverted on both the input and the output Thereby ca...

Page 307: ...1 0 0 1 0 0 0 Figure 17 3 IIS2 Configuration Registers 0x14 Address MBAR2 0x18 reset 0x0fc8 IIS3config MBAR2 0x1C reset 0x0fc8 IIS4config SCLK4 Access User read write 31 30 29 28 27 26 25 24 23 22 21...

Page 308: ...set to 1 sample remaining 0 Normal operation TXSOURCE SELECT See notes 2 9 12 and 15 following bit these descriptions 0 000 Digital zero 0 001 PDOR1 0 010 PDOR2 0 011 PDOR3 0 100 IIS1 RcvData 0 101 II...

Page 309: ...IFO outputs zero on its outgoing data bus regardless of the input side and content of the FIFO No FIFO related exceptions are generated 13 When the FIFO leaves the reset state because the user writes...

Page 310: ...terface 2 transmit FIFO empty The action of the IIS transmitters on FIFO underrun is to repeat the last sample Timing diagrams for IIS EIAJ mode are shown in Figure 17 5 and Figure 17 6 Data and word...

Page 311: ...bit fields Address MBAR2 0x20 Reset 0x3F00 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R TXSOURCE SELECT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5...

Page 312: ...ck sclk3 1001 IEC958 clock sclk4 0011 1 2 8 11 TX FIFO CONTROL 0 Normal operation 1 Reset to one sample remaining 1111 3 5 11 16 10 8 TXSOURCE SELECT 0 000 Digital zero 0 001 PDOR1 0 010 PDOR2 0 011 P...

Page 313: ...ansmitted the IEC958 transmit FIFO is not read any more by the IEC958 transmit hardware 7 PDOR1 PDOR2 PDOR3 Processor Data Out Register 8 Reprogramming bits 15 12 during functional operation is not al...

Page 314: ...that of the IIS transmitter The following functions are performed by the block 17 6 1 1 Audio Data Reception The IEC958 receive block 19 extracts the audio data from the stream and puts this in 20 bi...

Page 315: ...nel change Set when EBURcvCChannel register is updated The register is updated for every new C Channel received The exception is reset when EBURcvCChannel register is read EBU Illegal Symbol Set on re...

Page 316: ...r Channel and CD Subcode Over IEC958 Receiver The IEC958 receiver is capable of extracting the User Channel bits out of the data stream The extracted bits are assembled in the 32 bit UChannelReceive r...

Page 317: ...eceive and Q Channel Receive Registers Table 17 8 U Channel Receive and Q Channel Receive Registers Field Descriptions Field Description 31 0 UCHANNEL RECEIVE 1 AND 2 U channel receive register Contai...

Page 318: ...h the IEC958 receiver U channel reception is intended for reception of the following kind of data CD or CD compatible User channel subcode P Q and R W or Q and R W See the CD Red Book specification fo...

Page 319: ...y cause a change in data value which is not treated by this interface or it may cause a data symbol to be seen as a sync symbol or a sync symbol to be seen as a data symbol However not more than one o...

Page 320: ...1 11 Behavior of User Channel Receive Interface non CD data This section details the behavior of the user channel receive interface on incoming non CD data This mode is selected if UsyncMode bit 1 in...

Page 321: ...y Operation is guaranteed up to a maximum incoming transmit clock of 16MHz The mark space ratio of the transmit clock must be equal to or better than 38 62 17 6 2 4 Transmission of U Channel and CD Su...

Page 322: ...d with the CD Subcode data UChannelTxEmpty Register is empty needs re loaded UChannelTxUnderrun Under run error on register Table 17 13 UChannel Transmit Register Address Name Width Description Reset...

Page 323: ...llowed by 96 8 bit data symbols The boundaries of the 98 symbol packets are determined by free run counters The first symbol of any packet is transmitted with the special sync sequence on SFSY The fir...

Page 324: ...ill result in unpredictable undefined operation 17 6 4 Inserting CD User Channel Data Into IEC958 Transmit Data Source selection of data transmitted into the User Channel of the IEC958 transmitter is...

Page 325: ...1 2 Reset Value Access 0x34 0x38 0x3C 0x40 PDIR1 L 32 Processor data in Left Multiple address to read this register allows MOVEM instruction to read FIFO R 0x44 0x48 0x4C 0x50 PDIR3 L 32 Processor dat...

Page 326: ...ongword addresses are used to read data from the audio bus 0x34 0x38 0x3C 0x40 PDOR1 L 32 Processor data out 1 Left Multiple address to write this register allows MOVEM instruction to write FIFO undef...

Page 327: ...indication NOTE The DataInControl register bits 7 6 allow selection when FIFO full flag is set This is necessary due to polling It may be necessary to service the FIFO when it is less than completely...

Page 328: ...ull interrupt if at least 2 samples in FIFO 10 Full interrupt if at least 3 samples in FIFO 11 Full interrupt if at least 6 samples in FIFO 00 11 PDIR2 ZERO CONTROL 0 Normal operation 1 Always read ze...

Page 329: ...L6 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 L5 L4 L3 L2 L1 L0 0 0 0 0 0 0 0 0 0 0 Table 17 17 PDIR1 R PDIR3 R PDOR1 R PDOR2 R Formatting Bi...

Page 330: ...tten to the right half due to overrun Special hardware will make sure the next sample is not written to the left half of the FIFO If the overrun occurs on the left half of the FIFO the next sample is...

Page 331: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PDIR3 FIFO AUTO SYNC AUDIOTICK SOURCE EBU2 EXT EBU1 TX AUTO SYNC IIS2 FIFO AUTO SYNC PDIR2 FIFO AUTO SYNC PDIR1 FIFO AUTO SYNC AUDIO_TICK COUNT AUDIOTICK SOURCE W...

Page 332: ...very event 001 2 Interrupt for every 2 events 010 3 011 4 100 5 Other Reserved unused 000 11 2 0 AUDIO TICK SOURCE 0 000 Off 0 001 IIS1 Tx Right FIFO Read 0 010 IIS2 Tx Right FIFO Read 0 011 EBU Tx Ri...

Page 333: ...hould write data to the FIFO before underrun occurs Writing of data should be done using MOVE LONG or MOVEM instructions with long word oriented instructions When Empty is set and for example six samp...

Page 334: ...QChannelReceive register full read rcv reg 15 QChanOverrun QChannelReceive register overrun reg IntClear 14 UQChanSync U Q channel sync found reg IntClear 13 UQChanErr U Q channel framing error reg In...

Page 335: ...es data to them for the first time So during Step 2 of above mentioned start up procedure all transmit FIFO s are set in reset with one sample remaining They will stay in this state until the audio In...

Page 336: ...rface registers PDOR3 and PDIR2 are equipped with a CD ROM block encoder decoder The two interfaces are fully independent One control register is associated with the interface Address MBAR2 0xC8 Acces...

Page 337: ...ync sequence is found sector start is assumed to be one sector length 2352 bytes after the previous sector 3 CDROM descrambling scrambling control if required 4 Mode selection determines how the CRC i...

Page 338: ...new block noSync interrupt Set when the next longword to be read is the first word of new block and no valid sync pattern was found before the start of this new block in the stream ilSync interrupt S...

Page 339: ...ngword of the previous block This second detection mechanism builds in immunity for corrupted syncs Even if the sync is corrupted the block encoder will correctly find the start of the a new block 17...

Page 340: ...y when the IEC958 input is being used the CRIN clock requires trimming to match but this is only when the source is completely external to the application and when any audio output must be synchronous...

Page 341: ...io CRIN clock which is typically 16 93 MHz or 11 2896MHz Multiplexer 1 selects the incoming clock source Registers 2 3 and xor 4 are an edge detector Multiplexer 5 is a by pass for the IEC958 input Th...

Page 342: ...o additional filtering to push back the noise level on the phase 17 9 2 XTRIM Option Locking Xtal Clock to Incoming Signal The XTRIM output allows use of varicap controlled crystal See Figure 17 26 To...

Page 343: ...gic For XTRIM the internal circuit of the PDM modulator is used as shown in Figure 17 27 It is a first order pulse density modulator working from the system clock divided by 16 Figure 17 27 PDM Modula...

Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...

Page 345: ...Interface Features Compatibility with I2C Bus standard Multimaster operation Software programmable for one of 64 different serial clock frequencies Software selectable acknowledge bit Interrupt drive...

Page 346: ...many devices The flexible I2C allows additional devices to be connected to the bus for expansion and system development The interface operates up to 100 kbps with maximum bus loading and timing Operat...

Page 347: ...al clock line SCL for data transfer All devices connected to these two signals must have open drain or open collector outputs The logic AND function is exercised on both lines with external pullup res...

Page 348: ...wo slaves in the system can have the same address In addition if the I2C is master it must not transmit an address that is equal to its slave address The I2C cannot be master and slave at the same tim...

Page 349: ...e master can generate a START signal followed by a calling command without generating a STOP signal first This is called repeated START A STOP signal is defined as a low to high transition of SDA whil...

Page 350: ...the SCL line low after completion of one byte transfer 9 clocks In such cases it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line 18 4 9 Clock Str...

Page 351: ...r MBCR MBAR 28C I2C Status Register MBSR MBAR 290 I2 C Data I O Register MBDR MBAR2 440 MBAR2 I2 C Address Register MADR2 MBAR2 444 MBAR2 I2 C Frequency Divider Register MFDR2 MBAR2 448 MBAR2 I2 C Con...

Page 352: ...Rate This field is used to prescale the clock for bit rate selection Due to the potential slow rise and fall times of the SCL and SDA signals bus signals are sampled at the prescaler frequency The ser...

Page 353: ...13 480 33 256 14 576 34 320 15 640 35 384 16 768 36 448 17 960 37 512 18 1152 38 640 19 1280 39 768 1A 1536 3A 896 1B 1920 3B 1024 1C 2304 3C 1280 1D 2560 3D 1536 1E 3072 3E 1792 1F 3840 3F 2048 Addr...

Page 354: ...ntly pending interrupt condition 5 MSTA At reset the Master Slave Mode Select Bit is cleared When this bit is changed from 0 to 1 a START signal is generated on the bus and the master mode is selected...

Page 355: ...s detected the IBB is set If a STOP signal is detected it is cleared 1 Bus is busy 0 Bus is idle 4 IAL Hardware sets the Arbitration Lost bit IAL when the arbitration procedure is lost Arbitration is...

Page 356: ...ol Register MBCR to enable the I2C bus interface system 4 Modify the MBCR to select master slave mode transmit receive mode and interrupt enable or not 1 IIF The I2 C Interrupt IIF bit is set when an...

Page 357: ...e sent The data written to the data register comprises the address of the desired slave and the LSB is set to indicate the direction of transfer required The bus free time i e the time between a STOP...

Page 358: ...uent transfer and the MTX bit is programmed accordingly For slave mode data cycles IAAS 0 the SRW bit is not valid The MTX bit in the control register should be read to determine the direction of the...

Page 359: ...first generating a STOP signal A program example follows RESTART MOVE B MBCR A7 Another START RESTART BSET B 2 A7 MOVE B A7 MBCR MOVE B CALLING A7 Transmit the calling address D0 R W MOVE B CALLING A7...

Page 360: ...the byte during which arbitration was lost An interrupt occurs at the falling edge of the ninth clock of this transfer with IAL 1 and MSTA 0 If one master tries to transmit or do a START while the bus...

Page 361: ...ad From MBDR Generate Stop Signal Read Data From MBDR And Store Set TXAK 1 Generate Stop Signal 2nd Last Byte To Be Last Byte To Be Arbitration Lost Clear IAL IAAS 1 IAAS 1 SRW 1 TX RX Set Tx Mode Wri...

Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...

Page 363: ...allow operation with the following crystal or external clock frequencies 5 5 6448 8 4672 10 11 2896 16 9344 20 and 33 8688 MHz 19 1 1 Boot Modes The MCF5253 can be booted in one of three modes Extern...

Page 364: ...0000 length 0x10000000 mbar2 origin 0xc0000000 length 0x40000000 sram1 origin 0x10000000 length 0x00010000 sram0 origin 0x10010000 length 0x00010000 19 2 1 2 Internal SRAM usage The boot ROM data resi...

Page 365: ...KB validate move l d0 CSMR0 move l 0x0580 d0 port size 16 bit AA 1WS move l d0 CSCR0 move l ___SP_INIT sp move w 0x2000 SR enable interrupts jsr _main bra loop in case main returns 19 2 2 Boot Type De...

Page 366: ...to registers through the boot loader The following tables describe the encoding of the command and size bits 19 2 3 1 Command Encoding Size Encoding The destination address is the base address for the...

Page 367: ...cord has been loaded into memory The CRC allows the boot record to be validated before attempting to begin code execution The length of the boot record is described in number of sectors 512 bytes it o...

Page 368: ...0x 19 2 5 3 Boot from UART In UART mode the MCF5253 acts as a slave device and receives data over UART1 TXD1 and RXD1 UART configuration Baud rate 19200 9600 4800 baud Xtal 33 8688 16 9344 8 4672 MHz...

Page 369: ...des typically at least two boot record headers must be added to the raw binary file generated by the user code The first must be at the start of the file and should be a Store Immediate header with an...

Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...

Page 371: ...nts are backward compatible with the original ColdFire debug definition The general topic of debug support is divided into three separate areas 1 Real Time Trace Support 2 Background Debug Mode BDM 3...

Page 372: ...dated each processor cycle 20 1 3 Development Serial Clock DSCLK This input signal is synchronized internally and provides the clock for the serial communication port to the debug module The maximum f...

Page 373: ...inition of the dynamic execution path The ColdFire solution is to include a parallel output port providing encoded processor status and data to an external development system This port is partitioned...

Page 374: ...cution speed of the ColdFire processor is affected only when both storage elements contain valid data waiting to be dumped onto the DDATA port In this case the processor core is stalled until one FIFO...

Page 375: ...ints to a unique case within the structure For these types of change of flow operations the ColdFire processor uses the debug pins to output a sequence of information on successive processor clock cyc...

Page 376: ...ion Processing PST D This encoding is displayed during emulation mode debug interrupt or optionally trace Because this encoding defines a multicycle mode the PST outputs are driven with this value unt...

Page 377: ...ext sample point See Section 20 4 1 Theory of Operation for more detail 3 The execution of the HALT ColdFire instruction immediately suspends execution By default this is a supervisor instruction and...

Page 378: ...unrestricted commands to the debug module The debug module implements a synchronous protocol using a three pin interface development serial clock DSCLK development serial input DSI and development se...

Page 379: ...esponse try again 1 0001 Error terminated bus cycle data invalid 1 FFFF Illegal command Table 20 3 Receive BDM Packet Register Field Descriptions Field Description 16 S Status The status bit indicates...

Page 380: ...specified by the longword address Steal 1800 byte 1840 wd 1880 long 20 3 4 1 4 20 16 DUMP MEMORY BLOCK DUMP Used with the READ command to dump large blocks of memory An initial READ is executed to se...

Page 381: ...ment system Operand Size For sized operations this field specifies the operand data size All addresses are expressed as 32 bit absolute values The size field is encoded as listed in Table 20 7 Address...

Page 382: ...se unless the received command was decoded as unimplemented in which case the response data is the illegal command encoding If an illegal command response occurs the development system should retransm...

Page 383: ...contain detailed descriptions of each command NOTE The BDM status bit S is zero for normally completed commands while illegal commands not ready responses and bus error transfers return a logic one in...

Page 384: ...pplied most significant word first Result Data Command complete status is indicated by returning the data FFFF with the status bit cleared when the register write is complete 20 3 4 1 3 Read Memory Lo...

Page 385: ...Background Debug Mode BDM Interface MCF5253 Reference Manual Rev 1 Freescale Semiconductor 20 15 Figure 20 11 WAREG WDREG Command Format Figure 20 12 READ Command Result Format...

Page 386: ...error occurs 20 3 4 1 4 Write Memory Location WRITE The WRITE command writes the operand data to the memory location specified by the longword address The address space is defined by the contents of...

Page 387: ...he data FFFF with the status bit cleared when the register write is complete A value of 0001 with the status bit set is returned if a bus error occurs 20 3 4 1 5 Dump Memory Block DUMP DUMP is used in...

Page 388: ...s in the temporary register NOTE The DUMP command does not check for a valid address DUMP is a valid command only when preceded by another DUMP NOP or by a READ command Otherwise an illegal command re...

Page 389: ...first operand The FILL command writes subsequent operands The initial address is incremented by the operand size 1 2 or 4 and saved in a temporary register after the memory write Subsequent FILL comma...

Page 390: ...9 8 7 6 5 4 3 2 1 0 1 C 0 0 X X X X X X X X DATA 7 0 Table 20 10 Word FILL Command 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 C 4 0 DATA 15 0 Table 20 11 Long FILL Command 15 14 13 12 11 10 9 8 7 6 5 4...

Page 391: ...peline before resuming normal instruction execution Prefetching begins at the current PC and current privilege level If any register For example the PC or SR was altered by a BDM command while halted...

Page 392: ...ively form a 32 bit address used by the debug module to generate a special bus cycle to access the specified control register The 12 bit Rc field is the same as that used by the MOVEC instruction Figu...

Page 393: ...struction The first long operand selects the register to which the operand data is to be written The second operand is the data Result Data Successful write operations return a FFFF Bus errors on the...

Page 394: ...e selected debug register are returned as a longword value The data is returned most significant word first 20 3 4 1 12 Write Debug Module Register WDMREG The operand longword data is written to the s...

Page 395: ...mand response 20 3 4 2 BDM Accesses of the eMAC Registers The presence of rounding logic in the output data path of the eMAC requires special care for BDM initiated reads and writes of its programming...

Page 396: ...Data The single operand is the 32 bit Rc control register select field Result Data The contents of the selected control register are returned as a longword value The data is returned most significant...

Page 397: ...oints the processor may have executed several additional instructions As a result trigger reporting is considered imprecise If the processor core cannot be halted the special debug interrupt can be us...

Page 398: ...ere the execution of the first instruction occurs before another trace exception is generated This Rev A enhancement disables all hardware breakpoints until the first instruction after the RTE has com...

Page 399: ...of bits in the implementation The registers known as the debug control registers are accessed through the BDM port using two new BDM commands WDMREG and RDMREG These commands contain a 4 bit field DRc...

Page 400: ...REG commands The ABLR is accessible in supervisor mode as debug control register D using the WDEBUG instruction and through the BDM port using the WDMREG commands The ABHR is overwritten by the BDM ha...

Page 401: ...S 31 0 Reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W ADDRESS 31 0 Reset Figure 20 30 Address Breakpoint High Register ABHR Access User write only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W RM SZM TTM...

Page 402: ...rocessor Access 01 Reserved 10 Emulator Mode Access 11 Acknowledge CPU Space Access These bits also define the TT encoding for BDM memory commands In this case the 01 encoding generates an alternate m...

Page 403: ...y the DBMR value allowing only those bits in DBR that have a corresponding zero in DBMR to be compared with the data value from the processor s local bus as defined in the TDR The DBR is accessible in...

Page 404: ...ternal data bus A one causes that bit to be ignored The data breakpoint register supports both aligned and misaligned references The relationship between the processor address the access size and the...

Page 405: ...Byte Data 7 0 0x Word Data 31 16 1x Word Data 15 0 xx Long Data 31 0 Access User write only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R W TRC EDLW EDWL EDWU EDLL EDLM EDUM EDUU DI EAI EAR EAL EP...

Page 406: ...ord of the processor s local data bus 24 8 EDLM If set the Enable Data Breakpoint for the Lower Middle Data Byte bit enables the data breakpoint trigger based on the high order byte of the low order w...

Page 407: ...o BDM This bit is cleared by reading CSR 25 HALT If the read only Processor Halt status bit is set the processor has executed the HALT instruction and forced entry into BDM This bit is cleared by read...

Page 408: ...ervisor only instruction 1 HALT is a non privileged supervisor user instruction 9 8 BTB The 2 bit Branch Target Bytes field defines the number of bytes of branch target address to be displayed on the...

Page 409: ...any pending interrupt requests signalled while executing in single instruction step mode 4 SSM If set the Single Step Mode bit forces the processor core to operate in a single instruction step mode Wh...

Page 410: ...re interlocks so Freescale recommends that the TDR be disabled while the breakpoint registers are being loaded At the conclusion of this process the TDR can be written to define the exact trigger This...

Page 411: ...iance enable pin 21 1 Features The MCF5253 JTAG implementation can do the following Perform boundary scan operations to test circuit board electrical continuity Bypass the MCF5253 by reducing the shif...

Page 412: ...G Test Access Port signals TCK TMS TDI TDO TRST are interpreted as the debug port pins Table 21 1 JTAG Pin Descriptions Pin Description TCK A test clock input that synchronizes test logic operations T...

Page 413: ...its value will default to a logic level of 1 However if TRST is not used it can either be tied to ground or if TCK is clocked it can be tied to VDD The former connection will place the JTAG controlle...

Page 414: ...This pin also provides the single bit communication for the debug module commands 21 3 5 Test Data Output Development Serial Output TDO DSO This is a dual function pin When TEST 2 0 001 then DSO is s...

Page 415: ...GIC RESET TLR RUN TEST IDLE RTI SELECT DR SCAN SeDR CAPTURE IR UPDATE IR EXIT2 IR PAUSE IR EXIT1 IR SHIFT IR CAPTURE DR UPDATE DR EXIT2 DR PAUSE DR EXIT1 DR SHIFT DR 0 0 0 1 0 1 1 0 0 0 1 1 0 1 1 1 1...

Page 416: ...ixed values with the SAMPLE PRELOAD instruction and held in the boundary scan update registers The EXTEST instruction can also configure the direction of bidirectional pins and establish high impedanc...

Page 417: ...ent in the instruction register Users can observe this sampled data by shifting it through the boundary scan register to the output TDO by using the shift DR state Both the data capture and the shift...

Page 418: ...BYPASS instruction goes active on the falling edge of TCK in the update IR state when the data held in the instruction shift register is equivalent to 0xF 21 5 2 ID Code Register An IEEE 1149 1A compl...

Page 419: ...conjunction with system functional logic that uses both clocks must have coordination and synchronization of these clocks done externally to the MCF5253 21 7 Disabling IEEE 1149 1A Standard Operation...

Page 420: ...While in JTAG mode input pins TDI DSI TMS BKPT and TRST DSCLK have internal pullups enabled Figure 21 5 shows pin values recommended for disabling JTAG with the MCF5253 in debug mode Figure 21 5 Disab...

Page 421: ...ster MISCCR Table 22 1 Real Time Clock Memory Map MBAR2 Offset Register Access Reset Value Section Page 0x500 Miscellaneous Configuration Register MISCCR R W Undefined 22 2 1 22 1 0x504 ATA DMA Source...

Page 422: ...lock power loss To clear this bit set the RTCCLR bit and then clear the RTCCLR bit 0 RTC maintaining time OK 1 Power lost to RTC 7 RTCCLR Real time clock power loss clear 0 No action 1 Clears the RTCP...

Page 423: ...dress Register ATA_DADDR Table 22 3 ATA DMA Address Register ATA_DADDR Field Descriptions Field Description 31 18 RAMADDR DMA address on the RAM side of the bus 17 16 Reserved should be cleared 15 2 A...

Page 424: ...1 0 R CAN CLK USB CLK W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Figure 22 4 USB FlexCAN Clock Register USBCANCLK Table 22 5 USB FlexCAN Clock Register USBCANCLK Field Des...

Page 425: ...ry is visible from the CPU in straight endianess and in swapped endianness mode 22 3 1 2 DMA Transfer between ATA and Cache RAM The DMA of the ATA block can be used to transfer data between the ATA mo...

Page 426: ...ol bit Set this bit for ATA to RAM transfers clear it for RAM to ATA transfers 7 Enable the DMA interrupt if wanted 8 Allow the transfer to start by setting the MISCCR ATDA bit 9 Start the ATA transfe...

Page 427: ...interfaces with the ATA device over a number of ATA signals 23 1 Features The ATA interface includes the following features Programmable timing on the ATA bus Works with wide range of bus frequencies...

Page 428: ...he interface Before accessing the ATA bus the host must program the timing parameters to be used on the ATA bus The timing parameters control the timing on the ATA bus Most timing parameters are progr...

Page 429: ...requests the smart DMA to take steps to complete the transfer transfer the bytes remaining in the FIFO to the host memory and inform the host CPU the transfer is completed All transfers between FIFO...

Page 430: ...packet sizes can be handled too 23 4 External Signal Description See Table 23 1 for the list of signals entering and exiting this module to peripherals within the device 23 4 1 Detailed Signal Descri...

Page 431: ...All five lines follow the same timing 23 4 1 5 ATA_DMARQ In This signal is the ATA bus device DMA request It is pulled high by the device if it wants to transfer data using multiword DMA or ultra DMA...

Page 432: ...timing equations some timing parameters are used These parameters depend on the implementation of the ATA interface on silicon the bus buffer used the cable delay and cable skew Refer to Table 23 2 fo...

Page 433: ...A_CS1 ATA_A2 ATA_A1 ATA_A0 ATA_Dx write cable tskew6 Max difference in cable propagation delay without accounting for ground bounce cable Table 23 3 Timing Parameters PIO Read ATA Parameter PIO Read M...

Page 434: ...PIO Write ATA Parameter PIO Write Mode Timing Parameter1 1 See Figure 23 3 Value How to meet t1 t1 t1 min time_1 T tskew1 tskew2 tskew5 time_1 t2 t2w t2 min time_2w T tskew1 tskew2 tskew5 time_2w t9...

Page 435: ...e Table 23 5 Timing Parameters MDMA Read and Write ATA Parameter MDMA Read TIming1 and MDMA Write TIming2 Value How to Meet tm ti tm tm min ti min time_m T tskew1 tskew2 tskew5 time_m td td td1 td1 mi...

Page 436: ...tart Timing Diagram Figure 23 7 shows timing for host terminating UDMA in transfer tf write tf min write time_k T tskew1 tskew2 tskew6 time_k tL tL max time_d time_k 2 T tsu tco 2 tbuf 2 tcable2 time_...

Page 437: ...e Manual Rev 1 Freescale Semiconductor 23 11 Figure 23 7 UDMA in Host Terminates Transfer Figure 23 8 shows timing for device terminating UDMA in transfer Figure 23 8 UDMA in Device Terminates Transfe...

Page 438: ...tskew3 ti_ds 0 tskew3 ti_ds ti_dh should be low enough tdh tdh1 tdh tskew3 ti_dh 0 tcyc tc1 tcyc tskew TBD T T big enough trp trp trp min time_rp T tskew1 tskew2 tskew6 time_rp tx11 1 There is a speci...

Page 439: ...al Rev 1 Freescale Semiconductor 23 13 Figure 23 9 UDMA Out Transfer Start Timing Diagram Figure 23 10 shows timing for host terminating UDMA out transfer Figure 23 10 UDMA Out Host Terminates Transfe...

Page 440: ...t tack tack tack min time_ack T tskew1 tskew2 time_ack tenv tenv tenv min time_env T tskew1 tskew2 tenv max time_env T tskew1 tskew2 time_env tdvs tdvs tdvs time_dvs T tskew1 tskew2 time_dvs tdvh tdvh...

Page 441: ...2 2 8 23 21 MBAR2 0x808 TIME_9 TIME_9 PIO timing parameter Controls t9 R W 0x01 23 5 2 2 9 23 21 MBAR2 0x809 TIME_M TIME_M MDMA timing parameter Controls tm R W 0x01 23 5 2 2 10 23 22 Address TIME_JN...

Page 442: ...A Drive data register 16 bit RW 23 5 2 7 23 32 MBAR2 0x8A4 DRIVE_FEATURES DRIVE_FEATURES Drive features register R W 23 5 2 7 23 32 MBAR2 0x8A8 DRIVE_SECTOR_COUN T DRIVE_SECTOR_ COUNT Drive sector cou...

Page 443: ...4 R TIME_4 7 0 W MBAR2 0x808 TIME_9 R TIME_9 7 0 W MBAR2 0x809 TIME_M R TIME_M 7 0 W Address R TIME_JN 7 0 W Address R TIME_D 7 0 W Address R TIME_K 7 0 W MBAR2 0x80D TIME_ACK R TIME_ACK 7 0 W Address...

Page 444: ...R TIME_CYC 7 0 fifo_data 15 0 W Name 7 6 5 4 3 2 1 0 Address R FIFO_FILL 7 0 W Address R fifo_rst_ b ata_rst_ b fifo_tx_ en fifo_rcv _en dma_ pending dma_ult ra_se lected dma_ write iordy_ en W Addres...

Page 445: ...ations Section 23 4 3 2 PIO Mode Timing Section 23 4 3 3 Timing in Multiword DMA Mode Section 23 4 3 4 UDMA In Timing Diagrams Section 23 4 3 5 UDMA Out Timing Diagrams Every timing parameter is 8 bit...

Page 446: ...for illustration of valid bits in the TIME_2R Register and Table 23 8 for description of the bit fields Address MBAR2 0x801 TIME_ON Access User read write 7 6 5 4 3 2 1 0 R TIME_ON 7 0 W Reset 0 0 0...

Page 447: ...r illustration of valid bits in the TIME_4 Register and Table 23 8 for description of the bit fields 23 5 2 2 9 TIME_9 Register See Figure 23 20 for illustration of valid bits in the TIME_9 Register a...

Page 448: ...e 23 23 for illustration of valid bits in the TIME_D Register and Table 23 8 for description of the bit fields Address MBAR2 0x808 TIME_9 Access User read write 7 6 5 4 3 2 1 0 R TIME_9 7 0 W Reset 0...

Page 449: ...llustration of valid bits in the TIME_ENV Register and Table 23 8 for description of the bit fields 23 5 2 2 16 TIME_RPX Register See Figure 23 27 for illustration of valid bits in the TIME_RPX Regist...

Page 450: ...for illustration of valid bits in the TIME_DVH Register and Table 23 8 for description of the bit fields Address MBAR2 0x80F TIME_RPX Access User read write 7 6 5 4 3 2 1 0 R TIME_RPX 7 0 W Reset 0 0...

Page 451: ...llustration of valid bits in the TIME_CVH Register and Table 23 8 for description of the bit fields 23 5 2 2 23 TIME_SS Register See Figure 23 34 for illustration of valid bits in the TIME_SS Register...

Page 452: ...iption of the bit fields 23 5 2 3 2 FIFO_Data Register in 32 Bit Mode See Figure 23 37 for illustration of valid bits in the FIFO_Data Register in 32 bit Mode and Table 23 8 for description of the bit...

Page 453: ...tion of valid bits in the FIFO_FILL Register and Table 23 8 for description of the bit fields FIFO_FILL is a read only register Any read to it returns the current number of halfwords present in the FI...

Page 454: ...d the FIFO will request the DMA to refill it whenever FIFO filling drops below the alarm level 0 FIFO refill by DMA disabled 1 FIFO refill by DMA enabled 4 fifo_rcv_en FIFO receive enable This bit con...

Page 455: ...terrupt Pending Register Field Description Field Description 7 ata_intrq1 ATA interrupt request 1 This bit reflects the value of the ATA_INTRQ interrupt input It is set in the interrupt pending regist...

Page 456: ...is set in the interrupt pending register and the same bit is set in the interrupt enable register fifo_txfer_end_alarm will be asserted signalling the DMA the end of the transfer The interrupt clear r...

Page 457: ...itted N A Address MBAR2 0x830 INTERRUPT_CLEAR Access User write only 7 6 5 4 3 2 1 0 R W fifo_underflow fifo_overflow Reset Figure 23 42 Interrupt_Clear Register Table 23 13 Interrupt Clear Register F...

Page 458: ...ister 23 6 Functional Description The ATA interface provides two ways to communicate with the ATA peripherals connected to the ATA bus Address MBAR2 0x834 FIFO_ALARM Access User read write 7 6 5 4 3 2...

Page 459: ...ming parameters If dma_pending was 1 before the reprogramming started it should be set again after new timing is in effect to allow the drive to finish the current DMA transfer It only makes sense to...

Page 460: ...e fifo_rcv_alarm is high the DMA should read packetsize long ints from the FIFO and store them to main memory typical packetsize is 8 longs 4 Write 2 packetsize to fifo_alarm register In this way FIFO...

Page 461: ...m FIFO to drive running The steps for setting up a DMA data transfer from device to host are 1 Make sure the ATA bus is not in reset and all timing registers are programmed 2 Make sure the FIFO is emp...

Page 462: ...fer will start Data is transferred automatically from the FIFO and also from host memory to FIFO 8 During the transfer the host can monitor for end of transfer by reading some device ATA registers The...

Page 463: ...y time without notice The USB interface implements many industry standards However it is beyond the scope of this document to document the intricacies of these standards Instead it is left to the read...

Page 464: ...Figure 24 1 USB Interface Block Diagram 24 3 Overview The module is a USB 2 0 compliant serial interface engine for implementing a USB interface The registers and data structures are based on the Enha...

Page 465: ...he USB interface signals Table 24 1 describes the external signals functionality of the USB interface 24 5 1 On Chip Transceiver The On Chip transceiver is a UTMI specification compliant transceiver I...

Page 466: ...F TX buffer hardware parameters R 0x8004_0604 24 6 1 5 24 9 MBAR2 0x614 HWRXBUF RX buffer hardware parameters R 0x0000_0504 24 6 1 6 24 10 MBAR2 0x703 CAPLENGTH Capability Length Register R 0x40 24 6...

Page 467: ...D register MBAR2 0x784 PORTSC Port Status and Control register R W 0x1c00_0004 24 6 3 13 24 29 MBAR2 0x7a4 OTGSC On The Go Status and Control R W 0x0000_0020 24 6 3 14 24 34 MBAR2 0x7a8 USBMODE USB De...

Page 468: ...19 18 17 16 R REVISION W Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R NID ID W Reset 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1 Figure 24 2 ID Register Table 24 3 ID Register Fi...

Page 469: ...0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SM PHYM PHYW BWT CLKC RT W Reset 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 Figure 24 3 HWGENERAL Register Table 24 4 HWGENERAL Register Field D...

Page 470: ...n Address MBAR2 0x608 Access User read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R TTPER TTASY W Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R NPORT HC W Reset 0...

Page 471: ...18 17 16 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DEVEP DC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 Figure 24 5 HWDEVICE Register Table 24 6 HWDEVICE Register F...

Page 472: ...Always 0x4 15 8 TXADD Transmit address The number of address bits for the entire TX buffer Always 0x6 7 0 TXBURST Transmit burst Indicates the number of data beats in a burst for transmit DMA data tr...

Page 473: ...byte register containing a BCD encoding of the EHCI revision number supported by this host controller The most significant byte of the register represents a major revision and the least significant by...

Page 474: ...is field indicates the number of embedded transaction translators associated the module This field is always 1 23 20 N_PTT Ports per transaction translator This is a non EHCI field EHCI defines this f...

Page 475: ...here the software can reliably update the isochronous schedule When bit 7 is zero the value of the least significant 3 bits indicates the number of microframes a host controller can hold a set of isoc...

Page 476: ...n the EHCI specification This register describes the overall host device capability of the USB OTG module Figure 24 13 shows the DCCPARAMS register Table 24 14 provides bit descriptions for the DCCPAR...

Page 477: ...on 31 9 Reserved 8 HC Host Capable Always 1 indicating the controller can operate as an EHCI compatible USB 2 0 host 7 DC Device Capable Always 1 indicating the controller can operate as an USB 2 0 de...

Page 478: ...on the use of this bit is described in Section 24 12 2 Device Operation of this manual 12 Reserved 11 ASPE Asynchronous Schedule Park Mode Enable This bit defaults to a 0 and is R W The software uses...

Page 479: ...ernal pipelines timers counters state machines etc to their initial value Any transaction currently in progress on USB is immediately terminated A USB reset is not driven on downstream ports The softw...

Page 480: ...or enable the Asynchronous Schedule when the software transitions the Asynchronous Schedule Enable bit in the USBCMD register When this bit and the Asynchronous Schedule Enable bit are the same value...

Page 481: ...Interrupt on Async Advance Doorbell bit in the USBCMD register This status bit indicates the assertion of that interrupt source Used only in host mode 1 Async advance interrupt 0 No async advance int...

Page 482: ...Error detected 0 No error 0 UI USBINT USB Interrupt USBINT This bit is set by the controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor TD has a...

Page 483: ...errupt threshold The interrupt is acknowledged by the software clearing the Interrupt on Async Advance bit Only used in host mode 1 Enable 0 Disable 4 SEE System Error Enable When this bit is a one an...

Page 484: ...N based on the value of the Frame List Size in the USBCMD register when used in host mode Address MBAR2 0x74C Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R W Reset 0 0 0 0...

Page 485: ...shared between the host and device mode functions In host mode it is the PERIODICLISTBASE register in device mode it is the DEVICEADDR register See Section 24 6 3 7 Device Address Register DEVICEADDR...

Page 486: ...st Address Register ASYNCLISTADDR This 32 bit register contains the address of the next asynchronous queue head to be executed by the host Bits 4 0 of this register cannot be modified by the system so...

Page 487: ...ue head should be 2 Kbyte aligned This register is shared between the host and device mode functions In device mode it is the ENDPOINTLISTADDR register in host mode it is the ASYNCLISTADDR register Se...

Page 488: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R EPBASE con t W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24 21 Endpoint List Address ENDPOINTLISTADDR Register Table 24 23 E...

Page 489: ...so it proceeds to pre fill the TX FIFO If at anytime during the pre fill operation the time remaining the micro frame is Ts then the packet attempt ceases and the packet is tried at a later time Alth...

Page 490: ...of time to send the packet before the next Start Of Frame This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH Writing to this register clear...

Page 491: ...he software applies power to the port by setting port power to one For the module in device mode the controller does not support power control Port control in device mode is used only for status port...

Page 492: ...Reserved This bit is not defined in the EHCI specification 29 Reserved 28 PTW Parallel Transceiver Width This register bit is used to control the data bus width of the parallel transceiver interface...

Page 493: ...o if Port Power PP is zero or in device mode This bit is OTG host mode only for use by an external power control circuit 19 16 PTC Port Test Control Any other value than zero indicates that the port i...

Page 494: ...Port Power PP is zero 7 SUSP Suspend In host mode The Port Enabled bit PE and Suspend SUSP bit define the port states as follows 0x Disable 10 Enable 11 Suspend When in suspend state downstream propag...

Page 495: ...if a J to K transition is detected while the port is in the Suspend state The bit will be cleared when the device returns to normal operation Also when this bit transitions to a one because a J to K t...

Page 496: ...software has not cleared an existing connect status change For example the insertion status changes twice before the system software has cleared the changed condition hub hardware will be setting an...

Page 497: ...cription 31 Reserved 30 DPIE Data Pulse Interrupt Enable 1 Enable 0 Disable 29 1msE 1 millisecond timer Interrupt Enable 1 Enable 0 Disable 28 BSEIE B Session End Interrupt Enable 1 Enable 0 Disable 2...

Page 498: ...tus This bit is set when a change on the ID input has been detected The software must write a one to clear this bit 15 Reserved 14 DPS Data Bus Pulsing Status 1 Pulsing detected on port 0 No pulsing o...

Page 499: ...able pulldown on DN 2 HAAR Hardware assist auto reset 0 Disabled 1 Enable automatic reset after connect on host port 1 VC VBUS Charge Setting this bit causes the VBus line to be charged This is used f...

Page 500: ...X and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns underruns in bandwidth limited systems Note In High Speed Mode all...

Page 501: ...DPTSETUPSTAT Register Field Descriptions Field Description 31 4 Reserved 3 0 ENDPTSETUPSTAT Setup Endpoint Status For every setup transaction that is received a corresponding bit in this register is s...

Page 502: ...e buffer For each endpoint a corresponding bit is used to request a buffer prepare for a receive operation in order to respond to a USB OUT transaction The software should write a one to the correspon...

Page 503: ...PRIME register There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready This delay time varies based upon the current USB traffic and the number of b...

Page 504: ...ete ENDPTCOMPLETE Register Field Descriptions Field Description 31 20 Reserved 19 16 ETCE Endpoint transmit complete event Each bit indicates a transmit event IN INTERRUPT occurred and the software sh...

Page 505: ...ontrol endpoint 00 17 Reserved 16 TXS TX Endpoint Stall The software can write a one to this bit to force the endpoint to return a STALL handshake to the Host It will continue returning STALL until th...

Page 506: ...s Field Description 31 24 Reserved 23 TXE TX endpoint enable 1 Enabled 0 Disabled 22 TXR TX data toggle reset Whenever a configuration event is received for this Endpoint the software must write a one...

Page 507: ...d for this Endpoint the software must write a one to this bit in order to synchronize the data PID s between the Host and device 5 RXI RX data toggle inhibit This bit is used for test only and should...

Page 508: ...e active endpoints in the system In host mode the module uses a 256 byte TX buffer and a 128 byte RX buffer Device operation uses a single 128 byte RX buffer and a 64 byte TX buffer for each endpoint...

Page 509: ...ization Split transaction Interrupt Bulk and Control are also managed using queue heads and queue element transfer descriptors The periodic frame list is a 4K page aligned array of Frame List Link poi...

Page 510: ...the exact type of data structure being referenced by this pointer The value encodings for the Typ field are given in Table 24 37 24 8 2 Asynchronous List Queue Head Pointer The Asynchronous Transfer L...

Page 511: ...tatus1 Transaction 2 Length1 ioc PG2 Transaction 2 Offset2 0x0C Status1 Transaction 3 Length1 ioc PG2 Transaction 3 Offset2 0x10 Status1 Transaction 4 Length1 ioc PG2 Transaction 4 Offset2 0x14 Status...

Page 512: ...ted with this descriptor is completed the Host Controller sets this bit to zero indicating that a transaction for this element should not be executed when it is next encountered in the schedule 30 Dat...

Page 513: ...ffer page pointer indicated in the adjacent PG field to produce the starting buffer address for this transaction Table 24 40 Buffer Pointer Page 0 Plus Bit Name Description 31 12 Buffer Pointer Page 0...

Page 514: ...per micro frame The valid values are 00 Reserved A zero in this field yields undefined results 01 One transaction to be issued for this endpoint per micro frame 10 Two transactions to be issued for th...

Page 515: ...encodings are 00 iTD isochronous transfer descriptor 01 QH queue head 10 siTD split transaction isochronous transfer descriptor 11 FSTN frame span traversal node 0 T Terminate 0 Link Pointer is valid...

Page 516: ...es the value of the three low order bits of the FRINDEX register to index into this bit field If the FRINDEX register value indexes to a position where the Frame S mask field is a one then this siTD i...

Page 517: ...s detected during the transaction generated by this descriptor 3 Transaction Error XactErr Set by the Host Controller during status update in the case where the host did not receive a valid response f...

Page 518: ...fer Pointer Page 1 Plus Bit Name Description 31 12 Buffer Pointer Page 1 Bits 31 12 is a 4K page aligned physical memory addresses These bits correspond to physical address bits 31 12 respectively The...

Page 519: ...Current Offset1 0x0C Buffer Pointer Page 1 0000_0000_0000 0x10 Buffer Pointer Page 2 0000_0000_0000 0x14 Buffer Pointer Page 3 0000_0000_0000 0x18 Buffer Pointer Page 4 0000_0000_0000 0x1C Figure 24 4...

Page 520: ...n only on the successful completion of the transaction The maximum value the software may store in this field is 5 4K 0x5000 This is the maximum number of bytes 5 page pointers can access If the value...

Page 521: ...program Cerr to a value of zero when the EPS field is programmed with a value indicating a Full or Low speed device This combination could result in undefined behavior Stalled No Detection of Babble o...

Page 522: ...troller during status update in the case where the host did not receive a valid response from the device time out CRC bad PID If the host controller sets this bit to a one then it remains a one for th...

Page 523: ...nsaction via the new buffer pointer 11 0 Current Offset Page 0 Pages 1 4 This field is reserved in all pointers except the first one that is Page 0 The host controller should ignore all reserved bits...

Page 524: ...nterrupt via split transactions to USB2 0 Hub Transaction Translator There are additional fields used for addressing the hub and scheduling the protocol transactions for periodic The host controller m...

Page 525: ...nt number on the device serving as the data source or sink 7 I Inactivate on next transaction This bit is used by the system software to request that the host controller set the Active bit to zero Thi...

Page 526: ...action When the criteria for using this field are met a zero value in this field has undefined behavior This field is used by the host controller to match against the three low order bits of the FRIND...

Page 527: ...ults in a Nak or Nyet response This counter is reloaded from RL before a transaction is executed during the first pass of the reclamation list relative to an Asynchronous List Restart condition It is...

Page 528: ...nds to memory address signals 31 5 respectively 4 3 Reserved These bits must be written as 0s 2 1 Typ This field indicates to the host controller whether the item referenced is a iTD siTD a QH or an F...

Page 529: ...l of the interface data structures are allocated 6 Write the appropriate value to the USBINTR register to enable the appropriate interrupts 7 Write the base address of the Periodic Frame List to the P...

Page 530: ...functionality of these bits is specified in the USB Specification Revision 2 0 In this implementation however over current is not reported to the USB core Therefore the bits Over current Active and Ov...

Page 531: ...signaling down the port The system software times the duration of the resume nominally 20 milliseconds then clears the Force Port Resume bit When the host controller receives the write to transition F...

Page 532: ...sume K State received No Effect N A N A Port suspended Resume K State received Resume reflected downstream on signaled port Force Port Resume status bit in PORTSC register is set Port Change Detect bi...

Page 533: ...schedule and transitions immediately to traversing the asynchronous schedule Once this transition is made the host controller executes from the asynchronous schedule until the end of the micro frame...

Page 534: ...minates the beginning of frame and frame wrap scheduling boundary conditions The implementation of this phase shift requires that the host controller use one register value for accessing the periodic...

Page 535: ...actions execute on the high speed bus at exactly the right time for the USB 2 0 hub periodic pipeline As described in Section 24 6 3 4 Frame Index Register FRINDEX the SOF Value can be implemented as...

Page 536: ...ter The software then can poll the Periodic Schedule Status bit to determine when the periodic schedule has made the desired transition The software must not modify the Periodic Schedule Enable bit un...

Page 537: ...mum packet size and high bandwidth multiplier 24 9 8 1 Host Controller Operational Model for iTDs The host controller uses FRINDEX register bits 12 3 to index into the periodic frame list This means t...

Page 538: ...rame In other words the Mult field represents a transaction count for the endpoint in the current micro frame If the Mult field is zero the operation of the host controller is undefined The transfer d...

Page 539: ...st use more than one iTD Figure 24 48 illustrates the simple model of how a client buffer is mapped by the system software to the periodic schedule that is the periodic frame list and a set of iTDs On...

Page 540: ...wrap condition and properly advance to the next available Page Buffer Pointer The system software must not use the Page 6 buffer pointer in a transaction description where the length of the transfer w...

Page 541: ...field In the frame caching model the system software assumes that the host controller caches one or more isochronous data structures for an entire frame 8 micro frames The software uses the value of t...

Page 542: ...referenced data structure and begins executing transactions and traversing the linked list as appropriate When the host controller completes processing the asynchronous schedule it retains the value o...

Page 543: ...are two independent events for removing queue heads from the asynchronous schedule The first is shutting down deactivating the asynchronous list The second is extracting a single queue head from an ac...

Page 544: ...htweight handshake that is used by the software as a key that it can free or reuse the memory associated the data structures it has removed from the asynchronous schedule The handshake is implemented...

Page 545: ...head which allows the software to mark a queue head as being the head of the reclaim list host controller also keeps a 1 bit flag in the USBSTS register Reclamation that is cleared when the host cont...

Page 546: ...he proper management of the Reclamation bit in the USBSTS register The host controller tests for an empty schedule just after it fetches a new queue head while traversing the asynchronous schedule The...

Page 547: ...completed This state is always written back to the source qTD when the transfer is complete On transfer for example buffer or halt conditions boundaries the host controller must auto advance without s...

Page 548: ...The upper 20 bits of Page 0 references the start of the physical page Current Offset the lower 12 bits of queue head Dword 7 holds the offset in the page for example 2049 for example 4096 2047 The rem...

Page 549: ...ts of equal poll rates through the schedule so that the periodic bandwidth is allocated and managed in the most efficient manner possible Some examples are illustrated in Table 24 65 24 9 10 3 Managin...

Page 550: ...lows the host to be imprecise on the initialization of the ping protocol that is start in Do OUT when we don t know whether there is space on the device or not The host controller manages the Ping Sta...

Page 551: ...onous Transfers A queue head in the asynchronous schedule with an EPS field indicating a full or low speed device indicates to the host controller that it must use split transactions to stream data fo...

Page 552: ...ller proceeds to the next queue head in the asynchronous schedule When a Nyet handshake is received for a bus transaction where the queue head s PID Code indicates an IN or OUT the host controller rel...

Page 553: ...es The split transaction protocol is managed completely within this defined functional transfer framework For example for a high speed endpoint the host controller will visit a queue head execute a hi...

Page 554: ...w speed link The complete splits may span the H Frame boundary when the start split is in micro frame 4 or later When this occurs the H Frame to B Frame alignment requires that the queue head be reach...

Page 555: ...the use of the spreading technique FSTN data structures are used to preserve the integrity of the binary tree structure and enable the use of the spreading technique Section 24 8 7 Periodic Frame Spa...

Page 556: ...N A Save Place indicator this is always an FSTN with its Back Path Link Pointer T bit cleared A Restore indicator this is always an FSTN with its Back Path Link Pointer T bit set Host controller FSTN...

Page 557: ...hedule that includes FSTNs is illustrated in Figure 24 55 Figure 24 55 Example Host Controller Traversal of Recovery Path via FSTNs In frame N micro frames 0 7 for this example the host controller tra...

Page 558: ...k Path Link Pointer T bit set A Restore FSTN may be matched to one or more Save Place FSTNs For example if the schedule includes a poll rate 1 level then the system software only needs to place a Rest...

Page 559: ...en executed in order This can only occur due to system hold offs where the host controller cannot get to the memory based schedule C prog mask is a simple bit vector that the host controller sets one...

Page 560: ...er keeps the queue head in the Do_Complete state until the split transaction is complete see definition below or an error condition triggers the three strikes rule for example after the host tries the...

Page 561: ...ld After the split transaction has been executed the host controller sets up state in the queue head to track the progress of the complete split phase of the split transaction Specifically it records...

Page 562: ...queue head and sets QH FrameTag to the expected H Frame number The effect to the state of the queue head and thus the state of the transfer depends on the response by the transaction translator to th...

Page 563: ...h as retirement of the qTD and advancement of the queue MDATA This response will only occur for an IN endpoint The transaction translator responded with zero or more bytes of data and an MDATA PID The...

Page 564: ...te exited for example start split is retried This is a host induced error and does not effect Cerr In either case set the Missed Micro frame bit in the status field to a one A not B C If PIDCode IN Ha...

Page 565: ...current micro frame the host controller must not issue the start split bus transaction it must clear the Active bit The system software must save transfer state before setting the I bit This is requir...

Page 566: ...eneral scheduling boundary conditions that are supported by the EHCI periodic schedule The Sn and Cn labels indicate micro frames where the software can schedule start and complete splits respectively...

Page 567: ...nd low speed interrupt queue heads are employed in siTDs to schedule and track the portions of isochronous split transactions The following fields are initialized by the system software to instruct th...

Page 568: ...ription and the time references Each H Frame corresponds to a single location in the periodic frame list The implication is that each siTD is reachable from a single periodic frame list location at a...

Page 569: ...ired so all the mechanism employed for tracking in queue heads is not required for siTDs The software has the option of reusing siTD several times in the complete periodic schedule However it must ens...

Page 570: ...transfer and results in clearing the Active bit However in this case the result has not been delivered by the Transaction Translator and the host must continue with the next complete split transactio...

Page 571: ...between these states Solid circles denote the states of the split transaction state machine and the solid arcs denote the transitions between these states Dotted arcs and boxes reference actions that...

Page 572: ...e value in siTD TP to mark the start split with the correct transaction position code T Count is always initialized to the number of start splits for the current frame TP is always initialized to the...

Page 573: ...nces hold offs that cause the host controller to skip start split transactions for an OUT transfer the state of the transfer will not progress appropriately The transaction translator observes protoco...

Page 574: ...st controller executes a complete split transaction using the transfer state of the current siTD When the host controller commits to executing the complete split transaction it updates QH C prog mask...

Page 575: ...then the transfer state of the siTD is not advanced never received any data and the Active bit is cleared No bits are set in the Status field because this is essentially a skipped transaction The tran...

Page 576: ...recursively walk the list of siTD Back Pointers If siTDX 1 is active Active bit is set and SplitXStat is Do Complete Split then both Test A and Test B are applied as described above If these criteria...

Page 577: ...ome respects the split transaction state machine is sequenced using the Execute Transaction queue head traversal state machine Isochronous is a pure time oriented transaction data stream The interface...

Page 578: ...ave been executed the host controller changes siTDX SplitXState to Do Start Split early and naturally skips the remaining scheduled complete split transactions For this example siTDX 1 does not receiv...

Page 579: ...The value of this register controls when the host controller generates an interrupt on behalf of normal transaction execution When a transaction completes during an interrupt interval period the inte...

Page 580: ...rr field is decremented When the PID Code indicates a SETUP the following responses are protocol errors and result in XactErr bit being set and the Cerr field being decremented EPS field indicates a h...

Page 581: ...of the maximum packet size specified by the device Whenever a device misses an ACK for an IN endpoint the host and device are out of synchronization with respect to the progress of the data transfer T...

Page 582: ...of the interrupt threshold with the one exception being the Interrupt on Async Advance 24 9 14 2 1 Port Change Events Port registers contain status and status change bits When the status change bits...

Page 583: ...NTR register is set then the host controller issues a hardware interrupt This interrupt is not delayed to the next interrupt threshold Table 24 73 summarizes the required actions taken on the various...

Page 584: ...DR pointer The even numbered device queue heads in the list support receive endpoints OUT SETUP and the odd numbered queue heads in the list are used for transmit endpoints IN INTERRUPT The device con...

Page 585: ...9 8 7 6 5 4 3 2 1 0 Offset Mult zlt 00 Maximum Packet Length ios 000_0000_0000_0000 0x00 Current dTD Pointer1 1 Device controller read write all others read only 0_0000 0x04 Next dTD Pointer1 0000 T1...

Page 586: ...an RX dQH associated with it and only the RX queue head is used for receiving setup data packets 29 zlt Zero length termination select This bit is used to indicate when a zero length packet is used t...

Page 587: ...er to be read by the software 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Next Link Pointer 0000 T 0x00 00 Total Bytes1 1 Device controller read write...

Page 588: ...oftware builds such a transfer descriptor for an IN transfer the last transaction will always be less that Maximum Packet Length 15 Interrupt On Complete IOC This bit is used to indicate if USBINT is...

Page 589: ...perform the following steps 1 Set Controller Mode to device mode Optionally set Streaming Disable in the USBMODE register NOTE Transitioning from host mode to device mode requires a device controller...

Page 590: ...is designed as a control endpoint only and does not need to be configured using ENDPTCTRL0 register It is also not necessary to initially prime Endpoint 0 because the first packet received will alway...

Page 591: ...g the status bits identified in Table 24 79 Device Configured Address Assigned Reset When the host resets the device returns to the default state Power Interruption Bus Activity Bus Activity Bus Activ...

Page 592: ...ar all setup token semaphores by reading the ENDPTSETUPSTAT register and writing the same value back to the ENDPTSETUPSTAT register Clear all the endpoint complete status bits by reading the ENDPTCOMP...

Page 593: ...e USB_DR exits suspend mode when there is bus activity It may also request the host to exit suspend mode or selective suspend by using electrical signaling to indicate remote wake up The ability of a...

Page 594: ...e DCD can configure endpoint 1 IN to be a bulk endpoint and endpoint 1 OUT to be an isochronous endpoint This helps to conserve the total number of endpoints required for device operation The only exc...

Page 595: ...same instant NOTE Any write to the ENDPTCTRLn register during operational mode must preserve the endpoint type field that is perform a read modify write 24 11 3 2 Data Toggle Data toggle is a mechanis...

Page 596: ..._DR prepares packets for each endpoint direction in anticipation of the host request The process of preparing the device controller to send or receive data in response to host initiated transaction on...

Page 597: ...n primed data delivery will commence A dTD will be retired by the device controller when the packets described in the transfer descriptor have been completed Each dTD describes N packets to be transfe...

Page 598: ...followed when the Terminate bit is clear When the Terminate bit is set the USB_DR will flush the endpoint direction and cease operations for that endpoint direction On the unsuccessful completion of...

Page 599: ...up Lockout Mode As 0 will result in a potential compliance issue After receiving an interrupt and inspecting ENDPTSETUPSTAT to determine that a setup packet was received on a particular pipe Write 1 t...

Page 600: ...me the endpoint for the status phase The DCD must also perform the same checks of the ENDPTSETUPSTAT as described above in the data phase NOTE The MULT field in the dQH must be set to 00 for bulk inte...

Page 601: ...SOF is received After the DCD writes the prime bit the prime bit will be cleared as usual to indicate to the software that the device controller completed a priming the dTD for transfer Internal to th...

Page 602: ...by at least two micro frames 24 11 3 6 1 Isochronous Pipe Synchronization When it is necessary to synchronize an isochronous data pipe to the host the micro frame number FRINDEX register can be used a...

Page 603: ...will no longer be part of the linked list from the queue head Therefore the software is required to track all transfer descriptors since pointers will no longer exist within the queue head once the dT...

Page 604: ...2 or 3 as required bandwidth an in conjunction with the USB Chapter 9 protocol Note In FS mode the multiplier field can only be 1 for ISO endpoints Write the next dTD Terminate bit field to 1 Write t...

Page 605: ...ious control transfers and flush if any exist as discussed in Section 24 11 5 5 Flushing De Priming an Endpoint NOTE It is possible for the device controller to receive setup packets before previous c...

Page 606: ...er page 0 and the current offset to point to the start of the data buffer 7 Initialize buffer pointer page 1 through page 4 to be one greater than each of the previous buffer pointer 24 11 5 3 Executi...

Page 607: ...cuted DCD can check the status bits to determine success or failure CAUTION Multiple dTD can be completed in a single endpoint complete notification After clearing the notification DCD must search the...

Page 608: ...hat fail to flush be repeating steps 1 3 until each endpoint is successfully flushed 24 11 5 6 Device Error Matrix Table 24 88 summarizes packet errors that are not automatically handled by the USB_DR...

Page 609: ...tack up on any call to the Interrupt Service Routine AND during the Interrupt Service Routine Copy contents of setup buffer and acknowledge setup packet as indicated in Section 24 11 4 Managing Queue...

Page 610: ...vice operation and OTG operation are not specified in the EHCI and thus the implementation supported in the USB OTG module is proprietary 24 12 1 Embedded Transaction Translator Function In Host mode...

Page 611: ...ons to a device downstream from direct attached FS hub QH EPS Downstream Device Speed NOTE When QH EPS 01 LS and PORTSCn PSPD 00 FS a LS pre pid will be sent before the transmitting LS traffic Maximum...

Page 612: ...continue until the stored periodic transfers are complete As an example of the microframe pipeline implemented in the embedded Transaction Translator all periodic transfers that are tagged in EHCI to...

Page 613: ...started in microframes 6 Idle for more than 4 microframes Abort of pending complete splits EOF Idle for more than 4 microframes USB 2 0 11 18 7 8 Transaction tracking for up to 16 data pipes Some app...

Page 614: ...st Controller Structural Parameters HCSPARAMS for more information 24 12 2 Device Operation The co existence of a device operational controller within the USB OTG module has little effect on EHCI comp...

Page 615: ...e Modes The control bits for selecting the PHY operating mode have been added to the PORTSCn register providing a capability that is not defined by the EHCI specification 24 12 6 2 Discovery 24 12 6 2...

Page 616: ...eed Unlike the EHCI implementation which will re assign the port owner for any device that does not connect at High Speed this host controller supports direct attach of non HS devices Therefore the fo...

Page 617: ...figurable as Rx or Tx all supporting standard and extended messages Listen only mode capability Three programmable mask registers global for MBs 0 13 and 16 31 special for MB14 and special for MB15 Pr...

Page 618: ...iety of mediums such as fiber optic cable or an unshielded twisted pair of wires The FlexCAN supports both the standard and extended identifier ID message formats specified in the CAN protocol specifi...

Page 619: ...s connected physically to the CAN bus through a transceiver The transceiver provides the transmit drive waveshaping and receive compare functions required for communicating on the CAN bus It can also...

Page 620: ...ning to participate in CAN bus communication 25 3 2 3 Module Disabled Mode This mode disables the FlexCAN module it is entered by setting CANMCRn MDIS If the module is disabled during freeze mode it s...

Page 621: ...transceiver while CANnRX receives serial data from the CAN bus transceiver 25 5 Memory Map and Register Definitions The FlexCAN module address space is split into 128 bytes starting at the base addres...

Page 622: ...global system configurations such as the module operation mode and maximum message buffer configuration Most of the fields in this register can be accessed at any time except the MAXMB field which sh...

Page 623: ...hen set the FlexCAN can enter freeze mode when the BKPT line is asserted or the HALT bit is set Clearing this bit causes the FlexCAN to exit freeze mode Refer to Section 25 3 2 2 Freeze Mode for more...

Page 624: ...24 FRZACK Freeze acknowledge Indicates that the FlexCAN module has entered freeze mode The user should poll this bit after freeze mode has been requested to know when the module has actually entered f...

Page 625: ...by 256 For more information refer to Section 25 6 8 Bit Timing Eqn 25 1 23 22 RJW Resynchronization jump width Defines the maximum number of time quanta one time quantum is equal to the S clock perio...

Page 626: ...bits occurred then FlexCAN will re synchronize to the bus by waiting for 11 recessive bits before joining the bus After clearing the BOFFREC bit can be set again during bus off but it will only be ef...

Page 627: ...ly written 25 5 4 Rx Mask Registers RXGMASKn RX14MASKn RX15MASKn These registers are used as acceptance masks for received frame IDs Three masks are defined a global mask RXGMASKn used for Rx buffers...

Page 628: ...match for MB3 because of ID0 Rx_Msg in4 0 1 1 1 1 1 1 1 0 0 0 0 4 4 Mismatch for MB2 because of ID28 Rx_Msg in5 0 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MB145 5 Mismatch for MB3 bec...

Page 629: ...to a value less than or equal to 127 while the other already satisfies this condition the ERRSTATn FLTCONF field is updated to reflect error active state If the value of TXECTR increases to be greate...

Page 630: ...ion 25 7 1 Interrupts Offset MBAR2 0x101C ERRCNT0 MBAR2 0x201C ERRCNT1 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0...

Page 631: ...1 FRMERR Message form error Indicates that a form error has been detected by the receiver node i e a fixed form bit field contains at least one illegal bit 0 No form error was detected since the last...

Page 632: ...nterrupt Indicates that at least one of the ERRSTATn 15 10 bits is set The user must write a 1 to clear this bit Writing 0 has no effect 0 No error interrupt request 1 At least one of the error bits i...

Page 633: ...r read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R BUFnI n 31 0 W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25...

Page 634: ...dentifier 11 bits and the extended identifier 18 bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x0 CODE SRR IDE RTR LENGTH TIME STAMP 0x4 Standard ID 28 18...

Page 635: ...onsidered as a successful bit transmission 0 Indicates the current MB has a data frame to be transmitted 1 Indicates the current MB has a remote frame to be transmitted 19 16 LENGTH Length of data in...

Page 636: ...ffer 0010 If the code indicates OVERRUN but the CPU reads the C S word and then unlocks the MB when a new frame is written to the MB the code returns to FULL 0110 If the code already indicates OVERRUN...

Page 637: ...0000 or 1000 will be temporarily deactivated will not participate in the current arbitration matching run when the CPU writes to the C S field of that MB 25 6 1 Transmit Process The CPU prepares or ch...

Page 638: ...ID or the lowest MB number depending on the CANCTRLn LBUF bit NOTE If CANCTRLn LBUF is cleared the arbitration considers not only the ID but also the RTR and IDE bits placed inside the ID at the same...

Page 639: ...C S word of another MB Note that only a single MB is locked at a time The only mandatory CPU read operation is the one on the control and status word to assure data coherency The CPU should synchroni...

Page 640: ...orresponding ID bit is don t care 25 6 5 Message Buffer Handling In order to maintain data coherency and FlexCAN proper operation the CPU must obey the rules described in Section 25 6 1 Transmit Proce...

Page 641: ...might be present that it had already scanned before the deactivation There is a point in time until which the deactivation of a Tx MB causes it not to be transmitted end of move out After this point...

Page 642: ...be received When transmitting a remote frame the user initializes a message buffer as a transmit message buffer with the RTR bit set Once this remote frame is transmitted successfully the transmit me...

Page 643: ...ever a tight tolerance up to 0 1 is required for the CAN bus timing The crystal oscillator clock has better jitter performance than PLL generated clocks The value of this bit should not be changed unl...

Page 644: ...lated parameter values NOTE It is the user s responsibility to ensure the bit time settings are in compliance with the CAN standard For bit time calculations use an IPT Information Processing Time of...

Page 645: ...the clocks resumed before applying soft reset The clock source CANCTRLn CLK_SRC should be selected while the module is in disable mode After the clock source is selected and the module is enabled CANM...

Page 646: ...quired mask bits in the IMASKn register for all message buffer interrupts and the CANCTRLn for bus off and error interrupts 5 Clear the CANMCRn HALT bit At this point the FlexCAN will attempt to synch...

Page 647: ...of the RTC block Figure 26 1 Real Time Clock Block Diagram 26 2 External Signal Description Table 26 1 describes the RTC external signals 26 3 Memory Map and Register Definitions The RTC module s reg...

Page 648: ...ock has been in low battery state it will set the RTC_POWER_LOSS status bit in the ATA DMA configuration register This bit will remain set until the user sets the RTC_CLEAR bit in the ATA DMA configur...

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