Universal Serial Bus Interface
MCF5253 Reference Manual, Rev. 1
24-50
Freescale Semiconductor
24.8.3.2
iTD Transaction Status and Control List
DWords 1 through 8 are eight slots of transaction control and status. Each transaction description includes:
•
Status results field
•
Transaction length (bytes to send for OUT transactions and bytes received for IN transactions).
•
Buffer offset. The PG and Transaction
n
Offset fields are used with the buffer pointer list to
construct the starting buffer address for the transaction.
The host controller uses the information in each transaction description plus the endpoint information
contained in the first three DWords of the Buffer Page Pointer list, to execute a transaction on the USB.
2–1
Typ
This field indicates to the Host Controller whether the item referenced is an iTD, siTD or a QH. This allows
the Host Controller to perform the proper type of processing on the item after it is fetched. Value encodings
are:
00 iTD (isochronous transfer descriptor)
01 QH (queue head)
10 siTD (split transaction isochronous transfer descriptor
11 FSTN (frame span traversal node)
0 T
Terminate
1 Link Pointer field is not valid
0 Link Pointer field is valid
Table 24-39. iTD Transaction Status and Control
Bit
Name
Description
31–28
Status
This field records the status of the transaction executed by the host controller for this slot. This field is
a bit vector with the following encoding:
31 Active. Set by the software to enable the execution of an isochronous transaction by the Host
Controller. When the transaction associated with this descriptor is completed, the Host Controller
sets this bit to zero indicating that a transaction for this element should not be executed when it is
next encountered in the schedule.
30 Data Buffer Error. Set by the Host Controller during status update to indicate that the Host Controller
is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast
enough during transmission (underrun). If an overrun condition occurs, no action is necessary.
29 Babble Detected. Set by the Host Controller during status update when” babble” is detected during
the transaction generated by this descriptor.
28 Transaction Error (XactErr). Set by the Host Controller during status update in the case where the
host did not receive a valid response from the device (Time-out, CRC, Bad PID, etc.). This bit may
only be set for isochronous IN transactions.
27–16 Transaction
n
Length
For an OUT, this field is the number of data bytes the host controller will send during the transaction.
The host controller is not required to update this field to reflect the actual number of bytes transferred
during the transfer. For an IN, the initial value of the endpoint to deliver. During the status update, the
host controller writes back the field is the number of bytes the host expects the number of bytes
successfully received. The value in this register is the actual byte count (for example, 0 zero length
data, 1 one byte, 2 two bytes, etc.). The maximum value this field may contain is 0xC00 (3072).
15
ioc
Interrupt on complete. If this bit is set, it specifies that when this transaction completes, the Host
Controller should issue an interrupt at the next interrupt threshold.
Table 24-38. Next Schedule Element Pointer (continued)
Bit
Name
Description
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
