Audio Interface Module (AIM)
MCF5253 Reference Manual, Rev. 1
17-28
Freescale Semiconductor
17.7.2
Data Exchange Register Overview
•
PDOR1-L, PDOR1-R: (Processor Data Out 1). These are 32-bit registers. Both registers have 4
consecutive longword addresses assigned (multiple decode). This allows easy transfer of multiple
samples using MOVEM instructions. Data written to these registers will end in one of the FIFO ‘s
(
)
12, 14, 17, 17a, 17b
or
25
. The format of data in the registers is defined below.
•
PDOR2-L, PDOR2-R: (Processor Data Out 2). Same function as PDOR1. Both (PDOR2-L and
PDOR2-R) registers occupy 4 consecutive longword addresses (multiple decoded.) Data written to
it will end in one of the FIFO ‘s. (fig. 17-1)
12,14,17, 17a, 17b
or
25
.
•
PDOR3: (Processor Data Out3). Same function as PDOR1. But it is a single 32-bit register which
contains both Left + Right data in 16-bit precision occupying 4 consecutive longword addresses.
Data written to it will end in one of the FIFO ‘s. (fig 17-1)
12,14, 17a, 17b
or
25
.
•
PDIR1-L, PDIR1-R (Processor data in). Used to transfer data to the processor. These 32-bit
registers, each occupy 4 consecutive longword addresses are used to read data from the audio bus.
0x34
0x38
0x3C
0x40
PDOR1-L
32
Processor data out 1 Left.
Multiple address to write this register allows MOVEM instruction to write FIFO.
undef
W
0x44
0x48
0x4C
0x50
PDOR1-R
32
Processor data out 1 Right
Multiple address to write this register allows MOVEM instruction to write FIFO
undef
W
0x54
0x58
0x5C
0x60
PDOR2-L
32
Processor data out 2 Left
Multiple address to write this register allows MOVEM instruction to write FIFO
undef
W
0x64
0x68
0x6C
0x70
PDOR2-R
32
Processor data out 2 Right
Multiple address to write this register allows MOVEM instruction to write FIFO
undef
W
0x74
0x78
0x7C
0x80
PDOR3
32
Processor data out 3 left + right
undef
W
0x74
0x78
0x7C
0x80
PDIR2
32
Processor data in 3 left + right
undef
R
1
Multiple addresses for PDOR/PDIR fields are intended for easy use of MOVEM instruction to move data into and out of the FIFOs.
The data read at each address of any range is exactly the same, being the next sample in/out of the FIFO. There is no difference
in FIFO operation between a read at address e.g. 0x74, 0x78, 0x7C.
2
There are memory overlaps between PDIR’s and PDOR’s. PDOR’s cannot be read, PDIR cannot be written.
Table 17-14. Data Exchange Register Descriptions (continued)
Address
MBAR2 +
Name
Width
Description
1, 2
Reset
Value
Access
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
