Bus Operation
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
8-9
shows the description for the six states of a basic write cycle.
Figure 8-6. Basic Write Bus Cycle
8.5.4
Back-to-Back Bus Cycles
The MCF5253 can accommodate back-to-back bus cycles. The processor runs back-to-back bus cycles
whenever possible. For example, when a longword read is started on a word-size bus, and burst read enable
is disabled into the relevant chip select register, the processor will perform two word reads back to back.
shows a read, followed by a write that occurs back to back.
Table 8-7. Write Cycle States
State Name
Description
STATE 0
The write cycle is initiated in state 0 (S0). On the rising edge of BCLK, the MCF5253 places a valid address on
the address bus and drives RW low, if it is not already low.
STATE 1
The appropriate CS is asserted on the falling edge of BCLK.
STATE 2
The data bus is driven out of high impedance as data is placed on the bus on the rising edge of BCLK.
STATE 3
During state 3 (S3), the MCF5253 waits for a cycle termination signal (TA). If TA is not asserted before the rising
edge of BCLK at the end of the first clock cycle, the MCF5253 inserts wait states (full clock cycles) until TA is
asserted. TA is generated internally by the chip select module. If internal TA is requested (auto-acknowledge
enabled in the chip select control register, CSCR) then TA is generated internally by the chip select module.
STATE 4
During state 4, TA should be negated by the external device or if auto-acknowledge is enabled, negated internally
by the chip select module.
STATE 5
CS is negated on the falling edge of BCLK in state 5 (S5). The MCF5253 stops driving the address lines and RW,
terminating the write cycle. The data bus returns to high impedance on the rising edge of BCLK.
The rising edge of BCLK may be the start of state 0 for the next access cycle.
BCLK
A[23:1]
RW
D[31:16]
TA
S0
S1
S2
S3
S4
S5
CSx
Write
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
