Background Debug Mode (BDM) Interface
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
20-39
20.5.7
BDM Address Attribute Register (BAAR)
The BAAR register defines the address space for memory-referencing BDM commands. Bits [7:5] are
loaded directly from the BDM command, while the low-order 5 bits can be programmed from the external
development system. To maintain compatibility with the Rev. A implementation, this register is loaded any
time the AATR is written. The BAR is initialized to a value of $5, setting “supervisor data” as the default
address space.
20.5.8
Concurrent BDM and Processor Operation
The debug module supports concurrent operation of both the processor and most BDM commands. BDM
commands may be executed while the processor is running, except for the operations that access
processor/memory registers as follows:
5
IPI
If set, the Ignore Pending Interrupts bit forces the processor core to ignore any pending interrupt requests
signalled while executing in single-instruction-step mode.
4
SSM
If set, the Single-Step Mode bit forces the processor core to operate in a single-instruction-step mode. While
in this mode, the processor executes a single instruction and then halts. While halted, any of the BDM
commands may be executed. On receipt of the GO command, the processor executes the next instruction and
then halts again. This process continues until the single-instruction-step mode is disabled.
Access: User write only
7
6
5
4
3
2
1
0
R
W
R
SZ
TT
TM
Reset
0
0
0
0
0
1
0
1
Figure 20-38. BDM Address Attribute Register (BAAR)
Table 20-23. BDM Address Attribute (BAAR) Register Field Descriptions
Field
Description
7
R
0 Write
1 Read
6–5
SZ
Size
00 Longword
01 Byte
10 Word
11 Reserved
4–3
TT
Transfer Type
See the TT definition in the AATR description,
Section 20.5.2, “Address Attribute Trigger Register.”
2–0
TM
Transfer Modifier
See the TM definition in the AATR description,
Section 20.5.2, “Address Attribute Trigger Register.”
Table 20-22. Configuration/Status Register (CSR) Field Descriptions (continued)
Field
Description
Summary of Contents for MCF5253
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Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
