9 Appendix
9.1 Data image of the technology modules
188
XI/ON: XNE-GWBR-2ETH-MB
10/2011 MN05002008Z-EN
www.eaton.com
Table 85:
Process output
data of
XN-1SSI
Designation
Value
Meaning
REG_WR_DATA
0...
(2
32
-1)
Value to be written to the register with the address stated at
REG_WR_ADR.
REG_RD_ADR
0...63
Address of the register to be read. If the read operation is
successful (REG_RD_ABORT = 0), the user data is located in
REG_RD_DATA of the process input data (bytes 4 – 7).
REG_WR
0
Default status, i.e. there is no request to overwrite the
content of the register with the address stated at
REG_WR_ADR with REG_WR_DATA. Bit REG_WR_AKN is
reset (0) if necessary.
1
Request to overwrite the content of the register with the
address stated at REG_WR_ADR with REG_WR_DATA.
REG_WR_ADR
0...63
Address of the register to be written with REG_WR_DATA.
CLR_CMP2
0
Default status, i.e. no reset of FLAG_CMP2 active.
1
Reset of FLAG_CMP2 active
EN_CMP2
0
Default status, i.e. the data bits REL_CMP2, STS_CMP2 and
FLAG_CMP2 always have the value 0, irrespective of the
actual SSI encoder value.
1
Comparison active, i.e. the data bits REL_CMP2,STS_CMP2
and FLAG_CMP2 have a value based on the result of the
comparison with the SSI encoder value.
CLR_CMP1
0
Default status, i.e. reset of FLAG_CMP1 not active.
1
Reset of FLAG_CMP1 active
EN_CMP1
0
Default status, i.e. the data bits REL_CMP1, STS_CMP1 and
FLAG_CMP1 always have the value 0, irrespective of the
actual SSI encoder value.
1
Comparison active, i.e. the data bits REL_CMP1, STS_CMP1
and FLAG_CMP1 have a value based on the result of the
comparison with the SSI encoder value.
STOP
0
Request to read the SSI encoder cyclically
1
Request to interrupt communication with the encoder
