Core Configuration
4
-1
Chapter 4
Core Configuration
This chapter presents DSP56300 core configuration details specific to the DSP56303,
including:
n
Operating modes
n
Bootstrap program
n
Central Processor registers
— Status register (SR)
— Operating mode register (OMR)
n
Interrupt Priority Registers (IPRC and IPRP)
n
PLL control (PCTL) register
n
Bus Interface Unit registers
— Bus Control Register (BCR)
— DRAM Control Register (DCR)
— Address Attribute Registers (AAR[3–0])
n
DMA Control Registers 5–0 (DCR[5–0])
n
Device identification register (IDR)
n
JTAG identification register
n
JTAG boundary scan register (BSR)
For information on specific registers or modules in the DSP56300 core, refer to the
DSP56300 Family Manual.
Summary of Contents for DSP56303
Page 1: ...DSP56303 User s Manual 24 Bit Digital Signal Processor DSP56303UM AD Revision 1 January 2001 ...
Page 52: ...JTAG OnCE Interface 2 22 DSP56303 User s Manual ...
Page 114: ...General Purpose Input Output GPIO 5 10 DSP56303 User s Manual ...
Page 212: ...GPIO Signals and Registers 8 26 DSP56303 User s Manual ...
Page 268: ...Interrupt Equates A 22 DSP56303 User s Manual ...
Page 306: ...Programming Sheets B 38 DSP56303 User s Manual ...
Page 320: ...Index 14 DSP56303 User s Manual ...