IDT JTAG Boundary Scan
Instruction Register (IR)
PES12N3 User Manual
11 - 8
June 7, 2006
Notes
CLAMP
This instruction, listed as optional in the IEEE 1149.1 JTAG Specifications, allows the boundary scan
chain outputs to be clamped to fixed values. When the clamp instruction is issued, the scan chain will
bypass the PES12N3 and pass through to devices further down the scan chain.
DEVICEID
The DEVICEID instruction is automatically loaded when the TAP controller state machine is reset either
by the use of the JTAG_TRST_N signal or by the application of a ‘1’ on JTAG_TMS for five or more cycles
of JTAG_TCK as per the IEEE Std. 1149.1 specification. The least significant bit of this value must always
be 1. Therefore, if a device has a DEVICE_ID register, it will shift out a 1 on the first shift if it is brought
directly to the SHIFT-DR TAP controller state after the TAP controller is reset. The board- level tester can
then examine this bit and determine if the device contains a DEVICE_ID register (the first bit is a 1), or if the
device only contains a BYPASS register (the first bit is 0).
However, even if the device contains a DEVICE_ID register, it must also contain a BYPASS register. The
only difference is that the BYPASS register will not be the default register selected during the TAP controller
reset. When the DEVICE_ID instruction is active and the TAP controller is in the Shift-DR state, the thirty-
two bit value that will be shifted out of the device-ID register is 0x00022067.
VALIDATE
The VALIDATE instruction is automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits ‘01’ are mandated by the IEEE Std.
1149.1 specification.
RESERVED
Reserved instructions implement various test modes used in the device manufacturing process. The
user should not enable these instructions.
UNUSED
1
The unused instructions are behaviorally equivalent to the BYPASS instruction as per the IEEE Std.
1149.1 specification. However, the user is advised to use the explicit BYPASS instruction as the internal
usage of these currently unused instructions could possibly vary in future implementations of the device.
Bit(s) Mnemonic
Description
R/W
Reset
0
reserved
Reserved
R
0x1
11:1
Manuf_ID
Manufacturer Identity (11 bits)
This field identifies the manufacturer as IDT.
R
0x33
27:12 Part_number
Part Number (16 bits)
This field identifies the silicon as PES12N3.
R
0x800C
31:28
Version
Version (4 bits)
This field identifies the silicon revision of the PES12N3.
R
silicon-
dependent
Table 11.4 System Controller Device Identification Register
Version
Part Number
Mnfg. ID
LSB
xxxx
1000|0000|0000|1100
0000|0110|011
1
Figure 11.7 Device ID Register Format
1.
Any unused instruction is defaulted to the BYPASS instruction
Summary of Contents for 89HPES12N3
Page 10: ...IDT Table of Contents PES12N3 User Manual iv June 7 2006 Notes...
Page 14: ...IDT List of Figures PES12N3 User Manual viii June 7 2006 Notes...
Page 36: ...IDT Clocking Reset and Initialization Reset PES12N3 User Manual 2 8 June 7 2006 Notes...
Page 40: ...IDT Link Operation Slot Power Limit Support PES12N3 User Manual 3 4 June 7 2006 Notes...
Page 50: ...IDT Switch Operation Switch Core Errors PES12N3 User Manual 4 10 June 7 2006 Notes...
Page 54: ...IDT Power Management Active State Power Management PES12N3 User Manual 5 4 June 7 2006 Notes...
Page 62: ...IDT Hot Plug and Hot Swap Hot Swap PES12N3 User Manual 6 8 June 7 2006 Notes...
Page 78: ...IDT SMBus Interfaces Slave SMBus Interface PES12N3 User Manual 7 16 June 7 2006 Notes...
Page 148: ...IDT Test and Debug SerDes Test Clock PES12N3 User Manual 10 6 June 7 2006...
Page 158: ...IDT JTAG Boundary Scan Usage Considerations PES12N3 User Manual 11 10 June 7 2006 Notes...
