Analog-to-Digital Converter (ADC)
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
25-13
Preliminary
25.4.7
Limit Status Register (ADLSTAT)
The ADC limit status (ADLSTAT) register latches in the result of the comparison between the result of the
sample in the ADRSLT
n
register and the respective limit register, ADHLMT
n
or ADLLMT
n
.
For example, if the result for ADRSLT0 is greater than the value programmed into ADHLMT0, then the
the HLS0 bit is set. An interrupt is generated if CTRL1[HLMTIE] is set.
These bits are sticky—they are not cleared automatically by subsequent conversions. A bit may only be
cleared by writing a 1 to it.
8
HLMTI
High Limit Interrupt bit. If any high limit register (ADHLMT
n
) is enabled by having a value other than 0x7FF8,
high limit checking is enabled. This bit is set at the completion of an individual conversion which may or may
not be the end of a scan. It is cleared by writing 1 to all active ADLSTAT[HLS] bits.
0 No high limit interrupt request
1 High limit exceeded, IRQ pending if CTRL1[HLMTIE] is set
7–0
RDY
n
Ready Sample bits. These bits indicate samples 7-0 are ready to be read. The RDY
n
bits are set as the
individual channel conversions are completed and stored in a ADRSLT
n
register. These bits are cleared after
a read from the corresponding ADC results (ADRSLT
n
) register. If polling the RDY
n
bits to determine if a
particular sample is executed, care should be taken not to start a new scan until all enabled samples are
completed.
0 Sample not ready or has been read
1 Sample ready to be read
Note:
RDY
n
bits can be cleared when the debugger reads the corresponding results register during a debug
session.
IPSBAR
Offset: 0x19_000E (ADLSTAT)
Access: read/write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
HLS7 HLS6 HLS5 HLS4 HLS3 HLS2 HLS1 HLS0 LLS7 LLS6 LLS5 LLS4 LLS3 LLS2 LLS1 LLS0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 25-10. Limit Status Register (ADLSTAT)
Table 25-12. ADLSTAT Field Descriptions
Field
Description
15–8
HLS
n
High Limit Status bits. These bits hold the result of a comparison between the sample (stored in ADRSLT
n
)
and the high-limit value (stored in ADHLMT
n
).
0 Sample
n
is less than or equal to the associated high-limit value
1 Sample
n
is greater than the associated high-limit value
Note:
These bits are sticky, and can only be cleared by writing a 1 to them.
7–0
LLS
n
Low Limit Status bits. These bits hold the result of a comparison between the sample (stored in ADRSLT
n
)
and the low-limit value (stored in ADLLMT
n
).
0 Sample
n
is greater than or equal to the associated low-limit value
1 Sample
n
is less than the associated low-limit value
Note:
These bits are sticky, and can only be cleared by writing a 1 to them.
Table 25-11. ADSTAT Field Descriptions (continued)
Field
Description
