FIFO Data Interface
Writing and reading the FIFOs is straightforward, and similar to the procedure outlined in
. All FIFO writes
and reads are performed through the SPInDAT register. To write data into the transmit buffer, firmware should first check the status of
the TXNF bit. If TXNF reads 1, there is room in the buffer and firmware may write to the SPInDAT register. Writing the transmit buffer
when TXNF is 0 will cause a write collision error, and the data written will not be accepted into the buffer.
To read data from the receive FIFO, firmware should check the state of the RXE bit. When RXE is 0, it means there is data available in
the receive FIFO, and it may be read using the SPInDAT register. When RXE is 1 the receive FIFO is empty. Reading an empty receive
FIFO returns the most recently-received byte.
The data in either FIFO may be flushed (i.e. FIFO pointers reset) by setting the corresponding flush bit to 1. TFLSH will reset the trans-
mit FIFO, and RFLSH will reset the receive FIFO.
Half-Duplex Operation
SPI transfers are inherently full-duplex. However, the operation of either FIFO may be disabled to facilitate half-duplex operation.
The TXHOLD bit is used to stall transmission of bytes from the transmit FIFO. TXHOLD is checked by hardware at the beginning of a
byte transfer. If TXHOLD is 1 at the beginning of a byte transfer, data will not be pulled from the transmit FIFO. Instead, the SPI inter-
face will hold the output pin at the logic level defined by the TXPOL bit.
The RXFIFOE bit may be used to disable the receive FIFO. If RXFIFOE is 0 at the end of a byte transfer, the received byte will be
discarded and the receive FIFO will not be updated.
TXHOLD and RXFIFOE can be changed by firmware at any time during a transfer. Any data currently being shifted out on the SPI
interface has already been pulled from the transmit FIFO, and changing TXFLSH will not abort that data transfer.
FIFO Thresholds and Interrupts
The number of bytes present in the FIFOs is stored in the SPInFCT register. The TXCNT field indicates the number of bytes in the
transmit FIFO while the RXCNT field indicates the number of bytes in the receive FIFO.
Each FIFO has a threshold field which firmware may use to define when transmit and receive requests will occur. The transmit thresh-
old (TXTH) is continually compared with the TXCNT field. If TXCNT is less than or equal to TXTH, hardware will set the TFRQ flag to 1.
The receive threshold (RXTH) is continually compared with RXCNT. If RXCNT is greater than RXTH, hardware will set the RFRQ flag
to 1.
The thresholds can be used in interrupt-based systems to specify when the associated interrupt occurs. Both the RFRQ and TFRQ
flags may be individually enabled to generate an SPI interrupt using the RFRQE and TFRQE bits, respecitvely. In most applications,
when RFRQ or TFRQ are used to generate interrupts the SPIF flag should be disabled as an interrupt source by clearing the SPIFEN
control bit to 0.
Applications may choose to use any combination of interrupt sources as needed. In general, the following settings are recommended
for different applications:
•
Master mode, transmit only
: Use only the TFRQ flag as an interrupt source. Inside the ISR, check TXNF before writing more data
to the FIFO. When all data to be sent has been processed through the ISR, the ISR may clear TFRQE to 0 to prevent further inter-
rupts. Main threads may then set TFRQE back to 1 when additional data is to be sent.
•
Master mode, full-duplex or receive only
: Use only the RFRQ flag as an interrupt source. Transfers may be started by a write to
SPInDAT. Inside the ISR, check RXE and read bytes from the FIFO as they are available. For every byte read, a new byte may be
written to the transmit FIFO until there are no more bytes to send. If operating half-duplex in receive-only mode, the SPInDAT regis-
ter must still be written to initiate new transfers.
•
Slave mode, transmit only
: Use the TFRQ flag as an interrupt source. Inside the ISR, check TXNF before writing more data to the
FIFO. The receive FIFO may also be disabled if desired.
•
Slave mode, receive only
: Use the RFRQ flag as an interrupt source. If the RXTH field is set to anything other than 0, it is recom-
mended to configure and enable RX timeouts. Inside the ISR, check RXE and read bytes from the FIFO as they are available. The
transmit FIFO may be disabled if desired. Note that if the transmit FIFO is not disabled and firmware does not write to SPInDAT,
bytes received in the shift register could be sent back out on the SPI MISO pin.
•
Slave mode, full-duplex
: Pre-load the transmit FIFO with the initial bytes to be sent. Use the RFRQ flag as an interrupt source. If
the RXTH field is set to anything other than 0, it is recommended to configure and enable RX timeouts. Inside the ISR, check RXE
and read bytes from the FIFO as they are available. For every byte read, a new byte may be written to the transmit FIFO.
EFM8UB3 Reference Manual
Serial Peripheral Interface (SPI0)
silabs.com
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