SLA6
SDA
SLA5-0
R/W
D7
D6-0
SCL
Slave A R/W
Data Byte
START
ACK
NACK
STOP
Figure 18.3. SMBus Transaction
Transmitter vs. Receiver
On the SMBus communications interface, a device is the “transmitter” when it is sending an address or data byte to another device on
the bus. A device is a “receiver” when an address or data byte is being sent to it from another device on the bus. The transmitter con-
trols the SDA line during the address or data byte. After each byte of address or data information is sent by the transmitter, the receiver
sends an ACK or NACK bit during the ACK phase of the transfer, during which time the receiver controls the SDA line.
Arbitration
A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL and SDA lines remain high
for a specified time (see
● SCL High (SMBus Free) Timeout on page 234
). In the event that two or more devices attempt to begin a
transfer at the same time, an arbitration scheme is employed to force one master to give up the bus. The master devices continue
transmitting until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be pulled LOW. The
master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning master continues its transmission without
interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. This arbitration scheme is non-de-
structive: one device always wins, and no data is lost.
Clock Low Extension
SMBus provides a clock synchronization mechanism, similar to I
2
C, which allows devices with different speed capabilities to coexist on
the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The
slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency.
SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the master cannot force the
SCL line high to correct the error condition. To solve this problem, the SMBus protocol specifies that devices participating in a transfer
must detect any clock cycle held low longer than 25 ms as a “timeout” condition. Devices that have detected the timeout condition must
reset the communication no later than 10 ms after detecting the timeout condition.
For the SMBus 0 interface, Timer 3 is used to implement SCL low timeouts. The SCL low timeout feature is enabled by setting the
SMB0TOE bit in SMB0CF. The associated timer is forced to reload when SCL is high, and allowed to count when SCL is low. With the
associated timer enabled and configured to overflow after 25 ms (and SMB0TOE set), the timer interrupt service routine can be used to
reset (disable and re-enable) the SMBus in the event of an SCL low timeout.
SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 μs, the bus is designated as free. When
the SMB0FTE bit in SMB0CF is set, the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source
periods (as defined by the timer configured for the SMBus clock source). If the SMBus is waiting to generate a Master START, the
START will be generated following this timeout. A clock source is required for free timeout detection, even in a slave-only implementa-
tion.
EFM8UB3 Reference Manual
System Management Bus / I2C (SMB0)
silabs.com
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