20.3.6 Multiprocessor Communications
UART1 supports multiprocessor communication between a master processor and one or more slave processors by special use of the
extra data bit. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s).
An address byte differs from a data byte in that its extra bit is logic 1; in a data byte, the extra bit is always set to logic 0.
Setting the MCE bit and the XBE bit in the SMOD1 register configures the UART for multi-processor communications. When a stop bit
is received, the UART will generate an interrupt only if the extra bit is logic 1 (RBX = 1) signifying an address byte has been received. In
the UART interrupt handler, software will compare the received address with the slave's own assigned address. If the addresses match,
the slave will clear its MCE bit to enable interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave
their MCE bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. Once the entire
message is received, the addressed slave resets its MCE bit to ignore all transmissions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves, thereby enabling
"broadcast" transmissions to more than one slave simultaneously. The master processor can be configured to receive all transmissions
or a protocol can be implemented such that the master/slave role is temporarily reversed to enable half-duplex transmission between
the original master and slave(s).
Master
Device
Slave
Device
TX
RX
RX
TX
Slave
Device
RX
TX
Slave
Device
RX
TX
V+
Figure 20.5. Multi-Processor Mode Interconnect Diagram
20.3.7 LIN Break and Sync Detect
UART1 contains dedicated hardware to assist firmware in LIN slave applications. It includes automatic detection of LIN break and sync
fields, and can optionally perform automatic baud rate adjustment based on the LIN 0x55 sync word.
The LIN features are enabled by setting the LINMDE bit in UART1LIN to enable LIN mode. When enabled, both break and sync detec-
tion will be enabled for all incoming data. The circuitry can detect a break-sync sequence in the middle of an incoming data stream and
react accordingly.
The UART will indicate that a break has been detected by setting the BREAKDN flag to 1. Likewise, hardware will set the SYNCD bit if
a valid sync is detected, and the SYNCTO bit will indicate if a sync timeout has occured. The break done and sync flags may be individ-
ually enabled to generate UART1 interrupts by setting the BREAKDNIE, SYNCDIE, and SYNCTOIE bits to 1.
20.3.8 Autobaud Detection
Automatic baud rate detection and adjustment is supported by the UART. Autobaud may be enabled by setting the AUTOBDE bit in the
UART1LIN register to 1. Although the autobaud feature is primarily targeted at LIN applications, it may be used stand-alone as well.
For use in LIN applications, the LINMDE bit should be set to 1. This requires that the UART see a valid LIN break, followed by a delimit-
er, and then a valid LIN sync word (0x55) before adjusting the baud rate. When used in LIN mode, the autobaud detection circuit may
be left on during normal communications.
If LIN mode is not enabled (LINMDE = 0), the autobaud detection circuit will expect to see an 0x55 word on the received data path. The
autobaud detection circuit operates by measuring the amount of time it takes to receive a sync word (0x55), and then adjusting the
SBRL register value according to the measured time, given the current prescale settings.
Important:
Because there is no break involved, when autobaud is used in non-LIN applications, it is important that the autobaud circuit
only be enabled when the receiver is expecting an 0x55 sync byte. The SYNCD flag will be set upon detection of the sync byte, and
firmware should disable auto-baud once the sync detection flag has been set.
The autobaud feature counts the number of prescaled clocks starting from the first rising edge of the sync field and ending on the last
rising edge of the sync field. For 1% accuracy, the prescaler, system clock, and baud rate must be selected such that there are at least
100 clocks per bit. Because the baud rate generator overflows twice per bit, the resulting counts in the SBRLH1:SBRLL1 registers must
be at least 50 (i.e. the maximum value of SBRLH1:SBRLL1 must be 65536 – 50, or 65486 and 0xFFCE.
EFM8UB3 Reference Manual
Universal Asynchronous Receiver/Transmitter 1 (UART1)
silabs.com
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