1-20 Technical Information
When ranges for temperature or voltage are exceeded, an interrupt is activated. The
hardware monitor component connects to the ISA bus as a 8-bit I/O mapped device.
The 1 x 2-pin chassis security header (J0A1) can be connected to a normally-open
mechanical switch on the chassis. See Appendix A, “Connector Pin Assignments,” for the
location and pinouts of the chassis security header.
Interrupt Controller
The interrupt controller operates as an interrupt manager for the entire system environment.
The controller:
accepts requests from peripherals
issues interrupt requests to the processor
resolves interrupt priorities
provides vectors for the processor to determine which interrupt routine to
execute.
The interrupt controller has priority assignment modes that can be reconfigured at any time
during system operations.
The interrupt levels are described in Table 1-7. Interrupt level assignments 0 through 15 are
in order of decreasing priority. See Section 2 for information on using the Setup utility to
change the interrupts.
Table 1-7 Interrupt Level Assignments*
Interrupt Priority
System Resource
NMI
I/O channel check
0
Reserved, interval timer
1
Reserved, keyboard buffer full
2
Reserved, cascade interrupt from slave PIC
3
COM2*
4
COM1*
5
LPT2 (Plug and Play option) / audio / user available
6
Floppy drive
7
LPT1*
8
Real time clock
9
Reserved
* In Plug and Play systems, these interrupts are typical but may vary by configuration.