MAX32600 User’s Guide
Peripheral Management Unit (PMU)
6.3 PMU Programming Details
Interrupt Bit
Source
Cause
2
DAC2 almost empty
Interrupt is set when FIFO level falls below user defined threshold in the
register field,
interrupt self-clears when the FIFO level is above the user defined threshold in
3
DAC3 almost empty
Interrupt is set when FIFO level falls below user defined threshold in the
register field,
interrupt self-clears when the FIFO level is above the user defined threshold in
8
ADC almost full
Interrupt is set when FIFO level is above user defined threshold in the
register field,
interrupt self-clears when the FIFO level falls below the user defined threshold in
16
SPI0 trans_fifo_empty
Interrupt is set when FIFO level falls below the user defined threshold in the
register
field, the interrupt self-clears when the FIFO level is above the user defined threshold in
17
SPI0 rslts_fifo_almost_full
Interrupt is set when the FIFO level is above the user defined threshold in the
, the
interrupt self-clears when the FIFO level falls below the user defined threshold in
18
SPI1 trans_fifo_empty
Interrupt is set when FIFO level falls below the user defined threshold in the
register
field, the interrupt self-clears when the FIFO level is above the user defined threshold in
19
SPI1 rslts_fifo_almost_full
Interrupt is set when the FIFO level is above the user defined threshold in the
, the
interrupt self-clears when the FIFO level falls below the user defined threshold in
20
SPI2 trans_fifo_empty
Interrupt is set when FIFO level falls below the user defined threshold in the
register
field, the interrupt self-clears when the FIFO level is above the user defined threshold in
21
SPI2 rslts_fifo_almost_full
Interrupt is set when the FIFO level is above the user defined threshold in the
, the
interrupt self-clears when the FIFO level falls below the user defined threshold in
22
I2CM0 tx_fifo_empty
Interrupt is set when no data is in FIFO. Interrupt is cleared when FIFO has at least one byte of data.
23
I2CM0 rx_fifo_not_empty
Interrupt is set when FIFO has at least one byte of data. Interrupt is cleared when no data is in FIFO.
24
I2CM1 tx_fifo_empty
Interrupt is set when no data is in FIFO. Interrupt is cleared when FIFO has at least one byte of data.
25
I2CM1 rx_fifo_not_empty
Interrupt is set when FIFO has at least one byte of data. Interrupt is cleared when no data is in FIFO.
26
I2CS0 tx_fifo_empty
Interrupt is set when no data is in FIFO. Interrupt is cleared when FIFO has at least one byte of data.
27
I2CS0 rx_fifo_not_empty
Interrupt is set when FIFO has at least one byte of data. Interrupt is cleared when no data is in FIFO.
28
UART0 tx_fifo_empty
Interrupt is set when no data is in FIFO. Interrupt is cleared when FIFO has at least one byte of data.
29
UART0 rx_fifo_almost_full
Interrupt is set when FIFO level is above the user defined threshold in the
, interrupt
self-clears when FIFO level falls below the user defined threshold in
30
UART1 tx_fifo_empty
Interrupt is set when no data is in FIFO. Interrupt is cleared when FIFO has at least one byte of data.
31
UART1 rx_fifo_almost_full
Interrupt is set when FIFO level is above the user defined threshold in the
, interrupt
self-clears when FIFO level falls below the user defined threshold in
Rev.1.3 April 2015
Maxim Integrated
Page 200