MAX32600 User’s Guide
Memory, Register Mapping, and Access
3.3 Device Memory Instances
3.3.1
Main Program Flash Memory
The main program flash memory is 256KB in size and consists of 2KB (or 512 instruction words) logical pages.
3.3.2
Instruction Cache Memory
The instruction cache is 2KB in size (64 rows x 256 bits) and is used to cache instructions from the main flash memory after they have been descrambled. Note that
the cache is used for instruction fetches only; data fetches from the flash will always go directly to the flash contents, bypassing the Instruction Cache Memory.
3.3.3
Information Block Flash Memory
The information block is a separate flash instance with a single 2KB page. It is used to store trim settings (option configuration and analog trim) as well as other
device-specific information designed to be readable by firmware that needs to be preserved across main application flash load/erase cycles.
3.3.4
System SRAM
The system SRAM is 32KB in size and can be used for general purpose data storage, the ARM system stack, USB data transfers (endpoints), and code execution if
desired.
3.3.5
AES Key and Working Space Memory
The AES key memory and working space for AES operations (including input and output parameters) are located in a dedicated register file memory tied to the AES
engine block. This AES memory is mapped into AHB space for rapid firmware access. In the event of a tamper detection, the AES memory will be automatically
erased by hardware.
3.3.6
Modular Arithmetic Accelerator (MAA) Key and Working Space Memory
The MAA also contains a dedicated memory for key storage, input and output parameters for operations, and working space. It is mapped into the AHB memory
space for ease of loading and unloading.
3.3.7
TPU Memory Secure Key Storage Area
The
MAX32600
contains a specialized 128-bit memory that is designed to preserve a critical key (such as an AES key) even when the device is in the lowest
power-saving state. As long as the RTC power supply is still available, this key will be retained, even if the AES block and the main SRAM are shut down completely.
In the event of a tamper response, this key will be automatically erased by hardware.
Rev.1.3 April 2015
Maxim Integrated
Page 27
