MAX32600 User’s Guide
Memory, Register Mapping, and Access
3.2 Standard Memory Regions
3.2
Standard Memory Regions
A number of standard memory regions are defined for the ARM Cortex-M3 architecture; the use of many of these is optional for the system integrator. At a minimum,
the
MAX32600
, a Cortex-M3-based device, must contain some code and data memory for application code and variable/stack use, as well as certain components
which are part of the instantiated core.
3.2.1
Code Space
The code space area of memory is designed to contain the primary memory used for code execution by the device. This memory area is defined from byte address
range 0x0000_0000 to 0x1FFF_FFFF (0.5GB maximum). Two different standard core bus masters are used by the Cortex-M3 core and ARM debugger to access
this memory area. The I-Code AHB bus master is used for instruction decode fetching from code memory, while the D-Code AHB bus master is used for data fetches
from code memory. This is arranged so that data fetches avoid interfering with instruction execution.
On the
MAX32600
, the code space memory area contains the main program flash memory, which holds the majority of the instruction code that will be executed on
the device. The program flash is mapped from 0x0000_0000 to 0x0003_FFFF. This program memory area must also contain the default system vector table (located
initially at address 0x0000_0000), which contains the reset vector for the device and the initial settings for all system exception handlers and interrupt handlers.
The code space memory on the
MAX32600
also contains the mapping for the flash information block, from 0x0004_0000 to 0x0004_07FF. However, this mapping is
generally only present during production test; it is disabled once the information block has been loaded with valid data and the info block lockout option has been set.
This memory is accessible for data reads only and cannot be used for code execution.
3.2.2
SRAM Space
The SRAM area of memory is intended to contain the primary SRAM data memory of the device and is defined from byte address range 0x2000_0000 to 0x3FFF_
−
FFFF (0.5GB maximum). This memory can be used for general purpose variable and data storage, code execution, and the ARM Cortex-M3 stack.
This memory area contains the main system SRAM on the
MAX32600
, which is mapped from 0x2000_0000 to 0x2000_7FFF.
The entirety of the SRAM memory space on the
MAX32600
is contained within the dedicated ARM Cortex-M3 SRAM bit-banding region from 0x2000_0000 to
0x200F_FFFF (1MB maximum for bit-banding). This means that the entire SRAM can be accessed using bit-banding operations when executing core instructions.
This allows any single bit of 32-bit SRAM location to be set, cleared, or read individually by reading from or writing to a specified location in the bit-banding alias area.
The alias area for the SRAM bit-banding is located beginning at 0x2200_0000 and is a total of 32MB maximum, which allows the entire 1MB bit banding area to be
accessed. Each location in the bit-banding alias area translates into a single bit access (read or write) in the bit-banding primary area. Reading from the location
performs a single bit read, while writing either a 1 or 0 to the location performs a single bit set or clear.
Rev.1.3 April 2015
Maxim Integrated
Page 24