S1R72803F00A
48
EPSON
Address Register Name
Bit Symbol
R/W
Description
H.Rst S.Rst B.Rst
0x08
MainIntEnb
7: EnSubIntStat
R/W
0: Disable
1: Enable
6: EnTxIsoCmp
R/W
0: Disable
1: Enable
5: EnRxDmaCmp
R/W
0: Disable
1: Enable
4: EnTxAsyCmp
R/W
0: Disable
1: Enable
0x00
0x00
–
3: EnHwSBP2Cmp
R/W
0: Disable
1: Enable
2: EnIDE_DmaCmp R/W
0: Disable
1: Enable
1: EnIDE_INTRQ
R/W
0: Disable
1: Enable
0: EnBusReset
R/W
0: Disable
1: Enable
Address Register Name
Bit Symbol
R/W
Description
H.Rst S.Rst B.Rst
0x09
SubIntEnb
7: EnSelfIDdone
R/W
0: Disable
1: Enable
6: EnSelfIDerr
R/W
0: Disable
1: Enable
5: EnHwSBP2Err
R/W
0: Disable
1: Enable
4: EnHwSBP2BRst
R/W
0: Disable
1: Enable
0x00
0x00
–
3: EnLinkIntStat1
R/W
0: Disable
1: Enable
2: EnLinkIntStat0
R/W
0: Disable
1: Enable
1: EnPhyIntStat
R/W
0: Disable
1: Enable
0: EnDmaIntStat
R/W
0: Disable
1: Enable
Address Register Name
Bit Symbol
R/W
Description
H.Rst S.Rst B.Rst
0x0A
(Reserved)
7:
0:
1:
6:
0:
1:
5:
0:
1:
4:
0:
1:
0x00
0x00
–
3:
0:
1:
2:
0:
1:
1:
0:
1:
0:
0:
1:
Main Interrupt Enable Flag Register
This register enables/disables an interrupt factor of the MainIntStat Register.
Setting the corresponding bit to “1” enables an interrupt to the CPU.
Sub-Interrupt Enable Flag Register
This register enables/disables an interrupt factor of the SubIntStat Register.
Setting the corresponding bit to “1” enables an interrupt to the CPU.
