S1R72803F00A
EPSON
61
Address Register Name
Bit Symbol
R/W
Description
H.Rst S.Rst B.Rst
0x31
SBP2Stat
7: FwPause
R
0: Not Firmware Pause
1: FirmWre Pause
6: ErrPause
R
0: Not Error Pause
1: Error Pause
5: NotQuadEnable
R/W
0: Disable
1: Enable
4: WaitPLReady
R
0: Not Ready
1: Ready
0x00
0x00
–
3: HwSBP2Exec
R
0: Stop
1: Execute
2: PTaskExec
R
0: Stop
1: Execute
1: StTaskExec
R
0: Stop
1: Execute
0: TranExec
R
0: Stop
1: Execute
Hardware SBP2 Status Read Register
This register indicates the execution condition of the hardware SBP2.
Bit7 F/W Pause
When the firmware writes “1” at the HwSBP2Ctl. HwSBP2Pause bit during the execution of the HwSBP2Pause:1
(Pause) HwSBP2, this bit becomes “1”. When the firmware writes “1” at the HwSBP2Ctl.HwSBP2Rsum bit
or resets it, it is cleared. Writing to this bit is ignored.
Bit6 Error Pause
When firmware enters the pause state without writing “1” at the HwSBP2Ctl.HwSBP2Pause bit during the
execution of the HwSBP2Pause:1 (Pause) HwSBP2, this bit becomes “1”. It is cleared at the time of Reset.
Writing to this bit is ignored.
Bit5 NotQuadEnable
This bit specifies whether to generate a 0x32 bit 3 NotQuad interrupt by if SegmentLength of PageTableElement
is not the Quad unit during the HwSBP2 process.
NotQuadEnable: 0 (Disable) Set => A NotQuad interrupt is not generated.
NotQuadEnable: 1 (Enable) Set => A NotQuad interrupt is generated.
* Note that this bit does not indicate the status of HwSBP2.
Bit4 Wait Payload Ready
• WaitPLReady:0 (Not Ready) => Payload Domain Not Ready
• WaitPLReady:1 (Ready) => Payload Domain Ready
When the IDE interface has a problem, the payload may not be ready. At that time, perform a recovery
processing by the firmware.
Bit3 HwSBP2Exec
• HwSBP2Exec:0 (Stop) => Indicates the HwSBP2 processing is completed.
• HwSBP2Exec:1 (Execute) => Indicates the HwSBP2 processing is in execution.
It is cleared at the time of Reset. Writing to this bit is ignored..
Bit2 PageTaskExec
• PageTaskExec:0 (Stop) => Indicates a PageTask is completed.
• PageTaskExec:1 (Execute) => Indicates a PageTask is in execution.
It is cleared at the time of Reset. Writing to this bit is ignored..
Bit1 StreamTaskExec
• StreamTaskExec:0 (Stop) => Indicates a StreamTask is completed.
• StreamTaskExec:1 (Execute) => Indicates a StreamTask is in execution.
It is cleared at the time of Reset. Writing to this bit is ignored..
Bit0 TranExec.
• TranExec:0 (Stop) => Indicates a Transaction is completed.
• TranExec:1 (Execute) => Indicates a Transaction is in execution.
It is cleared at the time of Reset. Writing to this bit is ignored..
