When configured for PSTOP1, both the system clock and bus clock are gated. All bus
masters and bus slaves enter Stop mode, but the clock generators in the MCG and the on-
chip regulator in the PMC remain in Run (or VLP Run) mode. Exit from PSTOP1 can be
initiated by a reset or an asynchronous interrupt from a bus master or bus slave.
PSTOP1 is functionally similar to Stop mode, but offers faster wake-up at the expense of
higher power consumption. Another benefit is that it keeps all of the MCG clocks
enabled, which can be useful for some of the asynchronous peripherals that can remain
functional in Stop modes.
7.2.2 Compute Operation
Compute Operation is an execution or compute-only mode of operation that keeps the
CPU enabled with full access to the SRAM and Flash read port, but places all other bus
masters and bus slaves into their stop mode. Compute Operation can be enabled in either
Run mode or VLP Run mode.
NOTE
Do not enter any Stop mode without first exiting Compute
Operation.
Because Compute Operation reuses the Stop mode logic (including the staged entry with
bus masters disabled before bus slaves), any bus master or bus slave that can remain
functional in Stop mode also remains functional in Compute Operation, including
generation of asynchronous interrupts requests. When enabling Compute Operation in
Run mode, module functionality for bus masters and slaves is the equivalent of STOP
mode. When enabling Compute Operation in VLP Run mode, module functionality for
bus masters and slaves is the equivalent of VLPS mode. The MCG, PMC, SRAM, and
Flash read port are not affected by Compute Operation, although the Flash register
interface is disabled.
During Compute Operation, the AIPS peripheral space is disabled and attempted accesses
generate bus errors. The private peripheral space remains accessible during Compute
Operation, including the MCM, NVIC, IOPORT, and SysTick. Although access to the
GPIO registers via the IOPORT is supported, the GPIO port data input registers do not
return valid data since clocks are disabled to the Port Control and Interrupt modules. By
writing to the GPIO port data output registers, it is possible to control those GPIO ports
that are configured as output pins.
Compute Operation is controlled by the CPO register in the MCM (MCM_CPO), which
is only accessible to the CPU. Setting or clearing MCM_CPO[CPOREQ] initiates entry
or exit into Compute Operation. Compute Operation can also be configured to exit
Clocking modes
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
106
Freescale Semiconductor, Inc.
