Table 3-4. ARM Cortex-M0+ parameter settings (continued)
Parameter
Verilog name
Value
Description
Vector Table Offset Register
VTOR
1 = Present
Implements relocation of exception vector
table
WIC Support
WIC
1 = Present
Implements WIC interface
WIC Requests
WICLINES
34
Exact number of wake-up IRQs is 34
Watchpoints
WPT
2
Implements two watchpoints
For details on the ARM Cortex-M0+ processor core, see the ARM website:
.
3.3.1.2 Buses, interconnects, and interfaces
The ARM Cortex-M0+ core has two bus interfaces:
• Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to
peripherals and all system memory, which includes flash memory and RAM
• Single 32-bit I/O port bus interfacing to the GPIO with 1-cycle loads and stores
3.3.1.3 System tick timer
The CLKSOURCE field in SysTick Control and Status register selects either the core
clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock (when
CLKSOURCE = 0). Because the timing reference is a variable frequency, the TENMS
field in the SysTick Calibration Value Register is always 0.
3.3.1.4 Debug facilities
This device supports standard ARM 2-pin SWD debug port.
3.3.1.5 Core privilege levels
The core on this device is implemented with both privileged and unprivileged levels. The
ARM documentation uses different terms than this document to distinguish between
privilege levels.
If you see this term...
it also means this term...
Privileged
Supervisor
Unprivileged or user
User
Chapter 3 Chip Configuration
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
Freescale Semiconductor, Inc.
41
