29.4.10.3 SPTEF
SPTEF occurs when the SPI transmit buffer is ready to accept new data.
After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing
process that is described in the SPI Status Register details.
29.4.10.4 SPMF
SPMF occurs when the data in the receive data buffer is equal to the data in the SPI
Match Register.
29.4.10.5 Asynchronous interrupt in low-power modes
When the CPU is in Wait mode or Stop mode and the SPI module receives a
transmission, the SPI module can generate an asynchronous interrupt to wake the CPU
from the low power mode. The module generates the asynchronous interrupt only when
all of the following conditions apply:
1. C1[SPIE] is set to 1.
2. The CPU is in Wait mode—in which case C2[SPISWAI] must be 1—or in Stop
mode where the peripheral bus clock is stopped but internal logic states are retained.
3. The SPI module is in slave mode.
4. The received transmission ends.
After the interrupt wakes the CPU and the peripheral bus clock is active again, the SPI
module copies the received data from the shifter into the Data register and generates flags
signals. During the wakeup phase, a continuous transmission from a master would
destroy the first received data.
29.5 Initialization/application information
This section discusses an example of how to initialize and use the SPI.
29.5.1 Initialization sequence
Before the SPI module can be used for communication, an initialization procedure must
be carried out, as follows:
Chapter 29 Serial Peripheral Interface (SPI)
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
Freescale Semiconductor, Inc.
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