29.2.4 SS — Slave Select
When the SPI is enabled as a slave, this pin is the low-true slave select input. When the
SPI is enabled as a master and mode fault enable is off (MODFEN is 0), this pin is not
used by the SPI and reverts to other functions (based on chip configuration). When the
SPI is enabled as a master and MODFEN is 1, the slave select output enable bit
determines whether this pin acts as the mode fault input (SSOE is 0) or as the slave select
output (SSOE is 1).
Memory Map and Register Descriptions
The SPI has 8-bit registers to select SPI options, to control baud rate, to report SPI status,
to hold an SPI data match value, and for transmit/receive data.
SPI memory map
Address
offset (hex)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
0
4007_6000 SPI Control Register 1 (SPI0_C1)
8
R/W
04h
1
4007_6001 SPI Control Register 2 (SPI0_C2)
8
R/W
00h
2
4007_6002 SPI Baud Rate Register (SPI0_BR)
8
R/W
00h
3
4007_6003 SPI Status Register (SPI0_S)
8
R
20h
5
4007_6005 SPI Data Register (SPI0_D)
8
R/W
00h
7
4007_6007 SPI Match Register (SPI0_M)
8
R/W
00h
29.3.1 SPI Control Register 1 (SPIx_C1)
This read/write register includes the SPI enable control, interrupt enables, and
configuration options.
Address: 4007_6000h base + 0h offset = 4007_6000h
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
1
0
0
29.3
Memory Map and Register Descriptions
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
448
Freescale Semiconductor, Inc.
