System Interface Unit (SIU)
MPC5553/MPC5554 Microcontroller Reference Manual,
Rev. 5
6-6
Freescale Semiconductor
6.2.1.5
I/O Pin Weak Pullup Reset Configuration Pin (WKPCFG)
The WKPCFG pin is applied at the assertion of the internal reset signal (indicated by the assertion of
RSTOUT), and is sampled 4 clock cycles before the negation of the RSTOUT pin. The value is used to
configure whether the eTPU and eMIOS pins are connected to internal weak pullup or weak pulldown
devices after reset. The value latched on the WKPCFG pin at reset is stored in the reset status register
(SIU_RSR), and is updated for all reset sources except the debug port reset and software external reset.
The setting of the WKPCFG pin must be valid until the negation of RSTOUT.
6.2.1.6
External Interrupt Request Input Pins (IRQ[0:15])
The MPC5554 uses 16 interrupt request signals IRQ[0:15]; the MPC5553 uses 15 interrupt request signals
IRQ[0:5,7:15] to connect to the SIU IRQ inputs. SIU_ETISR select register 1 is used to select the input
pins for the IRQs.
The digital filter length field in the IRQ digital filter register (SIU_IDFR) specifies the minimum number
of system clocks the IRQ signals must hold a logic level to produce a valid state change. Each IRQ has a
counter that increments at the system clock rate to count the number of transitions between the rising- and
falling-edge events. To enable an IRQ counter, enable the rising- or falling-edge event for the IRQ. When
the number of transitions between the rising-edge and falling-edge events equal the value specified in the
digital filter length field in the SIU_IDFR register, the current IRQ filtered state is latched. If the previous
filtered state does not match the current filtered state, and the rising- or falling-edge event is enabled, the
IRQ flag bit in the external interrupt status register (SIU_EISR) is set to 1. For example, if the previous
filtered state was logic zero, and the current latched state is logic one, and the rising-edge event is enabled
for the IRQ signal, the IRQ flag bit is set to 1.
When the IRQ counter is not enabled, the state of the IRQ signal is held in the current and previous state
latches. The IRQ counter operates independently of the IRQ flag bit or overrun flag bit. Clearing the IRQ
flag bit or the overrun flag bit does not clear or reload the IRQ counter.
Enable rising- or falling-edge events by setting bits in the SIU_IREER or the SIU_IFEER. SIU_IREER
and SIU_IFEER can be configured such that only rising-edge events can set flag bits, or only falling-edge
events can set flag bits, or both rising- and falling-edge events can set flag bits. Refer to
Section 6.3.1.4,
“External Interrupt Status Register (SIU_EISR)
” for more information about the external interrupt
mechanism.
6.2.1.6.1
External Interrupts
The IRQ[
n
] pins map to 16 independent interrupt request outputs from the SIU. An interrupt request is
asserted when the corresponding IRQ flag bit is set in the External Interrupt Status Register (SIU_EISR)
with the corresponding DMA/interrupt request enable bit set in the DMA/interrupt request enable register
(SIU_DIRER) and the corresponding DMA/interrupt select bit cleared in the DMA/interrupt request select
register (SIU_DIRSR). The IRQ flag bit is set when an event as defined by the IRQ rising-edge event
enable register (SIU_IREER) occurs on the corresponding IRQ[
n
] pin.
Summary of Contents for MPC5553
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