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Freescale Semiconductor MPC5553, Reference Manual

The Freescale Semiconductor MPC5553 is a powerful microcontroller designed for automotive and industrial applications. For detailed information on how to use this product, download the Reference Manual for free from 88.208.23.73:8080. This manual provides all the necessary information to optimize the performance of your MPC5553.

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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5

19-24

Freescale Semiconductor

 

4

CFUFn

CFIFO underflow flag n. Indicates an underflow event on CFIFOn. CFUFn is set when 
CFIFOn is in the TRIGGERED state and it becomes empty. No commands will be 
transferred from an underflowing CFIFO, nor will command transfers from lower priority 
CFIFOs be blocked. When CFUIEn (see Section 19.3.2.7) and CFUFn are both asserted, 
the eQADC generates an interrupt request.
Apart from generating an independent interrupt request for a CFIFOn underflow event, the 
eQADC also provides a combined interrupt at which the result FIFO overflow interrupt, the 
command FIFO underflow interrupt, and the command FIFO trigger overrun interrupt 
requests of all CFIFOs are ORed. When RFOIEn, CFUIEn, and TORIEn are all asserted, 
this combined interrupt request is asserted whenever one of the following 18 flags 
becomes asserted: RFOFn, CFUFn, and TORFn (assuming that all interrupts are 
enabled). See 

Section 19.4.7, “eQADC eDMA/Interrupt Request

,” for details. Writing a 1 

clears CFUFn. Writing a 0 has no effect.
0 No CFIFO underflow event occurred
1 A CFIFO underflow event occurred

5

SSSn

CFIFO single-scan status bit n. When asserted, enables the detection of trigger events for 
CFIFOs programmed into single-scan level- or edge-trigger mode, and works as trigger for 
CFIFOs programmed into single-scan software-trigger mode. Refer to 

Section 19.4.3.5.2, 

“Single-Scan Mode

,” for further details. The SSSn bit is set by writing a 1 to the SSEn bit 

(see Section 19.3.2.6). The eQADC clears the SSSn bit when a command with an asserted 
EOQ bit is transferred from a CFIFO in single-scan mode, when a CFIFO is in single-scan 
level-trigger mode and its status changes from the TRIGGERED state due to the detection 
of a closed gate, or when the value of the CFIFO operation mode MODEn (see Section 
19.3.2.6) is changed to disabled. Writing to SSSn has no effect. SSSn has no effect in 
continuous-scan or in disabled mode.
0 CFIFO in single-scan level- or edge-trigger mode will ignore trigger events, or CFIFO in 

single-scan software-trigger mode is not triggered.

1 CFIFO in single-scan level- or edge-trigger mode will detect a trigger event, or CFIFO in 

single-scan software-trigger mode is triggered.

6

CFFFn

CFIFO fill flag n. CFFFn is set when the CFIFOn is not full. When CFFEn (see Section 
19.3.2.7) and CFFFn are both asserted, an interrupt or an eDMA request will be generated 
depending on the status of the CFFSn bit. When CFFSn is negated (interrupt requests 
selected), software clears CFFFn by writing a 1 to it. Writing a 0 has no effect. When 
CFFSn is asserted (eDMA requests selected), CFFFn is automatically cleared by the 
eQADC when the CFIFO becomes full.
0 CFIFOn is full.
1 CFIFOn is not full.
Note:  When generation of interrupt requests is selected (CFFSn=0), CFFFn must only be 
cleared in the ISR after the CFIFOn push register is accessed.

Note:  CFFFn should not be cleared when CFFSn is asserted (eDMA requests selected).

7–11

—

Reserved.

Table 19-12. EQADC_FISRn Field Descriptions (Continued)

Bits

Name

Description

Summary of Contents for MPC5553

Page 1: ..._RM Rev 5 1 03 2012 This is the MPC5553 5554 Microcontroller Reference Manual set consisting of the following files MPC5553 5554 Reference Manual Addendum Rev 3 MPC5553 5554 Microcontroller Reference...

Page 2: ...5554 Microcontroller Reference Manual order number MPC5553_MPC5554_RM For convenience the addenda items are grouped by revision Please check our website at http www freescale com for the latest update...

Page 3: ...pin for 416 package from J23 to N C Table 2 2 Page 2 33 Change VDDEH10 pin for 416 package from D14 to N C Table 2 Revision History Table Rev Number Substantive Changes Date of Release 1 0 Changes in...

Page 4: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 Freescale Semiconductor 1 MPC5553 5554 Microcontroller Reference Manual Devices Supported MPC5553 MPC5554 MPC5553_MPC5554_RM Rev 5 December 2011...

Page 5: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 2 Freescale Semiconductor...

Page 6: ...AM 1 17 1 5 13 eMIOS 1 17 1 5 14 eTPU 1 17 1 5 15 eQADC 1 18 1 5 16 DSPI 1 18 1 5 17 eSCI 1 18 1 5 18 FlexCAN 1 19 1 5 19 NDI 1 19 1 5 20 JTAGC 1 19 1 5 21 FEC MPC5553 Only 1 19 1 5 22 Calibration Bus...

Page 7: ...2 66 2 6 Revision History 2 67 Chapter 3 e200z6 Core Complex 3 1 Introduction 3 1 3 1 1 Block Diagram 3 2 3 1 2 Overview 3 2 3 1 3 Features 3 3 3 1 4 Microarchitecture Summary 3 5 3 2 Core Registers a...

Page 8: ...Chapter 5 Peripheral Bridge PBRIDGE_A PBRIDGE_B 5 1 Introduction 5 1 5 1 1 Block Diagram 5 1 5 1 2 Overview 5 1 5 1 3 Features 5 3 5 1 4 Modes of Operation 5 3 5 2 External Signal Description 5 4 5 3...

Page 9: ...2 1 Register Descriptions 7 4 7 3 Functional Description 7 8 7 3 1 Overview 7 8 7 3 2 General Operation 7 8 7 3 3 Master Ports 7 9 7 3 4 Slave Ports 7 9 7 3 5 Priority Assignment 7 10 7 3 6 Arbitrati...

Page 10: ...10 2 10 1 2 Overview 10 2 10 1 3 Features 10 5 10 1 4 Modes of Operation 10 5 10 2 External Signal Description 10 7 10 3 Memory Map Register Definition 10 8 10 3 1 Register Descriptions 10 10 10 4 Fu...

Page 11: ...2 Overview 12 3 12 1 3 Features 12 3 12 1 4 Modes of Operation 12 4 12 2 External Signal Description 12 6 12 2 1 Detailed Signal Descriptions 12 7 12 2 2 Signal Function Direction by Mode 12 11 12 3...

Page 12: ...erview 14 3 14 1 3 Features 14 4 14 2 Modes of Operation 14 4 14 2 1 Full and Half Duplex Operation 14 4 14 2 2 Interface Options 14 4 14 2 3 Address Recognition Options 14 5 14 2 4 Internal Loopback...

Page 13: ...n 15 1 15 2 1 Normal Functional Mode 15 1 15 2 2 Standby Mode 15 1 15 3 External Signal Description 15 2 15 4 Memory Map Register Definition 15 2 15 4 1 Register Descriptions 15 2 15 5 Functional Desc...

Page 14: ...rations on Changing a UC Mode 17 65 17 5 2 Generating Correlated Output Signals 17 65 17 5 3 Time Base Generation 17 65 17 6 Revision History 17 67 Chapter 18 Enhanced Time Processing Unit eTPU 18 1 I...

Page 15: ...tiplexing 19 92 19 4 7 eQADC eDMA Interrupt Request 19 96 19 4 8 eQADC Synchronous Serial Interface SSI Submodule 19 99 19 4 9 Analog Submodule 19 103 19 5 Initialization Application Information 19 10...

Page 16: ...20 64 20 5 2 Baud Rate Settings 20 65 20 5 3 Delay Settings 20 66 20 5 4 MPC5xx QSPI Compatibility with the DSPI 20 67 20 5 5 Calculation of FIFO Pointer Addresses 20 68 20 6 Revision History 20 69 Ch...

Page 17: ...2 24 22 4 3 Receive Process 22 25 22 4 4 Message Buffer Handling 22 26 22 4 5 CAN Protocol Related Features 22 27 22 4 6 Modes of Operation Details 22 30 22 4 7 Interrupts 22 31 22 4 8 Bus Interface 2...

Page 18: ...4 JTAGC Instructions 24 9 24 4 5 Boundary Scan 24 11 24 5 Initialization Application Information 24 11 24 6 Revision History 24 12 Chapter 25 Nexus Development Interface 25 1 Introduction 25 1 25 1 1...

Page 19: ...ccess Address RWA 25 38 25 11 6 Watchpoint Trigger Register WT 25 39 25 11 7Data Trace Control Register DTC 25 40 25 11 8Data Trace Start Address Registers 1 and 2 DTSAn 25 41 25 11 9Data Trace End Ad...

Page 20: ...C5554 Calibration Bus Implementation B 5 B 3 2 MPC5553 Calibration Bus Implementation B 5 B 4 Signals and Pads B 5 B 4 1 CAL_CS 0 2 3 Calibration Chip Selects 0 2 3 MPC5553 Only B 5 B 4 2 Pad Ring B 6...

Page 21: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 xvi Freescale Semiconductor...

Page 22: ...ry can hold instructions and data The external bus interface has been designed to support most of the standard memories used with the MPC5xx family The complex I O timer functions of the MPC5500 famil...

Page 23: ...d from the SIU External interrupts and reset control are also found in the SIU The internal multiplexer submodule SIU_DISR provides multiplexing of eQADC trigger sources daisy chaining the DSPIs and e...

Page 24: ...xus Interface External Master Interface eTPU 32 channel System Bus Integration Boot Assist Module MPC5500 Device Module Acronyms CAN Controller area network FlexCAN DSPI Deserial serial peripheral int...

Page 25: ...External Master Interface System Bus Integration Boot Assist Module MPC5500 Device Module Acronyms CAN Controller area network FlexCAN DSPI Deserial serial peripheral interface eDMA Enhanced direct m...

Page 26: ...s Selectable slew rate control External bus and Nexus pins support 1 62V 3 6V operation Selectable drive strength control Unused pins configurable as GPIO Designed with EMI reduction techniques Freque...

Page 27: ...the MPC5553 5 slave ports 32 bit address bus 64 bit data bus Simultaneous accesses from different masters to different slaves there is no clock penalty when a parked master accesses a slave Enhanced d...

Page 28: ...address bus without transfer size indication 324 BGA 16 bit data bus 20 bit address bus configurable to 24 bit address bus 208 MAPBGA no external bus Selectable drive strengths through pad control in...

Page 29: ...C5553 8 way set associative unified instruction and data cache in the MPC5554 2 way set associative unified instruction and data cache in the MPC5553 On chip internal static RAM SRAM 64 kilobyte gener...

Page 30: ...0 ksamples s 8 bit accuracy at 800 ksamples s Supports six FIFO queues with fixed priority Queue modes with priority based preemption initiated by software command internal eTPU and eMIOS or external...

Page 31: ...rchitecture core and eTPU engines through Nexus class 3 some Class 4 support Data trace of eDMA accesses Read and write access Configured via the IEEE 1149 1 JTAG port High bandwidth mode for fast mes...

Page 32: ...tatus Large on chip transmit and receive Fifes to support a variety of bus latencies Retransmission from the transmit FIFO after a collision Automatic internal flushing of the receive FIFO for runts a...

Page 33: ...2 bit6 32 bit6 32 bit6 Address Bus 24 24 24 24 267 267 267 Calibration Bus Yes Yes Partial No Yes Yes Yes Direct Memory Access DMA 32 channel 32 channel 32 channel 64 channel 32 channel 64 channel 32...

Page 34: ...3 Interrupt Controller 178 channel 210 channel 210 channel 300 channel 231 channel 329 channel 281 channel Analog to Digital Converter eQADC 40 channel 40 channel 40 channel 40 channel 40 channel 40...

Page 35: ...s such as move integer and floating point compare arithmetic and logical instructions and provide a mechanism for testing and branching Vectored and auto vectored interrupts are supported by the CPU V...

Page 36: ...quest is software configurable When multiple tasks share a resource coherent accesses to that resource must be supported The INTC supports the priority ceiling protocol for coherent accesses By provid...

Page 37: ...edicated flash memory array controller The FBIU supports a 64 bit data bus width at the system bus port and a 256 bit read data interface to flash memory The FBIU contains two 256 bit prefetch buffers...

Page 38: ...ory with either no arbitration or external arbitration Serial boot loading a program is downloaded into RAM via eSCI or the FlexCAN and then executed The BAM also reads the reset configuration halfwor...

Page 39: ...FIFOs and the system memory which is external to the eQADC 1 5 16 DSPI The deserial serial peripheral interface DSPI module provides a synchronous serial interface for communication between the MCU a...

Page 40: ...to provide development support as per the IEEE ISTO 5001 2003 standard The development support provided includes program trace data trace watchpoint trace ownership trace run time access to the MCU s...

Page 41: ...the two buses come out on two completely independent sets of pads The calibration bus memory controller supports single data rate SDR non burst mode flash SRAM and asynchronous memories In addition t...

Page 42: ...ytes 32 Kbytes Internal SRAM Array 0x4001_0000 0xBFFF_FFFF 2048Mbytes 64 Kbytes N A Reserved Bridge A Peripherals 0xC000_0000 0xC3EF_FFFF 63 M N A Reserved 0xC3F0_0000 0xC3F0_3FFF 16 K Bridge A Regist...

Page 43: ...0xFFF4_C000 0xFFF4_FFFF 16 K N A Fast Ethernet Controller FEC 2 MPC5553 Only 0xFFFC_0000 0xFFF4_FFFF 15 K N A Reserved MPC5554 Only 0xFFF5_0000 0xFFF7_FFFF 192 K N A Reserved 0xFFF8_0000 0xFFF8_3FFF 1...

Page 44: ...FF Table 1 3 External to Internal Memory Map Translation Table for Slave Mode Ext Addr 8 11 1 1 Only the lower 24 address signals addr 8 31 are available off chip Internal Addr 0 11 Size bytes Interna...

Page 45: ...the slave FLASH is not accessible by an external master Table 1 5 MPC5500 Family Master Memory Map Multi Master Mode Base Address Size bytes Use On Chip 0x0000_0000 2 Mbytes MPC55545 1 5 Mbytes MPC55...

Page 46: ...ded section for Calibration interface In Features List beefed up the section titled MPC5553 Specific Modules by adding more information about the FEC In the MPC5553 Specific Modules section added a se...

Page 47: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 1 26 Freescale Semiconductor...

Page 48: ...his chapter describes the signals of the MPC5553 and the MPC5554 that connect off chip It includes a table of signal properties detailed descriptions of signals and the I O pin power ground segmentati...

Page 49: ...MA 0 _SDS AN 13 _MA 1 _SDO AN 14 _MA 2 _SDI AN 15 _FCK AN 16 31 AN 32 39 ETRIG 0 _GPIO 111 ETRIG 1 _GPIO 112 VRH VRL REFBYPC TCRCLKA_IRQ 7 _GPIO 113 ETPUA 0 3 _ETPUA 12 15 _GPIO 114 117 ETPUA 4 7 _ETP...

Page 50: ...S_MA 0 _AN 12 SDO_MA 1 _AN 13 SDI_MA 2 _AN 14 FCK_AN 15 AN 16 39 TCRCLKA_IRQ 7 _GPIO 113 ETPUA 0 3 _ETPUA 12 15 _GPIO 114 117 ETPUA 4 7 _ETPUA 16 19 _GPIO 118 121 ETPUA 8 11 _ETPUA 20 23 _GPIO 122 125...

Page 51: ...al function is not always valid for all devices As shown in Figure 2 3 when the primary signal function is not available on the device a dash appears in the following signal table columns signal funct...

Page 52: ...TCFG_ GPIO 210 Reset Configuration Input General Purpose I O P G I I O VDDEH6 S RSTCFG Up Up Y28 V26 P22 BOOTCFG 0 _10 IRQ 2 _ GPIO 211 Boot Configuration Input External Interrupt Request General Purp...

Page 53: ..._14 FEC_TX_CLK_ CAL_DATA 0 _ GPIO 44 External Data Bus14 Ethernet Transmit Clock Calibration Data Bus General Purpose I O P A A2 G I O I I O I O VDDE3 17 F Up Up15 AF5 AF3 DATA 17 _14 FEC_CRS_ CAL_DAT...

Page 54: ...G I O I I O I O VDDE3 17 F Up Up15 AF6 AD6 DATA 26 _14 FEC_TX_EN_ CAL_DATA 10 _ GPIO 54 External Data Bus14 Ethernet Transmit Enable Calibration Data Bus General Purpose I O P A A2 G I O O I O I O VD...

Page 55: ...O I O VDDE2 F Up Up15 N2 N2 BR_22 CAL_ADDR 10 _ FEC_MDC_ CAL_CS 2 _ GPIO 72 Calibration Address Bus FEC Management Clock Calibration Chip Select General Purpose I O MP A A2 G I O O O I O VDDE3 17 F U...

Page 56: ...ansmit DSPI D Peripheral Chip Select General Purpose I O P A G O O I O VDDEH6 M Up Up W24 V23 P19 K13 CNRXC_ PCSD 4 _ GPIO 88 FlexCAN C Receive DSPI D Peripheral Chip Select General Purpose I O P A G...

Page 57: ...CSB 3 _ GPIO 101 DSPI B Peripheral Chip Select General Purpose I O A G O I O VDDEH6 M Up Up T26 U25 N21 SCKB_29 PCSC 1 _ GPIO 102 DSPI B Clock DSPI C Peripheral Chip Select General Purpose I O P A G I...

Page 58: ...Negative Differential Input P A I I VDDA1 31 AE I AN 5 B9 A8 A9 A7 AN 6 _ DAN3 Single ended Analog Input Positive Differential Input P A I I VDDA1 31 AE I AN 6 G13 D10 D11 D7 AN 7 _ DAN3 Single ended...

Page 59: ...B4 A4 D6 B5 F4 E3 B3 D2 ETRIG 0 1 _ GPIO 111 112 eQADC Trigger Inputs General Purpose I Os P G I I O VDDEH8 S Up Up A16 B16 B16 A16 VRH Voltage Reference High P I VDDA0 31 VDDINT VRH A9 A9 A10 A8 VRL...

Page 60: ...al Purpose I O P A G I O O I O VDDEH1 M WKPCFG WKPCFG G3 H2 G2 J2 ETPUA 20 23 _ IRQ 8 11 _ GPIO 134 137 eTPU A Channel External Interrupt Request General Purpose I O P A G I O I I O VDDEH1 M WKPCFG WK...

Page 61: ...H4 S WKPCFG WKPCFG AH19 M22 AF19 AD18 AB15 Y14 R9 T9 EMIOS 16 23 _ GPIO 195 202 eMIOS Channel General Purpose I O P G I O O I O VDDEH4 S WKPCFG WKPCFG AG19 AF19 AH20 AG20 AG21 L21 AF20 AF21 AE19 AD19...

Page 62: ...13 14 C14 D14 A14 A10 A11 B10 B11 VSSA0 43 Analog Ground Input ADC0 P I VSSINT I VSSA0 A15 B15 A14 B14 V20 A11 VDDA1 43 Analog Power Input P I 5 0 V VDDINT I VDDA1 A5 B7 E8 H12 C7 8 E9 C5 B5 B4 C6 C9...

Page 63: ...P13 R14 T15 N5 P4 R3 T2 VDDE2 External I O Supply Input P I 1 8 3 3 V I VDDE T7 R5 P5 R7 Y5 Y3 AA3 AB3 Y7 AC3 AC5 AB5 T3 T2 T1 V2 W1 2 Y1 2 AA2 AB2 AC2 AD2 3 AD1 AF2 AE3 U3 N1 U5 T5 N3 P1 W3 V3 N2 M1...

Page 64: ...28 B26 C25 D24 E23 K14 K15 K16 K17 L17 M17 N17 B26 C21 D20 E19 F19 J14 E13 VDDEH1 External I O Supply Input P I 3 3 5 0 V I VDDEH N5 M5 G8 M3 L3 L2 H9 M2 K3 K2 G9 L5 J3 J2 G10 K5 H3 K1 H10 J5 G3 J1 H1...

Page 65: ...DEH AF22 AG22 AG23 AH23 AD17 AD21 P21 R22 AD18 AD22 P22 AD19 N21 AD23 N22 AG18 M21 AF18 AH19 M22 AG19 AF19 AH20 AG20 AG21 L21 AF20 AF21 AC20 W14 N9 Table 2 1 MPC5553 Signal Properties Continued Signal...

Page 66: ...A16 B16 B22 D22 VDDEH9 47 External I O Supply Input P I 3 3 5 0 V I VDDEH H15 G15 E16 C16 D14 D15 D12 VDDEH10 External I O Supply Input P I 3 3 5 0 V I VDDEH G11 J7 AD20 V26 C21 H14 K24 T27 P28 N28 R...

Page 67: ...10 P12 14 W4 W19 AA 2 AA21 AB1 AB22 Y3 Y20 A1 B2 C3 D4 D13 C14 B15 A16 N13 P14 R15 T16 N4 P3 R2 T1 G7 10 H7 10 J7 10 K7 10 No Connect NC49 No Connect A17 20 B17 20 C16 19 D16 19 G26 H25 26 J24 26 K23...

Page 68: ...the same bus the CBI uses EBI signals ADDR 12 26 in addition to the CAL_ADDR 10 11 27 30 signals for calibration addressing Set the PA field in the SUI_PCR register to 0b1 to use the CBI or EBI 17 VD...

Page 69: ...must meet the VDDA1 specifications of 4 5 V to 5 25 V for analog input function 48 All pins with pad type pad_fc are driven to the high state if their VDDE segment is powered before VDD33 49 The pins...

Page 70: ...ernal Transfer Size General Purpose I O P G I O I O VDDE2 F Up Up10 R2 P2 T2 U2 RD_WR_ GPIO 62 External Read Write General Purpose I O P G I O I O VDDE2 F Up Up10 U3 T3 BDIP_ GPIO 63 External Burst Da...

Page 71: ...Nexus Ready Output P O VDDE7 F O High RDY High J24 H23 JTAG Test Signals TCK JTAG Test Clock Input P I VDDE7 F TCK Down TCK Down E27 D25 TDI JTAG Test Data Input P I VDDE7 F TDI Up TDI Up E28 D26 TDO...

Page 72: ...neral Purpose I O P A G O O I O VDDEH6 MH Up Up W24 V23 CNRXC_ PCSD 4 _ GPIO 88 FlexCAN C Receive DSPI D Peripheral Chip Select General Purpose I O P A G I O I O VDDEH6 MH Up Up Y26 W24 Table 2 2 MPC5...

Page 73: ...DSPI D Peripheral Chip Select General Purpose I O P A G I O O I O VDDEH6 MH Up Up R24 T24 PCSA 1 _ PCSB 2 _ GPIO 97 DSPI A Peripheral Chip Select DSPI B Peripheral Chip Select General Purpose I O P A...

Page 74: ...se I O P A G O I O I O VDDEH6 MH Up Up M26 R23 eQADC Signals AN 0 _ DAN0 Single Ended Analog Input Positive Differential Analog Input P I VDDA1 18 A I AN 0 C9 B7 AN 1 _ DAN0 Single Ended Analog Input...

Page 75: ...N 15 _19 FCK20 Analog Input eQADC Free Running Clock MP19 G20 I O VDDEH9 MHA21 I AN 15 C16 A15 AN 16 39 Analog Input P I VDDA1 18 VDDA0 18 A I AN n B7 E8 H12 C7 8 E9 C11 B11 H13 E12 C12 B12 A13 E13 C1...

Page 76: ...rpose I O P A G I O O I O VDDEH1 MH WKPCFG WKPCFG K1 J1 ETPUA 17 _ PCSD 2 _ GPIO 131 eTPU A Channel DSPI D Peripheral Chip Select General Purpose I O P A G I O O I O VDDEH1 MH WKPCFG WKPCFG H10 H4 ETP...

Page 77: ...7 H19 K27 G20 K28 J27 J28 M25 M24 L26 L25 L24 K26 L23 K25 K24 J26 K23 J25 J24 H26 H25 G26 ETPUB 16 _ PCSA 1 _ GPIO 163 eTPU B Channel DSPI A Peripheral Chip Select General Purpose I O P A G I O O I O...

Page 78: ...se I O P A G I O I I O VDDEH4 SH WKPCFG WKPCFG AH19 M22 AF19 AD18 EMIOS 16 23 _ ETPUB 0 7 _ GPIO 195 202 eMIOS Channel eTPU B Channel Output Only General Purpose I O P A G I O O I O VDDEH4 SH WKPCFG W...

Page 79: ...pply Input P I 3 3 V VDDINT N A VFLASH W27 U26 VPP 32 Flash Program erase Supply Input P I 5 0 V VDDINT N A VPP W28 T26 VSTBY 33 SRAM Standby Power Input P I 0 8 1 2 V VSTBY N A VSTBY B3 A2 VDD Intern...

Page 80: ...DEH4 AD20 AC20 VDDEH6 External I O High Supply Input P I 3 3 5 0 V VDDEH N A VDDEH6 V26 AA23 J23 VDDEH8 External I O High Supply Input P I 3 3 5 0 V VDDEH N A VDDEH8 C21 D22 VDDEH9 34 External I O Hig...

Page 81: ...n of the primary pin function alternate function or GPIO is determined in the SIU_PCR registers 2 Each line in the signal name column corresponds to a separate signal function on the pin For all devic...

Page 82: ...MP negated 17 The function and state of the FlexCAN A and eSCI A pins after execution of the BAM program is determined by the BOOTCFG 0 1 pins Refer to Table 16 9 for detail on the FlexCAN and eSCI pi...

Page 83: ...LLCFG 0 _IRQ 4 _GPIO 208 are sampled on the negation of the RESET input pin if the RSTCFG pin is asserted at that time The values are used to configure the FMPLL mode of operation The alternate functi...

Page 84: ...chip select output signals These balls can be individually configured as chip selects or GPIO Because ADDR 8 11 is multiplexed to more than one set of balls only assign ADDR 8 11 to one set of balls...

Page 85: ...libration functions are not available on the MPC5554 This pin can be used as a GPIO signal 2 3 3 0 4 External Data Ethernet Transmit Error Calibration Data GPIO DATA 18 _FEC_TX_ER_CAL_DATA 2 _GPIO 46...

Page 86: ...DATA 23 _FEC_TXD 3 _CAL_DATA 7 _GPIO 51 DATA 23 _FEC_TXD 3 _CAL_DATA 7 _GPIO 51 has the external data bus as the primary signal function The FEC transmit data signal is the first alternate function an...

Page 87: ...also be used as a GPIO signal The FEC and calibration signals are mapped to the same ball therefore either the FEC or calibration function can be used but not both The FEC and calibration functions ar...

Page 88: ...ss GPIO BDIP_GPIO 63 BDIP_GPIO 63 has a primary signal function of external burst data in progress This signal indicates that the EBI is currently transferring a burst of data This pin can be used as...

Page 89: ...ternate signal function CAL_CS 0 is only available on the MPC5553 and provides a calibration chip select function The calibration function CAL_CS 0 is not available on the MPC5554 This pin can be used...

Page 90: ...disable the Nexus Auxiliary port for trace After reset the EVTI pin is used to initiate program and data trace synchronization messages or generate a breakpoint 2 3 4 2 Nexus Event Out EVTO EVTO is a...

Page 91: ...ock Input TCK TCK provides the clock input for the on chip test logic 2 3 5 2 JTAG Test Data Input TDI TDI provides the serial test instruction and data input for the on chip test logic 2 3 5 3 JTAG T...

Page 92: ...n can also be used as a GPIO signal 2 3 6 4 FlexCAN B Receive DSPI C Chip Select GPIO CNRXB_PCSC 4 _GPIO 86 CNRXB_PCSC 4 _GPIO 86 has a primary signal function of FlexCAN B receive for the FlexCAN B m...

Page 93: ...eSCI B module The secondary function is a peripheral chip select for the DSPI D module This pin can also be used as a GPIO signal 2 3 8 DSPI Signals Only the MPC5554 has the DSPI A module Therefore a...

Page 94: ...have a DSPI A module the primary signal function PCSA 1 is not available on the MPC5553 The peripheral chip select output for the DSPI B module PCSB 2 is the alternate signal function This pin can al...

Page 95: ...used as a GPIO signal 2 3 8 12 DSPI B Data Output DSPI C Chip Select GPIO SOUTB_PCSC 5 _GPIO 104 SOUTB_PCSC 5 _GPIO 104 is the data output pin for the DSPI B module The alternate function is a chip s...

Page 96: ...e The alternate function is a chip select output slave select input in slave mode for the DSPI C module This pin can also be used as a GPIO signal 2 3 9 eQADC Signals 2 3 9 1 Analog Input Differential...

Page 97: ...e ended analog input to the two on chip ADCs DAN3 is the negative terminal of the differential analog input DAN3 DAN3 to DAN3 2 3 9 9 Analog Input Multiplexed Analog Input AN 8 _ANW AN 8 is an analog...

Page 98: ...d analog to digital conversion accuracy as compared to the AN 0 7 and AN 16 39 analog input pins 2 3 9 15 Analog Input Mux Address 2 eQADC Serial Data In AN 14 _MA 2 _SDI AN 14 _MA 2 _SDI is an analog...

Page 99: ...U A module 0 11 and the alternate functions are for ETPU A module 12 23 The eTPU A alternate function is for output channels only when configured as ETPUA 12 23 the pins function as output only These...

Page 100: ...external interrupt request input for the SIU module This pin can be used by the MPC5554 as a GPIO signal The TCRCLKB primary signal function is used by the eTPU B module that is not available on the M...

Page 101: ...GPIO 192 EMIOS 13 _SOUTD_GPIO 192 has a primary signal function for the eMIOS module output channel The alternate function is the data output for the DSPI D module This pin can be used as a GPIO signa...

Page 102: ...AL is the output pin for an external crystal oscillator 2 3 13 2 Crystal Oscillator Input External Clock Input EXTAL_EXTCLK EXTAL is the input pin for an external crystal oscillator or an external clo...

Page 103: ...YN is the power supply input for the FMPLL 2 3 14 7 Clock Synthesizer Ground Input VSSSYN VSSSYN is the ground reference input for the FMPLL 2 3 14 8 Flash Read Supply Input VFLASH VFLASH is the on ch...

Page 104: ...y input 2 3 14 15 Ground VSS VSS is the ground reference input 2 3 15 I O Power Ground Segmentation Table 2 3 gives the preliminary power ground segmentation of the MPC5553 MCU Table 2 4 gives the pre...

Page 105: ...EMIOS 16 23 _ETPUB 0 7 _GPIO 195 202 VDDEH6 3 3 5 0 V CNTXC_PCSD 3 _GPIO 87 CNRXC_PCSD 4 _GPIO 88 PCSC 1 _GPIO 93 PCSC 2 _GPIO 94 PCSC 5 _GPIO 95 PCSD 2 _GPIO 96 PCSB 2 _GPIO 97 SCKD_GPIO 98 SOUTD_GP...

Page 106: ..._GPIO 82 75 MSEO 1 0 RDY TCK TDI TDO TMS JCOMP TEST VDDSYN 3 3 V XTAL EXTAL_EXTCLK VRC33 3 3 V VRCCTL VDDA0 5 0 V AN 22 35 VRH VRL REFBYPC VDDA1 5 0 V AN 0 _DAN0 AN 1 _DAN0 AN 2 _DAN1 AN 3 _DAN1 AN 4...

Page 107: ...PCSD 1 _GPIO 91 RXDB_PCSD 5 _GPIO 92 SCKA_PCSC 1 _GPIO 93 SINA_PCSC 2 _GPIO 94 SOUTA_PCSC 5 _GPIO 95 PCSA 0 _PCSD 2 _GPIO 96 PCSA 1 _PCSB 2 _GPIO 97 PCSA 2 _SCKD_GPIO 98 PCSA 3 _SIND_GPIO 99 PCSA 4 _S...

Page 108: ...Other Power Segments VPP 4 5 5 25 V4 VFLASH 3 0 3 6 V VDD33 3 0 3 6 V VSTBY 0 9 1 1 V 1 These are nominal voltages VDDE is 1 62 3 6 V VDDEH is 3 0 5 5 V All VDDE voltages are 10 VDDEH voltages are 5 1...

Page 109: ...I C Serialized Input eTPU A Channel Output 15 11 14 10 13 9 12 8 11 7 10 6 9 5 8 4 7 3 6 2 5 1 4 0 3 15 eTPU A ETPUA 0 _ ETPUA 12 _ GPIO 114 CH0 IN EMIOS 0 _ ETPUA 0 _ GPIO 179 CH0 OUT CH9 IN CH9 OUT...

Page 110: ...B connections are given in Table 2 6 and ETPU A to DSPI D in Table 2 7 Although not shown in Figure 2 6 the output channels of ETPUA 16 23 are also connected to the ETPUA 4 11 _ETPUA 16 23 _GPIO 118...

Page 111: ...at the output channels of ETPUB 0 7 can 9 28 28 8 29 29 7 16 6 17 5 18 4 19 3 20 2 21 1 DSPI B serialized input channels 0 1 14 and 15 are connected to EMIOS channels DSPI B serialized output channels...

Page 112: ...ETPUB to DSPI A connections are given in Table 2 8 Figure 2 8 ETPUB 31 0 DSPI A I O Connections Table 2 8 ETPUB 0 15 DSPI A I O Mapping DSPI A Serialized Inputs eTPU B Channel Output 15 0 14 1 13 2 1...

Page 113: ...The output channels of EMIOS 10 13 may be serialized out and the inputs of EMIOS 12 15 may be serialized in The DSPI connections for EMIOS 10 11 are given in Figure 2 9 Figure 2 10 for EMIOS 12 13 an...

Page 114: ...variable n to VDDE and VDDEH Section 2 3 14 12 External I O Supply Input VDDEn and Section 2 3 14 13 External I O Supply Input VDDEHn Added 10 to the description in Section 2 3 14 14 Fixed 3 3 V Inter...

Page 115: ...g FPM in the NPC_PCR Changed footnote 33 in Table 2 1 from 0b000 to 0b00 for analog serial data strobe functions These registers have a 2 bit PA value Changed footnote 20 in Table 2 2 from 0b000 to 0b...

Page 116: ...s part of a family of CPU cores that implement versions built on the Power Architecture embedded category The host processor core of the device complies with the Power Architecture embedded category w...

Page 117: ...two write operations per clock Most integer instructions execute in a single clock cycle Branch target prefetching is performed by the branch target address cache to allow single cycle branches in ma...

Page 118: ...ess calculation adder Branch target prefetching Branch lookahead buffers of depth 2 Load store unit Pipelined operation supports throughput of one load or store operation per cycle 64 bit general purp...

Page 119: ...der for data memory address calculations Pipelined operation supports throughput of one load or store operation per cycle Dedicated 64 bit interface to memory supports saving and restoring of up to tw...

Page 120: ...decode resulting in execution time of three clocks Conditional branches which are not taken execute in a single clock Branches with successful lookahead and target prefetching have an effective execut...

Page 121: ...ows specification of a target register distinct from the two source registers thus preserving the original data for use by other instructions Data is transferred between memory and registers with expl...

Page 122: ...rrupt Vector Offset IVPR SPR 63 Exception Syndrome Machine Check Data Exception Address Syndrome ESR MCSR DEAR SPR 62 SPR 572 SPR 61 Timers Time Base write only Decrementer Control and Status TBL SPR...

Page 123: ...he remaining user level registers are SPRs Note that the Power Architecture provides the mtspr and mfspr instructions for accessing SPRs Integer exception register XER The XER indicates overflow and c...

Page 124: ...r PID also referred to as PID0 This register is provided to indicate the current process or task identifier It is used by the MMU as an extension to the effective address and by external Nexus 2 3 4 m...

Page 125: ...ion after a programmable delay Decrementer auto reload DECAR This register is provided to support the auto reload feature of the Decrementer Timer control register TCR This register controls decrement...

Page 126: ...register provides counter capability for debug functions Cache registers L1 cache configuration register L1CFG0 is a read only register that allows software to query the configuration of the L1 Cache...

Page 127: ...bit in the OnCE Control Register OCR has no effect Power Management The machine check input pin is not supported HID0 EMCP has no effect and MCSR MCP always reads a negated value Machine Check Least...

Page 128: ...MAS0 MAS4 MAS6 and the e200z6 PowerPCTM Core Reference Manual for more details Software can write and read the MMU Assist registers with mtspr move to SPR and mfspr move from SPR instructions These re...

Page 129: ...quential instruction fetches or due to a change in program flow branches and interrupts Data accesses are generated by load store and cache management instructions The instruction fetch branch and loa...

Page 130: ...de SX Supervisor execute permission Allows instruction fetches to access the page and instructions to be executed from the page while in supervisor mode UR User read permission Allows loads and load t...

Page 131: ...in Table 3 3 The MAS1 register is shown in Figure 3 8 MAS1 fields are defined in Table 3 4 0 1 2 3 4 10 11 15 16 26 27 31 Field TLBSEL ESEL NV Reset Undefined on Power Up Unchanged on Reset R W R W S...

Page 132: ...fective address to be translated A TID value of 0 defines an entry as global and matches with all process IDs 16 18 Reserved should be cleared 19 TS Translation address space This bit is compared with...

Page 133: ...s performed 0 Access to this page are not guarded and can be performed before it is known if they are required by the sequential execution model 1 All loads and stores to this page are performed witho...

Page 134: ...MAS4 Hardware Replacement Assist Configuration Register Bits Name Description 0 1 Reserved should be cleared 2 3 TLBSELD Default TLB selected 01 TLB1 ignored by the e200z6 should be written to 01 for...

Page 135: ...s Both instruction and data accesses are performed using a single bus connected to the cache Addresses from the processor to the cache are virtual addresses used to index the cache array The MMU provi...

Page 136: ...wo MPC5553 ways of 128 sets with each line containing 32 bytes four doublewords plus parity of storage Figure 3 14 illustrates the cache organization terminology used the cache line format and cache t...

Page 137: ...pending Accesses from the CPU following delivery of the critical doubleword may be satisfied from the cache hit under fill non blocking or from the linefill buffer if the requested information has bee...

Page 138: ...selected cache set are compared with the tag reference If any one of the tags matches the tag reference and the tag status is valid a cache hit has occurred 4 Virtual address bits A 27 28 are used to...

Page 139: ...FF_FFFC Reset by assertion of RESET Watchdog timer reset control Debug Reset Control Critical input IVOR0 IVOR0 is not supported in the MPC5553 MPC5554 Machine check IVOR 1 ME CSSR 0 1 Machine check e...

Page 140: ...truction translation lookup did not match a valid entry in the TLB Debug IVOR 15 DE IDM CSSR O 1 Debugger when HIDO DAPUEN 0 Caused by Trap Instruction Address Compare Data Address Compare Instruction...

Page 141: ...the fixed interval timer watchdog timer and timer and counter registers refer to the e200z6 PowerPCTM Core Reference Manual and EREF A Reference for Freescale Book E and the e500 core 3 3 6 Signal Pr...

Page 142: ...artially visible to the programmer in that its results do not have to be explicitly read to use them Instead they are always copied into a 64 bit destination GPR specified as part of the instruction T...

Page 143: ...Figures we replaced the following From Undefined on m_por assertion unchanged on p_reset_b assertion To Power Up Unchanged on Reset because m_por and p_reset_b are internal signals In the e200z6 Feat...

Page 144: ...n determining the boot mode The values on the PLLCFG 0 1 pins are latched at the negation of the RSTOUT pin determining the configuration of the FMPLL If the RSTCFG pin is negated during reset the FMP...

Page 145: ...onfiguration pins If the PLL is configured for any other operating mode the RSTOUT signal is asserted for 2400 clocks plus 4 clocks for sampling of the configuration pins See Section 11 1 4 FMPLL Mode...

Page 146: ...e register 4 3 1 1 Reset Status Register SIU_RSR The reset status register SIU_RSR reflects the most recent source or sources of reset This register contains one bit for each reset source A bit set to...

Page 147: ...can also be loaded with a default instead of what is on the associated pin or pins Figure 4 1 Reset Status Register SIU_RSR Table 4 2 SIU_RSR Field Descriptions Bits Name Description 0 PORS Power on r...

Page 148: ...xternal reset has occurred 1 A software external reset has occurred 16 WKPCFG Weak pull configuration pin status 0 WKPCFG pin latched during the last reset was logic 0 and weak pull down is the defaul...

Page 149: ...tically cleared by all reset sources except the software external reset 0 Do not generate a software system reset 1 Generate a software system reset 1 SER Software external reset Writing a 1 to this b...

Page 150: ...ws the reset flow for assertion of the RESET pin Figure 4 6 shows the internal processing of reset for all reset sources 4 4 2 3 1 Power on Reset The power on reset POR circuit is designed to detect a...

Page 151: ...ted Starting at the assertion of the internal reset signal as indicated by assertion of RSTOUT the value on the WKPCFG pin is applied at the same time the PLLCFG 0 1 values are applied if RSTCFG is as...

Page 152: ...d if RSTCFG is asserted The reset controller then waits 4 clock cycles before the negating RSTOUT and the associated bits fields are updated in the SIU_RSR In addition the WTRS bit is set and all othe...

Page 153: ...t does not cause a reset of the MCU the BAM program is not executed the PLLCFG 0 1 BOOTCFG 0 1 and WKPCFG pins are not sampled The SERF bit in the SIU_RSR is set but no other status bits are affected...

Page 154: ...in the SIU Also refer to Chapter 2 Signal Description for information about the WKPCFG pin 4 4 3 3 BOOTCFG 0 1 Pins MCU Configuration In addition to specifying the RCHW location the values latched on...

Page 155: ...ptions for a detailed description of each control bit NOTE Do not configure the RCHW to a 32 bit bus size for devices with only a 16 bit data bus If booting from internal flash or external memory the...

Page 156: ...time out period of 3 x 217 system clock cycles Example For 8 MHz crystal 12MHz system clock 32 7mS time out For 20 MHz crystal 30 MHz system clock 13 1mS time out 6 PS0 Port size Defines the width of...

Page 157: ...mory device enabled by chip select CS0 using either a 16 or 32 bit data bus The lowest address of one of the six low address space LAS blocks in the internal flash memory 2 x 16K 2 x 48K 2 x 64K At th...

Page 158: ...RSTOUT and stored in the reset status register SIU_RSR BOOTCFG 0 1 are latched only if RSTCFG is asserted WKPCFG is not dependent on RSTCFG Table 4 11 MPC5553 MPC5554 Reset Configuration Half Word Sou...

Page 159: ...e to RSTOUT PLLCFG and RSTCFG are 4 clock cycles PLL Locked 24001 clock cycles Don t Care and WKPCFG is treated as 1 during POR assertion PLLCFG RSTCFG and WKPCFG are applied but not latched RSTCFG st...

Page 160: ...cale Semiconductor 4 17 4 4 5 Reset Flow Figure 4 5 External Reset Flow Diagram False True RESET Asserted Wait 2 Clock Cycles False True RESET Asserted Set Latch Wait 8 False True RESET Asserted Set R...

Page 161: ...Applied Not Latched False True Wait 24001 Clock Cycles Latch WKPCFG Pin RSTCFG Asserted Latch BOOTCFG Values Wait 4 Clock Cycles Update Reset Status Register Negate Internal Resets RSTOUT Latch Defau...

Page 162: ...signifies that external bus access is not available in this package PLLCFG 0 and BOOTCFG 1 are always sampled at reset The device does not reset to the crystal reference mode as do the other packages...

Page 163: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 4 20 Freescale Semiconductor...

Page 164: ...module selects for peripheral devices on the slave bus interface 5 1 2 1 Access Protections The PBRIDGE provides programmable access protections for both masters and peripherals It allows the privile...

Page 165: ...D Table XBAR Port XBS port Module Master ID Peripheral Master 0 e200z6 Core CPU 0 e200z6 Nexus 1 Master 1 eDMA 2 Master 2 EBI 3 Master 3 MPC5553 only FEC MPC5553 only 4 Slave 0 FLASH Slave 1 EBI Slave...

Page 166: ...ed to each Supports a pair of slave accesses for 64 bit instruction fetches Provides configurable per module write buffering support Provides configurable per module and per master access protections...

Page 167: ...access control register 1 32 Base 0x0048 PBRIDGE_A_OPACR2 Off platform peripheral access control register 2 32 Base 0x004C Base 0x0053 Reserved Table 5 3 PBRIDGE_B Memory Map Address Register Name Re...

Page 168: ...s field 4 is available only in the MPC5553 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MBW 0 MTR 0 MTW 0 MPL 0 MBW 1 MTR 1 MTW 1 MPL 1 MBW 2 MTR 2 MTW 2 MPL 2 MBW 3 MTR 3 MTW 3 MPL 3 W Reset 0 1 1 1 0 1 1...

Page 169: ...how the privilege level of the Nexus is determined Accesses not forced to user mode by default 0 Accesses from the Nexus are forced to user mode 1 Accesses from the Nexus are not forced to user mode 8...

Page 170: ...5 MPL3 Master privilege level Determines how the privilege level of the EBI is determined Accesses not forced to user mode by default 0 Accesses from the EBI are forced to user mode 1 Accesses from th...

Page 171: ...atibility The type of peripheral designated by each PACR and OPACR access field is shown in Table 5 6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R BW01 SP0 WP0 TP0 BW1 SP1 WP1 TP1 BW2 SP2 WP2 TP2 BW3 SP3 W...

Page 172: ...n Table 5 5 PBRIDGE_x_PACRn and PBRIDGE_x_OPACRn Field Descriptions Bits Name Description 0 4 8 12 16 20 24 28 BWn1 Buffer writes Determines whether write accesses to this peripheral are allowed to be...

Page 173: ...peripheral access is initiated on the slave bus 3 7 11 15 19 23 27 31 TPn Trusted protect Determines whether the peripheral allows accesses from an untrusted master 0 Accesses from an untrusted maste...

Page 174: ...PBRIDGE_B_Base 0x040 0 eQADC 0b0100 1 3 0b0100 42 DSPI_A2 0b0100 5 DSPI_B 0b0100 6 DSPI_C 0b0100 7 DSPI_D 0b0100 PBRIDGE_B_OPACR1 PBRIDGE_B_Base 0x044 0 3 0b0100 4 eSCI_A 0b0100 5 eSCI_B 0b0100 6 7 0...

Page 175: ...pherals for which an error termination from the slave bus will either not occur or is safe to ignore When write buffering is enabled all accesses through the PBRIDGE will still occur in order no bypas...

Page 176: ...stall until it can either be buffered if bufferable or can be initiated If the buffer has valid entries a following read cycle will stall until the buffer is emptied and the read cycle can be complete...

Page 177: ...allow the individual slave peripherals to determine if user mode accesses are allowed In addition peripherals may be designated as write protected The PBRIDGE supports the notion of trusted masters f...

Page 178: ...BRIDGE_x_PACR and Off Platform Peripheral Access Control Registers PBRIDGE_x_OPACR PBRIDGE_x_PACR and PBRIDGE_x_OPACR should be written with a read modify write for code compatibility Table 5 9 Change...

Page 179: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 5 16 Freescale Semiconductor...

Page 180: ...r 6 System Integration Unit SIU 6 1 Introduction This chapter describes the MPC5553 MPC5554 system integration unit SIU which controls MCU reset configuration pad configuration external interrupt gene...

Page 181: ...The reset configuration module contains the external pin boot configuration logic The pad configuration module controls the static electrical characteristics of I O pins The GPIO module provides unif...

Page 182: ...or the MPC5553 Rising or falling edge event detection Programmable digital filter for glitch rejection GPIO GPIO function 214 GPIO I O pins on the MPC5554 177 GPIO pins on the MPC5553 Dedicated input...

Page 183: ...ype Pull Up Down1 1 Internal weak pullup down The reset weak pullup down state is given by the pullup down state for the primary pin function For example the reset weak pullup down state of the BOOTCF...

Page 184: ...3 SIU_GPDIn 6 2 1 4 Boot Configuration Pins BOOTCFG 0 1 The boot configuration pins specify the boot mode initiated by the boot assist module BAM program BOOTCFG 0 1 are input pins that are sampled 4...

Page 185: ...gth field in the SIU_IDFR register the current IRQ filtered state is latched If the previous filtered state does not match the current filtered state and the rising or falling edge event is enabled th...

Page 186: ...rrupt requests 6 2 1 6 4 Edge Detects The IRQ n pins can be used as edge detect pins Edge detect operation is enabled by selecting rising or falling edge events in the IRQ rising edge event enable reg...

Page 187: ...08D6 Base 0x08FF Reserved Base 0x0900 Base 0x0903 SIU_ETISR eQADC trigger input select register 32 Base 0x0904 Base 0x0907 SIU_EIISR External IRQ input select register 32 Base 0x0908 Base 0x090B SIU_D...

Page 188: ...values Figure 6 3 shows the MPC5554 MCU ID register values Address Base 0x0004 Access Read only 0 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R PARTNUM W Reset pin value 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 A...

Page 189: ...watchdog or checkstop reset requests occur on the same clock cycle and a higher priority reset source is not requesting reset see Table 6 5 the reset status bits for all of the requesting resets are s...

Page 190: ...controller has been asserted and no other reset source has been acknowledged since that assertion of the power on reset input except an external reset 1 ERS External reset status 0 The last reset sour...

Page 191: ...s the default setting 17 28 Reserved 29 30 BOOTCFG Reset configuration pin status The BOOTCFG field is used by the BAM program to determine the location of the reset configuration halfword Holds the v...

Page 192: ...software system reset is processed as a synchronous reset The bit is automatically cleared on the assertion of any other reset source except a software external reset 0 Do not generate a software sys...

Page 193: ...pt request flag bits cause assertion of the one interrupt request signal Address Base 0x0014 Access Read Write 16 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0...

Page 194: ...4 EIRE13 EIRE12 EIRE11 EIRE10 EIRE9 EIRE8 EIRE7 EIRE6 EIRE5 EIRE4 EIRE3 EIRE2 EIRE1 EIRE0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6 7 SIU DMA Interrupt Request Enable Register SIU_DIRER Table 6...

Page 195: ...DMA or interrupt request when an edge triggered event occurs on the corresponding IRQ n pin 0 Interrupt request is selected 1 DMA request is selected Address Base 0x0020 Access Read Write 16 31 0 1 2...

Page 196: ...RE4 ORE3 ORE2 ORE1 ORE0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6 10 Overrun Request Enable Register SIU_ORER Table 6 12 SIU_ORER Field Descriptions Register Bit Range Field Name Function 0 15...

Page 197: ...gister Bit Range Field Name Function 0 15 Reserved 16 31 IREEn IRQ rising edge event enable n Enables rising edge triggered events on the corresponding IRQ n pin 0 Rising edge event is disabled 1 Risi...

Page 198: ...ies Table 6 16 describes the SIU_PCR fields NOTE The fields available in a given SIU_PCR depend on the type of pad it controls Refer to the specific SIU_PCR definition All MPC5553 MPC5554 pin names be...

Page 199: ...ption Figure 6 14 shows a sample PCR register with all bit fields displayed Figure 6 14 Register Diagram Description Address Base 0x14 Access Read write 3 11 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1...

Page 200: ...fast I O pad type F 00 10 pF drive strength 01 20 pF drive strength 10 30 pF drive strength 11 50 pF drive strength 10 ODE Open drain output enable Controls output driver configuration for the pads E...

Page 201: ...ices are used for the pad when weak pullup down devices are enabled The WKPCFG pin determines whether pullup or pulldown devices are enabled at reset The WPS bit determines whether weak pullup or pull...

Page 202: ...e PA field to 0b1 in the SIU_PCR12 SUI_PCR26 to use the EBI or CBI Address Base 0x0048 through Base 0x0054 Access Read write 3 11 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 PA1 1 The PA field...

Page 203: ...E to zero to reduce power consumption When configured as GPI set the IBE bit to 1 DSC ODE3 3 When configured as ADDR 12 31 clear the ODE bit to 0 HYS4 4 If external master operation is enabled clear t...

Page 204: ...gisters SIU_PCR28 SIU_PCR59 Refer to Table 6 16 for bit field definitions Address Base 0x0078 through Base 0x00B6 Access Read write 5 11 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 PA OBE1...

Page 205: ...bration only OBE2 2 When configured as DATA 16 FEC_TX_CLK or CAL_DATA 0 the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE3 3 When configured as DATA 16 FEC_TX_CLK CAL_DATA 0 or...

Page 206: ...configured as DATA 17 FEC_CRS or CAL_DATA 1 the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE3 3 When configured as DATA 17 FEC_CRS CAL_DATA 1 or GPO set the IBE bit to 1 to r...

Page 207: ...configured as DATA 18 FEC_TX_ERR or CAL_DATA 2 the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE3 3 When configured as DATA 18 FEC_TX_ERR CAL_DATA 2 or GPO set the IBE bit to 1...

Page 208: ...onfigured as DATA 19 FEC_RX_CLK or CAL_DATA 3 the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE3 3 When configured as DATA 19 FEC_RX_CLK CAL_DATA 3 or GPO set the IBE bit to 1...

Page 209: ...en configured as DATA 20 FEC_TXD 0 or CAL_DATA 4 the OBE bit has no effect When configured as GPO set the OBE to 1 IBE3 3 When configured as DATA 20 FEC_TXD 0 CAL_DATA 4 or GPO set the IBE bit to 1 to...

Page 210: ...configured as DATA 21 FEC_RX_ERR or CAL_DATA 5 the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE3 3 When configured as DATA 21 FEC_RX_ERR CAL_DATA 5 or GPO set the IBE bit to...

Page 211: ...configured as DATA 22 FEC_RXD 0 or CAL_DATA 6 the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE3 3 When configured as DATA 22 FEC_RXD 0 CAL_DATA 6 or GPO set the IBE bit to 1...

Page 212: ...configured as DATA 23 FEC_TXD 3 or CAL_DATA 7 the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE3 3 When configured as DATA 23 FEC_TXD 3 CAL_DATA 7 or GPO set the IBE bit to 1...

Page 213: ...configured as DATA 24 FEC_COL or CAL_DATA 8 the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE3 3 When configured as DATA 24 FEC_COL CAL_DATA 8 or GPO set the IBE bit to 1 to r...

Page 214: ...configured as DATA 25 FEC_RX_DV or CAL_DATA 9 the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE3 3 When configured as DATA 25 FEC_RX_DV CAL_DATA 9 or GPO set the IBE bit to 1 t...

Page 215: ...onfigured as DATA 26 FEC_TX_EN or CAL_DATA 10 the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE3 3 When configured as DATA 26 FEC_TX_EN CAL_DATA 10 or GPO set the IBE bit to 1...

Page 216: ...configured as DATA 27 FEC_TXD 2 or CAL_DATA 11 the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE3 3 When configured as DATA 27 FEC_TXD 2 CAL_DATA 11 or GPO set the IBE bit to 1...

Page 217: ...configured as DATA 28 FEC_TXD 1 or CAL_DATA 12 the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE3 3 When configured as DATA 28 FEC_TXD 1 CAL_DATA 12 or GPO set the IBE bit to 1...

Page 218: ...configured as DATA 29 FEC_RXD 1 or CAL_DATA 13 the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE3 3 When configured as DATA 29 FEC_RXD 1 CAL_DATA 13 or GPO set the IBE bit to 1...

Page 219: ...n configured as DATA 30 FEC_RXD 2 or CAL_DATA 14 the OBE bit has no effect When configured as GPO set the OBE to 1 IBE3 3 When configured as DATA 30 FEC_RXD 2 CAL_DATA 14 or GPO set the IBE bit to 1 t...

Page 220: ...configured as DATA 31 FEC_RXD 3 or CAL_DATA 15 the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE3 3 When configured as DATA 31 FEC_RXD 3 CAL_DATA 15 or GPO set the IBE bit to 1...

Page 221: ...0 0 0 PA OBE1 1 When configured as TSIZ 0 1 the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE2 2 When configured as TSIZ 0 1 or GPO set the IBE bit to 1 to reflect the pin stat...

Page 222: ...efinition PA Field Pin Function 0b0 GPIO 62 0b1 RD_WR Address Base 0x00BE Access Read write 5 11 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 PA OBE1 1 When configured as BDIP the OBE bit h...

Page 223: ...bit field definitions The PA field for the MPC5553 PCR66 PCR67 is given in Table 6 35 Address Base 0x00C0 and Base 0x00C2 Access Read write 5 11 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0...

Page 224: ...rnal bus interface EBI share the same physical bus the MPC5553 uses the OE signal for the CBI as well as the EBI The OE function is not available in the 208 MAP BGA package The GPIO function is the on...

Page 225: ...ODE3 3 When configured as OE clear the ODE bit to 0 HYS4 4 If the external master operation is enabled set the HYS bit to 1 0 0 WPE5 5 Refer to the EBI section for weak pullup settings when configure...

Page 226: ...ct the pin state in the corresponding GPDI register Clear the IBE to 0 to reduce power consumption When configured as GPI set the IBE bit to 1 DSC ODE3 3 When configured as TA and external master oper...

Page 227: ...1 For calibration only Address Base 0x00CE Access Read write 5 11 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 PA OBE1 1 When configured as TEA the OBE bit has no effect When configured as...

Page 228: ...PA1 1 The BR function is not available on the MPC5553 Set the PA field to 0b001 or 0b011 to select the CAL_ADDR 10 signal to use the calibration bus on the MPC5553 OBE2 2 When configured as CAL_ADDR...

Page 229: ...it to 1 to reflect the pin state in the corresponding GPDI register Clearing the IBE bit to 0 reduces power consumption When configured as GPI set the IBE bit to 1 DSC ODE3 3 When configured as BR and...

Page 230: ...ibutes of the BB_GPIO 74 pin Table 6 40 MPC5553 PCR73 PA Field Definition PA Field Pin Function 0b000 GPIO 73 0b001 CAL_ADDR 11 1 0b010 FEC_MDIO 0b011 CAL_ADDR 11 1 0b100 CAL_CS 3 1 1 For calibration...

Page 231: ...ect When configured as GPO set the OBE bit to 1 IBE2 2 When configured as BB or GPO set the IBE bit to 1 to reflect the pin state in the corresponding GPDI register Clear the IBE to 0 to reduce power...

Page 232: ...ction direction and static electrical attributes of the CNTXA_GPIO 83 pin Figure 6 51 CNTXA_GPIO 83 Pad Configuration Register SIU_PCR83 Refer to Table 6 16 for bit field definitions Address Base 0x00...

Page 233: ...0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 PA OBE1 1 When configured as CNRXA the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE2 2 When configured as CNRXA or GPO set t...

Page 234: ...lectrical attributes of the CNRXC_PCSD 4 _GPIO 88 pin Address Base 0x00EC Access Read write 4 7 10 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA1 1 The CNRXB function is not available on the M...

Page 235: ...ect When configured as GPO set the OBE bit to 1 IBE2 2 When configured as CNRXC or PCS or GPO set the IBE bit to 1 to reflect the pin state in the corresponding GPDI register Clear the IBE to 0 to red...

Page 236: ...11 12 13 14 15 R 0 0 0 0 0 PA OBE1 1 When configured as RXDA the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE2 2 When configured as RXDA or GPO set the IBE bit to 1 to reflect...

Page 237: ...RXDB or PCS the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE2 2 When configured as RXDB or PCS or GPO set the IBE bit to 1 to reflect the pin state in the corresponding GPDI r...

Page 238: ...11 12 13 14 15 R 0 0 0 0 PA1 1 The SINA function is only available on the MPC5554 it is not available on the MPC5553 Therefore set the PA field value for 0b01 or 0b11 only on the MPC5554 Valid MPC555...

Page 239: ...it is not available on the MPC5553 Therefore set the PA field value for 0b01 or 0b11 only on the MPC5554 Valid MPC5553 PA settings are 0b10 for the PCSD 2 or 0b00 for GPIO OBE2 2 When configured as PC...

Page 240: ...ot available on the MPC5553 Therefore set the PA field value for 0b01 or 0b11 only on the MPC5554 Valid MPC5553 PA settings are 0b10 for the SCKD or 0b00 for GPIO OBE2 2 When configured as PCSA the OB...

Page 241: ...PCSA 4 function is only available on the MPC5554 it is not available on the MPC5553 Therefore set the PA field value for 0b01 or 0b11 only on the MPC5554 to select PCSCA 4 Valid MPC5553 PA settings a...

Page 242: ...0 0 PA OBE1 1 When configured as SCKB set the OBE bit to 1 for master operation and clear it to 0 for slave operation When configured as GPO set the OBE bit to 1 IBE2 2 When configured as SCKB in slav...

Page 243: ...3 14 15 R 0 0 0 0 PA OBE1 1 When configured as SOUTB or PCS the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE2 2 When configured as SOUTB or PCS or GPO set the IBE bit to 1 to...

Page 244: ...as PCSB 1 the OBE bit has no effect When configured as PCSD 0 set the OBE bit to 1 for master operation and clear it to 0 for slave operation When configured as GPO set the OBE bit to 1 IBE2 2 When c...

Page 245: ...PCS or SINC the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE2 2 When configured as PCS or SINC or GPO set the IBE bit to 1 to reflect the pin state in the corresponding GPDI r...

Page 246: ...1 When configured as PCSB 5 the OBE bit has no effect When configured as PCSC 0 set the OBE bit to 1 for master operation and clear it to 0 for slave operation When configured as GPO set the OBE bit...

Page 247: ...ical attributes of the ETPUA 12 _PCSB 1 _GPIO 126 pin Address Base 0x0122 Access Read write 4 7 10 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 When configured as TCRCLKA or IRQ the OB...

Page 248: ...OBE bit has no effect The OBE bit must be set to 1 for ETPUA or GPIO when configured as outputs IBE2 2 The IBE bit must be set to 1 for ETPUA or GPIO when configured as inputs When configured as PCS E...

Page 249: ...outputs IBE2 2 The IBE bit must be set to 1 for ETPUA or GPIO when configured as inputs When configured as PCS ETPUA or GPO outputs set the IBE bit to 1 to reflect the pin state in the corresponding G...

Page 250: ...bit has no effect The OBE bit must be set to 1 for both ETPUA or GPIO when configured as outputs IBE2 2 The IBE bit must be set to 1 for ETPUA or GPIO when configured as inputs When configured as PCS...

Page 251: ...e OBE bit has no effect The OBE bit must be set to 1 for ETPUA of GPIO when configured as outputs IBE2 2 The IBE bit must be set to 1 for ETPUA or GPIO when configured as inputs When configured as PCS...

Page 252: ...5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 When configured as ETPUA 24 27 or IRQ the OBE bit has no effect The OBE bit must be set to 1 for ETPUA 20 23 or GPIO 134 141 when configured...

Page 253: ...d as ETPUA or PCS the OBE bit has no effect When configured as GPO set the OBE bit to 1 IBE2 2 When configured as ETPUA PCS or GPO set the IBE bit to 1 to reflect the pin state in the corresponding GP...

Page 254: ...0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 When configured as PCS the OBE bit has no effect When configured as ETPUA output or GPO set the OBE bit to 1 IBE2 2 When configured as ETPUA o...

Page 255: ...CR163 NOTE The MPC5553 does not implement PCR163 This register is reserved in the MPC5553 The SIU_PCR163 register controls the pin function direction and static electrical attributes of the ETPUB 16 _...

Page 256: ...bit has no effect IBE2 2 When configured as ETPUB or GPIO outputs or configured as PCS set the IBE bit to 1 to reflect the pin state in the corresponding GPDI register Clear the IBE to 0 to reduce pow...

Page 257: ...s reserved in the MPC5553 The SIU_PCR166 register controls the pin function direction and static electrical attributes of the ETPUB 19 _PCSA 4 _GPIO 166 pin Both the input and output channel of ETPUB...

Page 258: ...outputs When configured as PCS the OBE bit has no effect IBE2 2 When configured as ETPUB or GPIO outputs or configured as PCS set the IBE bit to 1 to reflect the pin state in the corresponding GPDI re...

Page 259: ...ugh Base 0x01B8 Access Read write 4 7 10 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 The OBE bit must be set to 1 for EMIOS 0 9 or GPIO 179 188 when configured as outputs IBE2 2 When...

Page 260: ...7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 The OBE bit must be set to 1 for GPIO 191 when configured as an output IBE2 2 When configured as EMIOS or GPO set the IBE bit to 1 to reflect the pin state...

Page 261: ...only as output channels to the pins Figure 6 107 EMIOS 16 23 _ETPUB 0 7 _GPIO 195 202 Pad Configuration Register SIU_PCR195 SIU_PCR202 Address Base 0x01C2 through Base 0x01C4 Access Read write 4 7 10...

Page 262: ...pe with slew rate control and GPIO 206 207 are fast pad types with drive strength control The PA bit is not implemented for this PCR because GPIO is the only pin function Figure 6 109 GPIO 205 Pad Con...

Page 263: ...l attributes of the PLLCFG 0 _IRQ 4 _GPIO 208 pin Figure 6 111 PLLCFG 0 _IRQ 4 _GPIO 208 Pad Configuration Register SIU_PCR208 Refer to Table 6 16 for bit field definitions Address Base 0x01DC and Bas...

Page 264: ...nction applies only when the RSTCFG pin is asserted during reset Set the PA field to 0b010 for IRQ 5 0b100 for SOUTD and 0b000 for GPIO 209 OBE2 2 When configured as IRQ the OBE bit has no effect When...

Page 265: ...0 0 PA1 1 The BOOTCFG function applies only during reset when the RSTCFG pin is asserted during reset Set the PA field to 0b10 for IRQ 2 3 and clear the PA field to 0b00 for GPIO 211 212 OBE2 2 When c...

Page 266: ...butes of the AN 12 _MA 0 _SDS pin Figure 6 117 AN 12 _MA 0 _SDS Pad Configuration Register SIU_PCR215 Refer to Table 6 16 for bit field definitions The PA field for PCR215 is given in Table 6 41 Addre...

Page 267: ...3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA1 1 Input and output buffers are enabled disabled based on the PA selection The input and output buffer is disabled for the AN 13 function Only the output...

Page 268: ...O Pad Configuration Register SIU_PCR219 Refer to Table 6 16 for bit field definitions Table 6 43 PCR217 PA Field Definition PA Field Pin Function 0b00 SDI 0b01 Reserved 0b10 MA 2 0b11 AN 14 Address Ba...

Page 269: ..._PCR224 SIU_PCR225 Refer to Table 6 16 for bit field definitions 6 3 1 12 112 Pad Configuration Register 226 SIU_PCR226 The SIU_PCR226 register controls the drive strength of the RDY pin Figure 6 124...

Page 270: ...er 229 SIU_PCR229 The SIU_PCR229 register controls the enabling disabling and drive strength of the CLKOUT pin The CLKOUT pin is enabled and disabled by setting and clearing the OBE bit The CLKOUT pin...

Page 271: ...the GPIO pin number with an offset of SIU_BASE 0x0600 The SIU_GPDOn registers are written to by software to drive data out on the external GPIO pin Each register drives a single external GPIO pin whi...

Page 272: ...e state of the output pin 6 3 1 15 eQADC Trigger Input Select Register SIU_ETISR The SIU_ETISR selects the source for the eQADC trigger inputs The eQADC trigger numbers 0 5 specified by TSEL 0 5 corre...

Page 273: ...6 ETPUA 28 EMIOS 14 ETRIG 1 4 4 8 ETPUA 27 EMIOS 13 ETRIG 0 5 5 10 ETPUA 26 EMIOS 12 ETRIG 1 Address Base 0x0900 Access Read write 0 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TSEL5 TSEL4 TSEL3 TSEL2...

Page 274: ...ecifies the input for eQADC trigger 1 00 GPIO 207 01 ETPUA 31 channel 10 EMIOS 11 channel 11 ETRIG 1 pin 10 11 TSEL0 eQADC trigger input select 0 Specifies the input for eQADC trigger 0 00 GPIO 206 01...

Page 275: ...UA 25 pin 10 DSPI_C 13 serialized input ETPUA 9 pin 11 DSPI_D 14 serialized input ETPUA 25 pin 8 9 ESEL11 External IRQ input select 11 Specifies the input for IRQ 11 00 IRQ 11 pin 01 DSPI_B 11 seriali...

Page 276: ...ut EMIOS 10 pin 22 23 ESEL4 External IRQ input select 4 Specifies the input for IRQ 4 00 IRQ 4 pin 01 DSPI_B 4 serialized input ETPUA 19 pin 10 DSPI_C 5 serialized input ETPUA 1 pin 11 DSPI_D 6 serial...

Page 277: ...LB TRIGSELB W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address Base 0x0908 Access Read write 8 31 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R SINSELC SSSELC SCKSELC TRIGSELC SINSELD SSSELD SCKSELD...

Page 278: ..._A trigger input 00 No Trigger 01 PCSB 4 10 PCSC 4 11 PCSD 4 Reserved 8 9 SINSELB DSPI B data input select Specifies the source of DSPI_B data input 00 SINB_PCSC 2 _GPIO 103 pin 01 SOUTA 10 SOUTC 11 S...

Page 279: ...A 4 not available 24 25 SINSELD DSPI D data input select Specifies the source of the DSPI_D data input 00 PCSA 3 _SIND_GPIO 99 pin 01 SOUTA 10 SOUTB 11 SOUTC PCSA 3 and SOUTA not available 26 27 SSSEL...

Page 280: ...to the SIU The match input is asserted if the values in the SIU_CARH and SIU_CBRH as well as the SIU_CARL and SIU_CBRL are equal The MATCH bit is reset by the synchronous reset signal 0 The content of...

Page 281: ...5 Engineering clock division factor Specifies the frequency ratio between the system clock and ENGCLK The ENGCLK frequency is divided by the system clock frequency according to the equation Note Clea...

Page 282: ...appears in the MATCH bit in the SIU_CCR register The SIU_CARH holds the 32 bit value that is compared against the value in the SIU_CBRH register The CMPAH field is read write and is reset by the sync...

Page 283: ...value in the SIU_CARH The CMPBH field is read write and is reset by the synchronous reset signal Address Base 0x098C Access Read write 0 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CMPAL W Reset 0 0 0...

Page 284: ...n Halfword Read of the BAM chapter for detail on the RCHW Table 6 53 defines the boot modes specified by the BOOTCFG 0 1 pins If the RSTCFG pin is asserted during the assertion of RSTOUT except in the...

Page 285: ...an 2 clock cycles the event is latched After the latch is set if the RESET pin is negated before 10 clock cycles elapses the reset controller sets the RGF bit without affecting any of the other bits i...

Page 286: ...multiplexing select registers SIU_ETISR SIU_EIISR and SIU_DISR provide selection of the source of the input for the eQADC external trigger inputs the SIU external interrupts and the DSPI signals that...

Page 287: ...ter SIU_ETISR for the SIU_ETISR TSEL0 SIU_ETISR TSEL5 bit definitions If an ETRIG input is connected to an eTPU or eMIOS channel the external pin used by that channel can be used by the alternate func...

Page 288: ...peripheral chip select PCS and clock SCK The trigger input of the master allows a slave DSPI to trigger a transfer when a data change occurs in the slave DSPI and the slave DSPI is operating in change...

Page 289: ...Freescale Semiconductor Figure 6 145 DSPI Serial Chaining SOUT SOUT SIN SIN PCS 0 SS SCK SCK IN DSPI_A master in MPC5554 DSPI_B slave in MPC5554 SS SCK IN SIN SOUT External SPI device MPC5553 MPC5554...

Page 290: ...conductor 6 111 Figure 6 146 DSPI Parallel Chaining SOUT SOUT SIN SIN PCS 0 SS SCK SCK IN SS SCK IN SIN SOUT External SPI device MPC5553 MPC5554 SIN SCK IN SS SOUT External SPI device MTRIG Trigger DS...

Page 291: ...ction to the PCR registers in Section 6 3 1 12 for clarity Added the following PA field definition tables Table 6 17 through Table 6 44 Figure 6 6 Added w1c write 1 to clear to bits 16 through 31 SIU_...

Page 292: ...e ports 7 1 1 Block Diagram Figure 7 1 shows a block diagram of the crossbar switch Table 7 1 gives the crossbar switch port for each master and slave and the assigned and fixed ID number for each mas...

Page 293: ...ll be granted access to a slave port in round robin fashion based upon the ID of the last master to be granted access A block diagram of the XBAR is shown in Figure 7 1 The XBAR can place each slave p...

Page 294: ...slave port 0 32 Base 0x0004 Base 0x000F Reserved Base 0x0010 XBAR_SGPCR0 General purpose control register for slave port 0 32 Base 0x0014 Base 0x00FF Reserved Base 0x0100 XBAR_MPR1 Master priority reg...

Page 295: ...ority of each master port when operating in fixed priority mode They are ignored in round robin priority mode unless more than one master has been assigned high priority by a slave NOTE Masters must b...

Page 296: ...ster 3 priority Set the arbitration priority for master port 3 on the associated slave port 00 This master has the highest priority when accessing the slave port 01 This master has the 2nd highest pri...

Page 297: ...t being accessed by another master because it will not be parked on any master The XBAR_SGPCR can only be accessed in supervisor mode with 32 bit accesses After the RO read only bit has been set in th...

Page 298: ...fter being written to 1 it can only be cleared by hardware reset This bit is cleared by hardware reset 0 All this slave port s registers can be written 1 All this slave port s registers are read only...

Page 299: ...ates inserted until the targeted slave port can service the master s request The latency in servicing the request will depend on each master s priority level and the responding slave s access time Bec...

Page 300: ...odes is either currently servicing the master or is parked on the master In this case the XBAR will be completely transparent and the master s access will be immediately seen on the slave bus and no a...

Page 301: ...currently has control over the slave port if any The slave port does an arbitration check at every clock edge to ensure that the proper master if any has control of the slave port If the new requesti...

Page 302: ...heck at every clock edge to ensure that the proper master if any has control of the slave port A new requesting master must wait until the end of the fixed length burst transfer before it will be gran...

Page 303: ...of Change Added to Register Descriptions section Please note the difference in numerical values of XBAR Master Port and Master ID as shown in Table 7 1 Changed wording of reserved fields in registers...

Page 304: ...ong in a 64 bit doubleword In this case it is corrected automatically by hardware and no flags or other indication is set that the error occurred A non correctable ECC error is generated when 2 bits i...

Page 305: ...mization Master Control Register MPC5553 Only 32 Base 0x0028 Base 0x0042 Reserved Base 0xFFF4_0000 0x0043 ECSM_ECR ECC configuration register 8 Base 0x0044 Base 0x0046 Reserved Base 0x0047 ECSM_ESR EC...

Page 306: ...gisters in the ECSM is not recommended The values in these registers should be left in their reset state Any change from reset values may cause an unintentional ECSM_SWTIR_SWTIC interrupt 8 2 1 2 ECC...

Page 307: ...e error where the combination of a properly enabled category in the ECSM_ECR and the detection of the corresponding condition in the ECSM_ESR produces the interrupt request The ECSM allows a maximum o...

Page 308: ...pability provides a mechanism to allow testing of the software service routines associated with memory error logging The intent is to generate errors during data write cycles such that subsequent read...

Page 309: ...bit data errors as defined by the bit position specified in ERRBIT 0 6 and the overall odd parity bit continuously on every write operation The normal ECC generation takes place in the RAM controller...

Page 310: ...it specified by this field plus the odd parity bit of the ECC code are inverted The internal SRAM controller follows a vector bit ordering scheme where LSB 0 Errors in the ECC syndrome bits can be gen...

Page 311: ...ry Depending on the state of the ECSM_ECR register an ECC event in the flash causes the address attributes and data associated with the access to be loaded into the ECSM_FEAR ECSM_FEMR ECSM_FEAT and E...

Page 312: ...et U U U U U U U U Reg Addr Base 0x0057 1 U signifies a bit that is uninitialized Figure 8 6 Flash ECC Attributes Register ECSM_FEAT Table 8 8 ECSM_FEAT Field Descriptions Bits Name Description 0 WRIT...

Page 313: ...ECSM_ESR to be asserted The data captured on a multi bit non correctable ECC error is undefined 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R FEDH W Reset U U U U U U U U U U U U U U U U Reg Addr Base 0x58...

Page 314: ...19 20 21 22 23 24 25 26 27 28 29 30 31 R FEDL W Reset U U U U U U U U U U U U U U U U Reg Addr Base 000x5C 1 U signifies a bit that is uninitialized Figure 8 8 Flash ECC Data Low Register ECSM_FEDRL...

Page 315: ...and data associated with the access to be loaded into the ECSM_REAR ECSM_REMR ECSM_REAT and ECSM_REDRs and the appropriate flag RNCE in the ECSM_ESR to be asserted Table 8 11 ECSM_REAR Field Descripti...

Page 316: ...bit non correctable ECC error is undefined Table 8 13 ECSM_REAT Field Descriptions Bits Name Description 0 WRITE Write The reset value of this field is undefined 0 System bus read access 1 System bus...

Page 317: ...the ECSM_ESR to be asserted The data captured on a multi bit non correctable ECC error is undefined 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R REDH W Reset U U U U U U U U U U U U U U U U Reg Addr Base...

Page 318: ...9 of the INTC If properly enabled this INTC vector 9 can cause an external interrupt IVOR4 along with the data storage interrupt IVOR2 To avoid the external interrupt IVOR4 being generated the applic...

Page 319: ...escale Semiconductor 8 4 Revision History Table 8 17 Changes to MPC5553 5554 RM for Rev 5 0 Release Table 8 16 Changes to MPC5553 5554 RM for Rev 4 0 Release Description of Change No changes since the...

Page 320: ...9 1 Chapter 9 Enhanced Direct Memory Access eDMA 9 1 Introduction This chapter describes the MPC5553 MPC5554 s enhanced direct memory access eDMA controller a second generation module capable of perf...

Page 321: ...as been optimized to minimize the required intervention from the host processor It is intended for use in applications where the data size to be transferred is statically known and is not defined with...

Page 322: ...interrupt requests One interrupt per channel optionally asserted at completion of major iteration count Error terminations are enabled per channel and logically summed together to form two optional er...

Page 323: ...Base 0x0018 EDMA_SERQR eDMA set enable request register 8 Base 0x0019 EDMA_CERQR eDMA clear enable request register 8 Base 0x001A EDMA_SEEIR eDMA set enable error interrupt register 8 Base 0x001B EDM...

Page 324: ...r 8 Base 0x0117 EDMA_CPR23 eDMA channel 23 priority register 8 Base 0x0118 EDMA_CPR24 eDMA channel 24 priority register 8 Base 0x0119 EDMA_CPR25 eDMA channel 25 priority register 8 Base 0x011A EDMA_CP...

Page 325: ...36 EDMA_CPR54 eDMA channel 54 priority register 8 Base 0x0137 EDMA_CPR55 eDMA channel 55 priority register 8 Base 0x0138 EDMA_CPR56 eDMA channel 56 priority register 8 Base 0x0139 EDMA_CPR57 eDMA chan...

Page 326: ...e 0x12C0 TCD22 eDMA transfer control descriptor 22 256 Base 0x12E0 TCD23 eDMA transfer control descriptor 23 256 Base 0x1300 TCD24 eDMA transfer control descriptor 24 256 Base 0x1320 TCD25 eDMA transf...

Page 327: ...1580 TCD44 eDMA transfer control descriptor 44 256 Base 0x15A0 TCD45 eDMA transfer control descriptor 45 256 Base 0x15C0 TCD46 eDMA transfer control descriptor 46 256 Base 0x15E0 TCD47 eDMA transfer c...

Page 328: ...up are executed first where priority level 3 in the MPC5554 priority level 1 for the MPC5553 is the highest and priority level 0 is the lowest The group priorities are assigned in the GRPnPRI fields o...

Page 329: ...TCD BITER E_LINK bit All configuration error conditions except scatter gather and minor loop link error are reported as the channel is activated and assert an error interrupt request if enabled When p...

Page 330: ...ame error condition 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R VLD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr Base 0x0004 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30...

Page 331: ...inconsistent with TCD SSIZE 26 DAE Destination address error 0 No destination address configuration error 1 The last recorded error was a configuration error detected in the TCD DADDR field indicatin...

Page 332: ...3 ERQ 52 ERQ 51 ERQ 50 ERQ 49 ERQ 48 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr Base 0x0008 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R ERQ 47 ERQ 46 ERQ 45 ERQ 44 ERQ 43 ERQ 42 ERQ 41 ERQ...

Page 333: ...oth the DMA error indicator and this error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R EEI63 EEI62...

Page 334: ...alue on a register write causes the corresponding bit in the EDMA_ERQRH or EDMA_ERQRL to be cleared Setting bit 1 CERQn provides a global clear function forcing the entire contents of the EDMA_ERQRH a...

Page 335: ...0 0 0 0 0 0 W CERQ 0 6 Reset 0 0 0 0 0 0 0 0 Reg Addr Base 0x0019 Figure 9 9 eDMA Clear Enable Request Register EDMA_CERQR Table 9 7 EDMA_CERQR Field Descriptions Bits Name Description 0 Reserved 1 7...

Page 336: ..._IRQRH or EDMA_IRQRL to disable the interrupt request for a given channel The given value on a register write causes the corresponding bit in the EDMA_IRQRH or EDMA_IRQRL to be cleared Setting bit 1 C...

Page 337: ...given channel The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set Setting bit 1 SSBn provides a global set function forcing all START bi...

Page 338: ...nnels 63 32 while EDMA_IRQRL covers channels 31 00 For the MPC5553 EDMA_IRQRL maps to channels 31 0 EDMA_IRQRH is reserved on the MPC5553 and accessing it will result in a bus error 0 1 2 3 4 5 6 7 R...

Page 339: ...or a single channel can easily be cleared 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R INT 63 INT 62 INT 61 INT 60 INT 59 INT 58 INT 57 INT 56 INT 55 INT 54 INT 53 INT 52 INT 51 INT 50 INT 49 INT 48 W Rese...

Page 340: ...tion indicators setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request are not affected when an error is detected The contents of this register can also b...

Page 341: ...emporarily suspended in favor of starting a higher priority channel After the preempting channel has completed all of its minor loop data transfers the preempted channel is restored and resumes execut...

Page 342: ...n cannot be suspended by a higher priority channel s service request 1 Channel n can be temporarily suspended by the service request of a higher priority channel 1 Reserved 2 3 GRPPRI 0 1 Channel n cu...

Page 343: ...0x1000 32 x n 224 1 Channel to channel Linking on Minor Loop Complete BITER E_LINK 0x1000 32 x n 225 6 Starting Major Iteration Count or Link Channel Number BITER or BITER LINKCH 0x1000 32 x n 231 9...

Page 344: ...Name Description 0 31 0x0 0 31 SADDR 0 31 Source address Memory address pointing to the source data Word 0x0 bits 0 31 32 36 0x4 0 4 SMOD 0 4 Source address modulo 0 Source address modulo feature is d...

Page 345: ...estored to the local memory If the major iteration count is completed additional processing is performed Note The NBYTES value of 0x0000_0000 is interpreted as 0x1_0000_0000 thus specifying a 4 GByte...

Page 346: ...DLAST_SGA 0 31 Last destination address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel scatter gather If scatter gather processing for the cha...

Page 347: ...generates read write sequences until the minor count is exhausted This field forces the eDMA to stall after the completion of each read write access to control the bus request bandwidth seen by the s...

Page 348: ...onding EDMA_ERQH or EDMA_ERQL bit when the current major iteration count reaches zero 0 The channel s EDMA_ERQH or EDMA_ERQL bit is not affected 1 The channel s EDMA_ERQH or EDMA_ERQL bit is cleared w...

Page 349: ...DDR CITER back into the local memory If the major iteration count is exhausted additional processing is performed including the final address pointer updates reloading the TCDn CITER field and a possi...

Page 350: ...r each reference of the larger size As an example if the source size references 16 bit data and the destination is 32 bit data two reads are performed then one 32 bit write TCD local memory Memory con...

Page 351: ...memory Next the TCD memory is accessed and the required descriptor read from the local memory and loaded into the eDMA engine address path channel x y registers The TCD memory is organized 64 bits in...

Page 352: ...ER If the outer major iteration count is exhausted then there are additional operations which are performed These include the final address adjustments and reloading of the BITER field into the CITER...

Page 353: ...e useful metric In this environment the speed of the source and destination address spaces remains important but the microarchitecture of the eDMA also factors significantly into the resulting metric...

Page 354: ...tes The transfer control descriptor local memory read is initiated Cycle 5 6 The first two parts of the activated channel s TCD is read from the local memory The memory width to the eDMA engine is 64...

Page 355: ...for the first channel s service request Assuming zero wait states on the system bus DMA requests can be processed every 9 cycles Assuming an average of the access times associated with slave to SRAM 4...

Page 356: ...alization A typical initialization of the eDMA would have the following sequence 1 Write the EDMA_CR if a configuration other than the default is desired 2 Write the channel priority levels into the E...

Page 357: ...n START Control bit to explicitly start channel when using a software initiated DMA service Automatically cleared by hardware ACTIVE Status bit indicating the channel is currently in execution DONE St...

Page 358: ...he same priority level 4 If group 1 has any service requests those requests will be executed 5 After all of group 1 requests have completed group 0 will be the next active group 6 If Group 0 has a ser...

Page 359: ...ag eQADC_FISR1_RFDF1 3 EQADC FISR1 RFDF1 eQADC Receive FIFO 1 Drain Flag eQADC_FISR2_CFFF2 4 EQADC FISR2 CFFF2 eQADC Command FIFO 2 Fill Flag eQADC_FISR2_RFDF2 5 EQADC FISR2 RFDF2 eQADC Receive FIFO 2...

Page 360: ...DSPIAISR TFFF DSPIA Transmit FIFO Fill Flag DSPIA_SR_RFDF 33 DSPIA SR RFDF DSPIA Receive FIFO Drain Flag eSCIB_COMBTX 34 ESCIB SR TDRE ESCIB SR TC ESCIB SR TXRDY eSCIB combined DMA request of the Tran...

Page 361: ...RS0 52 ETPU CDTRSR_B DTRS0 eTPUB Channel 0 Data Transfer Request Status eTPU_CDTRSR_B_DTRS1 53 ETPU CDTRSR_B DTRS1 eTPUB Channel 1 Data Transfer Request Status eTPU_CDTRSR_B_DTRS2 54 ETPU CDTRSR_B DTR...

Page 362: ...servicing of lower priority channels in the same group 9 5 4 3 Round Robin Group Arbitration Round Robin Channel Arbitration Groups will be serviced as described in Section 9 5 4 2 but this time chann...

Page 363: ...urn to their beginning values TCD CITER TCD BITER 1 TCD NBYTES 16 TCD SADDR 0x1000 TCD SOFF 1 TCD SSIZE 0 TCD SLAST 16 TCD DADDR 0x2000 TCD DOFF 4 TCD DSIZE 2 TCD DLAST_SGA 16 TCD INT_MAJ 1 TCD START...

Page 364: ...E 0 TCD SLAST 32 TCD DADDR 0x2000 TCD DOFF 4 TCD DSIZE 2 TCD DLAST_SGA 32 TCD INT_MAJ 1 TCD START 0 Should be written last after all other fields have been initialized All other TCD fields 0 This woul...

Page 365: ...01c last iteration of the minor loop major loop complete 14 eDMA engine writes TCD SADDR 0x1000 TCD DADDR 0x2000 TCD CITER 2 TCD BITER 15 eDMA engine writes TCD ACTIVE 0 TCD DONE 1 EDMA_IRQRn 1 16 The...

Page 366: ...1 channel has completed the major loop and is idle The best method to test for minor loop completion when using hardware initiated service requests is to read the TCD CITER field and test for a change...

Page 367: ...ing a lower priority channel 9 5 7 Channel Linking Channel linking or chaining is a mechanism where one channel sets the TCD START bit of another channel or itself thus initiating a service request fo...

Page 368: ...ution a coherency model is needed Consider the scenario where the user attempts to execute a dynamic channel link by enabling the TCD MAJOR E_LINK bit at the same time the eDMA engine is retiring the...

Page 369: ...FROM removed eDMA Peak Transfer Rate table TO Added an eDMA Peak Transfer Rates table Table 9 19 with revised values and with columns that show the effect of buffering enabled and disabled Table 9 26...

Page 370: ...e interrupt controller INTC which schedules interrupt requests IRQs from software and internal peripherals to the e200z6 core The INTC provides interrupt prioritization and preemption interrupt maskin...

Page 371: ...sters Flag Bits Priority Select Registers 8 Peripheral Interrupt Requests 3001 Including 22 Reserved1 3081 Priority Arbitrator 3081 Highest Priority Interrupt Requests 3081 Request Selector Lowest Vec...

Page 372: ...upt exception handler whose location is determined by an address derived from special purpose registers IVPR and IVOR4 The interrupt exception handler reads the INTC_IACKR to determine Software IRQs 1...

Page 373: ...ce It also provides 16 priorities so that lower priority ISRs do not delay the execution of higher priority ISRs Because each individual application will have different priorities for each source of i...

Page 374: ...ed to one of 16 priorities Preemption Preemptive prioritized interrupt requests to processor ISR at a higher priority preempts ISRs or tasks at lower priorities Automatic pushing or popping of preempt...

Page 375: ...processor The last actions of the interrupt exception handler must be the write to the end of interrupt register INTC_EOIR Writing to the INTC_EOIR signals the end of the servicing of the interrupt r...

Page 376: ...cription The INTC does not have any direct external MCU signals However there are sixteen external pins which can be configured in the SIU as external interrupt request input pins When configured in t...

Page 377: ...O I O ETPUA 24 26 F1 G3 F3 P ETPUA 24 26 eTPU A channel output only O WKPCFG WKPCFG A IRQ 12 14 External interrupt request I G GPIO 138 140 GPIO I O ETPUA27 F2 P ETPUA 27 eTPU A channel output only O...

Page 378: ...r interrupt register 4 8 Base 0x0025 INTC_SSCIR5 INTC software set clear interrupt register 5 8 Base 0x0026 INTC_SSCIR6 INTC software set clear interrupt register 6 8 Base 0x0027 INTC_SSCIR7 INTC soft...

Page 379: ...does not affect the operation of the write 10 3 1 1 INTC Module Configuration Register INTC_MCR The INTC_MCR is used to configure options of the INTC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0...

Page 380: ...NOTE On some MPC55xx MCUs a store to raise the PRI field which closely precedes an access to a shared resource can result in a non coherent access to that resource unless an mbar or msync followed by...

Page 381: ...n hardware vector mode NOTE In software vector mode the INTC_IACKR must be read before setting MSR EE No synchronization instruction is needed after reading the INTC_IACKR and before setting MSR EE Ta...

Page 382: ...ossible future compatibility write four bytes of all 0 s to the INTC_EOIR Reading the INTC_EOIR has no effect on the LIFO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R VTBA most significant 16 bits W Reset...

Page 383: ...is the flag bit Writing a 1 to CLRn will clear it Writing a 0 to CLRn will have no effect If a 1 is written to a pair SETn and CLRn bits at the same time CLRn will be asserted regardless of whether C...

Page 384: ...hat the access does not cross a 32 bit boundary NOTE The PRIn field of an INTC_PSRn must not be modified while its corresponding peripheral or software settable interrupt request is asserted Table 10...

Page 385: ...oftware settable Clear flag 2 0x0030 3 INTC_SSCIR3 CLR3 INTC_SSCIR3 CLR3 INTC software settable Clear flag 3 0x0040 4 INTC_SSCIR4 CLR4 INTC_SSCIR4 CLR4 INTC software settable Clear flag 4 0x0050 5 INT...

Page 386: ...EDMA_IRQRL INT20 eDMA channel Interrupt 20 0x0200 32 EDMA_IRQRL INT21 EDMA_IRQRL INT21 eDMA channel Interrupt 21 0x0210 33 EDMA_IRQRL INT22 EDMA_IRQRL INT22 eDMA channel Interrupt 22 0x0220 34 EDMA_I...

Page 387: ...0x03B0 59 EMIOS_GFR F8 EMIOS_GFR F8 eMIOS channel 8 Flag 0x03C0 60 EMIOS_GFR F9 EMIOS_GFR F9 eMIOS channel 9 Flag 0x03D0 61 EMIOS_GFR F10 EMIOS_GFR F10 eMIOS channel 10 Flag 0x03E0 62 EMIOS_GFR F11 E...

Page 388: ...A CIS17 ETPU_CISR_A CIS17 eTPU Engine A Channel 17 Interrupt Status 0x0560 86 ETPU_CISR_A CIS18 ETPU_CISR_A CIS18 eTPU Engine A Channel 18 Interrupt Status 0x0570 87 ETPU_CISR_A CIS19 ETPU_CISR_A CIS1...

Page 389: ...RFDF eQADC Receive FIFO 1 Drain Flag 0x06F0 111 EQADC_FISR2 NCF EQADC_FISR2 NCF eQADC command FIFO 2 Non Coherency Flag 0x0700 112 EQADC_FISR2 PF EQADC_FISR2 PF eQADC command FIFO 2 Pause Flag 0x0710...

Page 390: ...SPI_B Transfer Complete Flag 0x0870 135 DSPI_BSR RFDF DSPI_BSR RFDF DSPI_B Receive FIFO Drain Flag 0x0880 136 DSPI_CSR TFUF DSPI_CSR RFOF DSPI_CSR TFUF DSPI_CSR RFOF DSPI_C combined overrun interrupt...

Page 391: ...0 149 ESCIB_SR TDRE ESCIB_SR TC ESCIB_SR RDRF ESCIB_SR IDLE ESCIB_SR OR ESCIB_SR NF ESCIB_SR FE ESCIB_SR PF ESCIB_SR BERR ESCIB_SR RXRDY ESCIB_SR TXRDY ESCIB_SR LWAKE ESCIB_SR STO ESCIB_SR PBERR ESCIB...

Page 392: ...Buffer 13 Interrupt 0x0A90 169 CANA_IFRL BUF14 CANA_IFRL BUF14 FLEXCAN_A Buffer 14 Interrupt 0x0AA0 170 CANA_IFRL BUF15 CANA_IFRL BUF15 FLEXCAN_A Buffer 15 Interrupt 0x0AB0 171 CANA_IFRL BUF31I BUF16...

Page 393: ...IR HBERR EIR BABR EIR BABT EIR GRA EIR TXB EIR RXB EIR MII EIR EBERR EIR LC EIR RL EIR UN Reserved Combined Interrupt Requests of the FEC Ethernet Interrupt Event Register Heartbeat Error Babbling Rec...

Page 394: ...221 EDMA_IRQRH INT42 eDMA channel Interrupt 42 0x0DE0 222 EDMA_IRQRH INT43 eDMA channel Interrupt 43 0x0DF0 223 EDMA_IRQRH INT44 eDMA channel Interrupt 44 0x0E00 224 EDMA_IRQRH INT45 eDMA channel Inte...

Page 395: ...Channel 9 Interrupt Status 0x0fd0 253 ETPU_CISR_B CIS10 eTPU Engine B Channel 10 Interrupt Status 0x0fe0 254 ETPU_CISR_B CIS11 eTPU Engine B Channel 11 Interrupt Status 0x0ff0 255 ETPU_CISR_B CIS12 e...

Page 396: ...ansfer Complete Flag 0x1170 279 DSPIA_ISR RFDF DSPI_A Receive FIFO Drain Flag FlexCAN_B 0x1180 280 CANB_ESR BOFF_INT FLEXCAN_B Bus off Interrupt 0x1190 281 CANB_ESR ERR_INT FLEXCAN_B Error Interrupt 0...

Page 397: ...its mask bit has the same consequences as clearing its flag bit Setting its enable bit or clearing its mask bit while its flag bit is asserted has the same effect on the INTC as an interrupt event se...

Page 398: ...is set regardless of whether CLRn was asserted before the write The time from the write to the SETn bit to the time that the INTC starts to drive the interrupt request to the processor is four clocks...

Page 399: ...rts whether this highest priority is raised above the value of PRI in INTC_CPR or the PRI value in INTC_CPR is lowered below this highest priority This highest priority then becomes the new priority w...

Page 400: ...gister INTC_IACKR is updated with the preempting interrupt request s vector when the interrupt request to the processor is asserted The INTVEC field retains that value until the next time the interrup...

Page 401: ...th the preempting peripheral or software settable interrupt request s vector when the interrupt request to the processor is asserted The INTVEC field retains that value until the next time the interru...

Page 402: ...oftware settable interrupt requests to cause an interrupt request to the processor is interrupt_request_initialization configure VTES and HVEN in INTC_MCR configure VTBA in INTC_IACKR raise the PRIn f...

Page 403: ...r4 0x0 form 0 to write to INTC_EOIR wrteei 0 disable processor recognition of interrupts stw r4 INTC_EOIR l r3 store to INTC_EOIR informing INTC to lower priority code to restore SRR0 and SRR1 restore...

Page 404: ...ute with PRI in INTC current priority register INTC_CPR having a value of 0 The RTOS will execute the tasks according to whatever priority scheme that it may have but that priority scheme is independe...

Page 405: ...n Table 10 10 shows the order of execution of both ISRs with different priorities and the same priority Table 10 10 Order of ISR Execution Example Step Step Description Code Executing At End of Step P...

Page 406: ...tion of all interrupts eliminates the time when accessing a shared resource that all higher priority interrupts are blocked For example while ISR3 can not preempt ISR1 while it is accessing the shared...

Page 407: ...seResource mbar lower PRI 10 5 5 2 2 Raised Priority Preserved Before the instruction after the GetResource system service executes all pending transactions have completed These pending transactions c...

Page 408: ...rrupt exception handler prolog acknowledges interrupt by reading INTC_IACKR F PRI of 3 pushed onto LIFO PRI in INTC_CPR updates to 2 the priority of ISR208 G ISR208 clears its flag bit deasserting its...

Page 409: ...ar deadlines that share a resource They do not need to use the PCP to access the shared resource 10 5 7 Software Settable Interrupt Requests The software settable interrupt requests can be used in two...

Page 410: ...wering Priority Within an ISR In implementations without the software settable interrupt requests in the INTC software set clear interrupt registers INTC_SSCIR0 INTC_SSCIR7 a way besides scheduling a...

Page 411: ...he clearing of the flag bit that caused the present ISR to be executed Refer to Section 10 4 3 1 2 End of Interrupt Exception Handler for more information A flag bit whose enable bit or mask bit is ne...

Page 412: ...settable interrupt requests are not cleared the peripheral interrupt request to the processor re asserts when INTC_CPR PRI is lower than the priorities of those peripheral or software settable interr...

Page 413: ...ng processor recognition of interrupts while examining the LIFO contents provides a coherent view of the preempted priorities The code sequence is pop_lifo store to INTC_EOIR load INTC_CPR examine PRI...

Page 414: ...ing this later portion which does not need to be executed at this higher priority can block the execution of ISRs which do not have a higher priority than the earlier portion of the ISR but do have a...

Page 415: ...d speculatively In hardware vector mode guarded writes to the INTC_CPR or INTC_EOIR complete before the interrupt acknowledge signal from the processor asserts SECTION 10 4 2 1 4 Priority Comparator S...

Page 416: ...his section contains block diagrams that illustrate the FMPLL the clock architecture and the various FMPLL and clock configurations that are available on the MPC5553 MPC5554 The following diagrams are...

Page 417: ...x 4 MCKO_EN MCKO_GT MCKO Divider MCKO MDIS EBI MDIS eMIOS MDIS eTPU Engines MDIS eSCI x 2 MDIS CAN Interface CLK FlexCAN x 3 CLK_SRC Message Buffer CLK ENGCLK Divider CLKOUT Divider ENGCLK CLKOUT NPC...

Page 418: ...L_EXTCLK PFD Charge Filter RFD Bus Interface Control Status Registers Successive Approximation Frequency FM Control 1 0 Pumps Current Controlled Oscillator ICO XTAL PREDIV 0 1 MFD PLLCFG 0 1 MDIS DSPI...

Page 419: ...tor OSC EXTAL_EXTCLK PFD Charge Filter RFD Bus Interface Control Status Registers Successive Approximation Frequency FM Control 1 0 Pumps Current Controlled Oscillator ICO XTAL PREDIV 0 1 MFD PLLCFG 0...

Page 420: ...ence 1 Oscillator OSC EXTAL PFD Charge Filter RFD Bus Interface Control Status Registers Successive Approximation Frequency FM Control 1 0 Pumps Current Controlled Oscillator ICO XTAL PREDIV 0 1 MFD P...

Page 421: ...e 1 Oscillator OSC EXTAL PFD Charge Filter RFD Bus Interface Control Status Registers Successive Approximation Frequency FM Control 1 0 Pumps Current Controlled Oscillator ICO XTAL PREDIV 0 1 MFD PLLC...

Page 422: ...ator OSC EXTAL_EXTCLK PFD Charge Filter RFD Bus Interface Control Status Registers Successive Approximation Frequency FM Control 1 0 Pumps Current Controlled Oscillator ICO XTAL PREDIV 0 1 MFD PLLCFG...

Page 423: ...4 1 Crystal Reference Default Mode External reference mode Refer to Section 11 1 4 2 External Reference Mode PLL dual controller 1 1 mode for EXTAL_EXTCLK to CLKOUT skew minimization Programmable fre...

Page 424: ...o shows that to enter any other mode RSTCFG must be asserted during reset Note that because the 208 package size of the MPC5553 has no RSTCFG pin after reset the 208 resets to the values of PLLCFG bef...

Page 425: ...mode is shown in Figure 11 4 Figure 11 7 Crystal Oscillator Network In crystal reference mode the FMPLL can generate a frequency modulated clock or a non modulated clock locked on a single frequency...

Page 426: ...external clock on the EXTAL_EXTCLK pin The external clock is used directly to produce the internal system clocks In bypass mode the analog portion of the FMPLL is disabled and no clocks are generated...

Page 427: ...sections describe these registers in detail 11 3 1 1 Synthesizer Control Register FMPLL_SYNCR The synthesizer control register FMPLL_SYNCR contains bits for defining the clock operation for the syste...

Page 428: ...LL analog loop When the PREDIV bits are changed the FMPLL will immediately lose lock To prevent an immediate reset the LOLRE bit must be cleared before writing the PREDIV bits In 1 1 dual controller m...

Page 429: ...Note To avoid unintentional interrupt requests disable LOLIRQ before changing MFD and then reenable it after acquiring lock 9 Reserved 10 12 RFD 0 2 Reduced frequency divider The RFD bits control a di...

Page 430: ...ck 16 DISCLK Disable CLKOUT The DISCLK bit determines whether CLKOUT is active When CLKOUT is disabled it is driven low 0 CLKOUT driven normally 1 CLKOUT driven low 17 LOLIRQ Loss of lock interrupt re...

Page 431: ...requency modulation depth and enables the frequency modulation When programmed to a value other than 0x0 the frequency modulation is automatically enabled The programmable frequency deviations from th...

Page 432: ...e user must write a 1 to the bit Writing 0 has no effect This flag will not be set and an interrupt will not be requested if the loss of lock condition was caused by a system reset a write to the FMPL...

Page 433: ...ode 1 Crystal reference or external reference mode 26 PLLREF PLL clock reference source Determined at reset this bit indicates whether the PLL reference source is an external clock or a crystal refere...

Page 434: ...not requested 1 Interrupt service requested 30 CALDONE Calibration complete Indicates whether the calibration sequence has been completed since the last time modulation was enabled If CALDONE 0 then...

Page 435: ...so that the oscillator clock can be selected as the clock source for the CAN interface in the FlexCAN blocks resulting in very low jitter performance Figure 11 1 shows a block diagram of the FMPLL an...

Page 436: ...ect EBTS bit in the SIU_ECCR See Chapter 6 System Integration Unit SIU for more information 11 4 1 3 2 Nexus Message Clock MCKO The Nexus message clock MCKO divider can be programmed to divide the sys...

Page 437: ...1 shows the two clock domains in the FlexCAN modules See Chapter 22 FlexCAN2 Controller Area Network for more information on the FlexCAN modules 11 4 1 3 5 FEC Clocks In the MPC5553 the FEC TX_CLK and...

Page 438: ...ck frequency is not well defined and may exceed the maximum system frequency thereby violating the system clock timing specifications when changing MFD and PREDIV this is avoided by following the proc...

Page 439: ...MPC5553 Microcontroller Data Sheet and the MPC5554 Microcontroller Data Sheet assumes that the RFD has been programmed to 0x0 If loss of clock is enabled and the loss of clock is due to a FMPLL failu...

Page 440: ...hesize a frequency out of its range See the MPC5553 Microcontroller Data Sheet and the MPC5554 Microcontroller Data Sheet for more information 11 4 3 1 Programming System Clock Frequency Without Frequ...

Page 441: ...calibration results b Clear FMPLL_SYNCR LOLRE If this bit is set the MCU will go into reset when MFD is written c Initialize the FMPLL for less than the desired final system frequency done in one sin...

Page 442: ...etermine the modulation rate and the modulation depth The EXP field controls the FM calibration routine Section 11 4 3 3 FM Calibration Routine shows how to obtain the values to be programmed for EXP...

Page 443: ...SYNCR RFD to its desired final value Note that the FMPLL will not need to re lock when only changing the RFD 8 Re enable LOLIRQ NOTE This first register write will cause the FMPLL to switch to an init...

Page 444: ...or example if 80 MHz is the desired final frequency and 8 MHz crystal is used the final values of MFD 6 and RFD 0 will produce the desired 80 MHz For a desired frequency modulation with a 1 depth then...

Page 445: ...me to settle Both counters are reset and restarted The feedback counter begins to count full ICO clock cycles again to obtain the delta frequency count When the reference counter has counted to the ne...

Page 446: ...er Reference Manual Rev 5 Freescale Semiconductor 11 31 Figure 11 11 FM Auto Calibration Data Flow Reference Counter ICO Counter 10 13 Count 0 10 Expected EXP Error ERR 13 13 10 10 A B C D Control A B...

Page 447: ...4 Reference Counts to Settle CAL N 1 Enable FM N 7 Count M Reference Clock Cycles Store Value of Feedback Counter in CAL0 Enter Calibration Mode Set PCALPASS 1 Let DIFF CALX CAL0 DIFF 0 Yes Let ERR DI...

Page 448: ...added this note When using crystal reference mode or external reference mode The PREDIV value must not be set to any value that causes the phase frequency detector to go below 4 MHz That is the cryst...

Page 449: ...ted the equation at the end of the third paragraph changed value of M from 640 to 480 Updated Figure 11 9 Synthesizer Status Register FMPLL_SYNSR to reflect that bits 23 28 and bits 30 31 are read onl...

Page 450: ...ce EBI of the MPC5553 MPC5554 which handles the transfer of information between the internal buses and the memories or peripherals in the external address space and enables an external master to acces...

Page 451: ...Slave Interface CLKOUT Driver CLKOUT Crossbar Switch XBAR Master Interface Crossbar Switch XBAR Peripheral Bridge ADDR 8 11 DATA 0 31 CS 0 3 TS WE 0 3 BE 0 3 OE TSIZ 0 1 RD_WR BDIP TA TEA BR BG BB ADD...

Page 452: ...5554 and MPC5553 MPC5553 MPC5554 416 324 208 416 EBI Address Bus Size 24 bit1 1 24 bits available ADDR 12 31 is the default pin set then ADDR 8 11 is added to make the 24 bits ADDR 8 11 can be used or...

Page 453: ...he MPC5554 has four WE BE signals WE 0 3 BE 0 3 The MPC5553 has the following WE BE signals depending on the package 416 BGA four WE BE signals WE 0 3 BE 0 3 324 BGA two WE BE signals WE 0 1 BE 0 1 20...

Page 454: ...BB BR BG are not functional dual master operation multiple masters initiating external bus cycles is not supported However a multi MCU system with one master and one slave is supported In such a dual...

Page 455: ...TA 0 15 are the only data signals used by the EBI For EBI mastered accesses the operation in 16 bit data bus mode EBI_MCR DBM 1 EBI_BRn PS x is similar to a chip select access to a 16 bit port in 32 b...

Page 456: ...d to ADDR 8 11 then the full 24 address lines are available The calibration bus shares ADDR 12 26 with the EBI s primary bus CLKOUT3 Output Clockout Enabled 416 324 Yes CS 0 3 Output Chip Selects Up 4...

Page 457: ...e a corresponding pin See Section 12 4 2 5 Burst Transfer 12 2 1 4 Bus Grant BG MPC5554 Only BG is asserted to grant ownership of the external bus to the requesting master The BG signal is only used b...

Page 458: ...ation Chip Selects 0 2 3 CAL_CS 0 CAL_CS 2 3 MPC5553 Only CAL_CSx is asserted by the master to indicate that this transaction is targeted for a particular memory bank on the calibration external bus T...

Page 459: ...ts For write transactions TA is only asserted once at access completion even if more than one write data beat is transferred TA is driven by the EBI when the access is controlled by the chip selects o...

Page 460: ...nables WE BE Write enables are used to enable program operations to a particular memory These signals can also be used as byte enables for read and write operation by setting the WEBS bit in the appro...

Page 461: ...non EBI function Address bus Output Address bus I O 1 BB None non EBI function non EBI function Bus Busy I O BDIP 416 324 non EBI function Burst Data in Progress Output BG None non EBI function non EB...

Page 462: ...nsfer error status register 32 Base 0x000C EBI_BMCR EBI bus monitor control register 32 Base 0x0010 EBI_BR0 EBI base register bank 0 32 Base 0x0014 EBI_OR0 EBI option register bank 0 32 Base 0x0018 EB...

Page 463: ...Module Configuration Register EBI_MCR The EBI_MCR contains bits that configure various attributes associated with EBI operation 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 SIZEN SIZE 0 0 0 0 0 0...

Page 464: ...Section 12 4 2 8 Arbitration for details on internal and external arbitration When EXTM 0 the EARB bit is a don t care and is treated as 0 0 Internal arbitration is used 1 External arbitration is use...

Page 465: ...nabled or disabled 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr Base 0x0008 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31...

Page 466: ...ME 0 0 0 0 0 0 0 W Reset 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 Reg Addr Base 0x000C Figure 12 4 EBI Bus Monitor Control Register EBI_BMCR Table 12 9 EBI_BMCR Field Descriptions Bits Name Description 0 15 Re...

Page 467: ...mpared to the corresponding unmasked address signals among ADDR 0 16 of the internal address bus to determine if a memory bank controlled by the memory controller is being accessed by an internal bus...

Page 468: ...le burst accesses for this bank This is the default value out of reset 31 V Valid bit Indicates that the contents of this base register and option register pair are valid The appropriate CS signal doe...

Page 469: ...of the address mask AM field EBI_ORx 0 2 are tied to a fixed value of 111 These bits reset to their fixed value 17 23 Reserved 24 27 SCY 0 3 Cycle length in clocks Represents the number of wait state...

Page 470: ...operations are described in detail in Section 12 4 2 10 Bus Operation in External Master Mode 12 4 1 5 Memory Controller with Support for Various Memory Types The EBI contains a memory controller tha...

Page 471: ...iate base register External burst lengths of 4 and 8 words are supported Burst length is configured for each chip select by using the BL bit in the appropriate base register See Section 12 4 2 5 Burst...

Page 472: ...olling four independent memory banks See Section 12 4 1 5 Memory Controller with Support for Various Memory Types for more details on chip select bank configuration 12 4 1 12 Support for Dynamic Calib...

Page 473: ...bus DATA 0 7 contain valid data during a write read cycle The lower write byte enable WE1 BE1 indicates that the lower eight bits of the data bus DATA 8 15 contain valid data during a write read cycle...

Page 474: ...pads logic in the MCU to disable CLKOUT This feature is disabled out of reset and can be enabled or disabled by the ACGE bit in the EBI_MCR NOTE This feature must be disabled for multi master systems...

Page 475: ...e EBI are specified with respect to the rising edge of the CLKOUT signal and they are guaranteed to be sampled as inputs or changed as outputs with respect to that edge 12 4 2 2 Reset Upon detection o...

Page 476: ...support the EBI keeps driving valid write data on the data bus until 1 clock after the rising edge where RD_WR and WE for chip select accesses are negated See Figure 12 14 for an example of write timi...

Page 477: ...Figure 12 10 Single Beat 32 bit Read Cycle CS Access Zero Wait States Yes No Receives Address Asserts Transfer Start TS Drives Address and Attributes Master EBI Drives Data Asserts Transfer Acknowledg...

Page 478: ...eat 32 bit Read Cycle Non CS Access Zero Wait States Wait state 00 DATA is valid CLKOUT ADDR 8 31 TS DATA 0 31 TA RD_WR TSIZ 0 1 BDIP OE CSx 00 DATA is valid The EBI drives address and control signals...

Page 479: ...ite cycle are illustrated in the following flow and timing diagrams Figure 12 13 Basic Flow Diagram of a Single Beat Write Cycle Yes No Receives Address Asserts Transfer Start TS Drives Address and At...

Page 480: ...ingle Beat 32 bit Write Cycle CS Access Zero Wait States Figure 12 15 Single Beat 32 bit Write Cycle CS Access One Wait State 00 DATA is valid CLKOUT ADDR 8 31 TS DATA 0 31 TA RD_WR TSIZ 0 1 BDIP WE 0...

Page 481: ...d Figure 12 21 Besides this dead cycle in most cases back to back accesses on the external bus do not cause any change in the timing from that shown in the previous diagrams and the two transactions a...

Page 482: ...17 Back to Back 32 bit Reads to the Same CS Bank Figure 12 18 Back to Back 32 bit Reads to Different CS Banks 00 DATA is valid DATA is valid CLKOUT ADDR 8 31 TS DATA 0 31 TA RD_WR TSIZ 0 1 BDIP OE CSx...

Page 483: ...ure 12 19 Write After Read to the Same CS Bank Figure 12 20 Back to Back 32 bit Writes to the Same CS Bank DATA is valid CLKOUT ADDR 8 31 TS DATA 0 31 TA RD_WR TSIZ 0 1 BDIP WE CSx 00 DATA is valid CL...

Page 484: ...ternal request to the EBI indicates a size of less than 32 bytes the request is fulfilled by running one or more single beat external transfers not by an external burst transfer An 8 word wrapping bur...

Page 485: ...gram see Section 12 4 2 6 3 Small Access Example 3 32 byte Read to 32 bit Port with BL 1 During burst cycles the BDIP burst data in progress signal is used to indicate the duration of the burst data D...

Page 486: ...c Flow Diagram of a Burst Read Cycle No Yes Receives Address Asserts Transfer Start TS Drives Address and Attributes Master Next to Last Data Beat Slave Drives Data Asserts Transfer Acknowledge TA Rec...

Page 487: ...signal than the default to run burst cycles Using the default value of TBDIP 0 in the appropriate EBI base register results in BDIP being asserted SCY 1 cycles after the address transfer phase and bei...

Page 488: ...en every beat when BSCY is a non zero value Figure 12 26 shows an example of the TBDIP 1 timing for the same four beat burst shown in Figure 12 25 Figure 12 26 Burst 32 bit Read Cycle One Wait State b...

Page 489: ...12 16 shows all the combinations of burst length port size and requested byte count that cause the EBI to run multiple external transactions to fulfill the request In most cases the timing for small a...

Page 490: ...al TA Figure 12 28 shows an example of a 32 byte write to a non chip select device such as an external master using external TA requiring eight 32 bit external transactions Note that due to the use of...

Page 491: ...asking out the lower 4 bits to fix them at zero Table 12 17 Examples of 4 word Burst Addresses 1st Address Lower 5 bits of 1st Address 0x10 no carry Final 2nd Address After Masking Lower 4 Bits 0x000...

Page 492: ...ate 3 bytes get written The EBI supports only natural address alignment Byte access can have any address 16 bit access address bit 31 must be 0 32 bit access address bits 30 31 must be 0 For burst acc...

Page 493: ...the following convention is adopted The most significant byte of a 32 bit operand is OP0 and OP3 is the least significant byte The two bytes of a 16 bit operand are OP0 most significant and OP1 or OP...

Page 494: ...s Requirements for Read Cycles Transfer Size TSIZ 0 1 1 1 TSIZ is not enabled on the MPC5553 Address 32 Bit Port Size 16 Bit Port Size2 2 Also applies when DBM 1 for 16 bit data bus mode A30 A31 D0 D7...

Page 495: ...tral arbiter device When an MCU is configured to use external arbitration that MCU asserts BR when it needs ownership of the external bus and it waits for BG to be asserted from the external arbiter F...

Page 496: ...nfigured for unequal priority between internal and external masters then whenever requests are pending from both masters the one with higher priority is always granted the bus However in all cases a t...

Page 497: ...G signals of each master are also connected together because only master 0 drives BG See Figure 12 38 for an example of these connections Figure 12 35 Internal External Arbitration Timing Diagram EARP...

Page 498: ...in progress BG 0 BB 0 1 Table 12 22 Internal Arbiter Truth Table State Outputs Inputs Next State BG BB1 BR2 previ ous BB3 previ ous MCU Internal Request Pending IRP 4 previous External has Higher Prio...

Page 499: ...st for use of the external bus is pending After a transaction for a pending request has been started on the external bus this internal signal is cleared The state machine uses the previous clock value...

Page 500: ...in this state where the EBI drives BB 1 to actively negate the pin before letting go to hiZ In the case where a second granted internal request IRP 1 ETP 1 is ready to start just before the transition...

Page 501: ...onger by the slave because the EBI latches DATA every cycle during non chip select accesses During these accesses the EBI does not drive the TA signal leaving it up to an external device or weak inter...

Page 502: ...I has returned to an idle state The expectation is that the internal slaves will always respond with either valid data or an error indication within a reasonable period of time to avoid hanging the sy...

Page 503: ...y available in the MPC5554 Limited support for external master accesses master slave systems only is available in the MPC5553 see Section 12 5 5 Dual MCU Operation with Reduced Pinout MCUs 1 Latched v...

Page 504: ...s The only exceptions are the TA and TEA signals described in Section 12 4 2 9 Termination Signals Protocol and the DATA bus which are driven by the EBI for external master reads to internal address s...

Page 505: ...EBI External master access to valid internal slave If ADDR 8 1 then ADDR 9 11 are checked versus a list of 3 bit codes to determine which internal slave to forward the access to The upper 8 internal...

Page 506: ...40 illustrate the basic flow of read and write external master accesses Figure 12 39 Basic Flow Diagram of an External Master Read Access External Master EBI Slave No Yes External Arbitration Request...

Page 507: ...rom External Arbiter Receives BB Negated for 2 Cycles Negates BR if No Other Requests No Yes External Master has Priority Negates BG if Asserted Asserts Bus Busy BB if No Other Master is Driving Asser...

Page 508: ...12 41 External Master Read from MCU Receive bus grant and bus busy negated for 2nd cycle Assert BB drive address and assert TS Using the internal arbiter CLKOUT BR Input RD_WR TSIZ 0 1 BDIP BG BB ADD...

Page 509: ...y adding the arbitration sequence to the flow and timing diagrams shown for single master mode in earlier sections See Section 12 4 2 4 Single Beat Transfer and Section 12 4 2 5 Burst Transfer If the...

Page 510: ...ation Request Bus BR Receives Bus Grant BG Asserted from External Arbiter Receives BB Negated Negates BR if No Other Requests No Yes EBI has Priority Negates BG if Asserted Asserts Bus Busy BB if No O...

Page 511: ...nal master is configured for external arbitration Figure 12 45 shows an external master read followed by an MCU read to the same chip select bank Figure 12 46 shows an MCU read followed by an external...

Page 512: ...by MCU Read to Same CS Bank DATA is valid DATA is valid External master and MCU off External master starts read access Receive bus grant and bus busy negated for 2nd cycle Using the internal arbiter...

Page 513: ...External Master Read to Different CS Bank MCU starts read access Receive bus busy negated for 2nd cycle External master and MCU off Using the internal arbiter External master starts read access DATA...

Page 514: ...EBI For this case a special 2 beat burst protocol is used for reads and writes so that the EBI slave can internally generate one 32 bit read or write access thus 32 bit coherent as opposed to two sep...

Page 515: ...cle Assert BB drive address and assert TS Using the internal arbiter CLKOUT BR Input RD_WR TSIZ 0 1 BDIP BG BB ADDR 8 31 DATA 0 15 TS Input Minimum 2 wait states DATA is valid TA Output 00 DATA is val...

Page 516: ...sses can switch from one bus to the other as determined by the type of chip select each address matches The timing diagrams and protocol for the calibration bus is identical to the primary bus except...

Page 517: ...ries This includes flash and external SRAM memories with a compatible burst interface BDIP is required only for some SDR memories Figure 12 48 shows a block diagram of an MCU connected to a 32 bit SDR...

Page 518: ...ree wait states is sufficient If the actual input setup was less than 4 0ns we would have to use four wait states instead 12 5 3 2 Timing and Connections for Asynchronous Memories The connections to a...

Page 519: ...53 Read Operation to Asynchronous Memory Three Initial Wait States Figure 12 54 Write Operation to Asynchronous Memory Three Initial Wait States CLKOUT CSx OE TS ADDR 8 31 DATA 0 31 TA WE 0 1 3 wait s...

Page 520: ...r each of these scenarios More than one section may apply if the applicable pins are not present on one or both MCUs 12 5 5 1 Connecting 16 bit MCU to 32 bit MCU Master Master or Master Slave This sce...

Page 521: ...ve s SIZE field the master MCU must first write the slave s SIZE field with the correct size for the subsequent transaction 12 5 5 4 No Transfer Acknowledge TA Pin If an MCU has no TA pin available th...

Page 522: ...pport on external bus Removed address type AT write protect WP and dual mapping features because these functions can be replicated by memory management unit MMU in e200z6 core Removed support for 8 bi...

Page 523: ...ip select See Figure 12 20 and Figure 12 21 Added the following footnote to the Table 12 18 Transaction Sizes Supported by EBI Some misaligned access cases may result in 3 byte writes These cases are...

Page 524: ...s ideal for program and data storage for single chip applications allowing for field reprogramming without requiring external programming voltage sources The module is a solid state silicon memory dev...

Page 525: ...torage elements sense amplifiers row selects column selects charge pumps ECC logic and redundancy logic The arrayed storage elements in the flash core are subdivided into physically separate units ref...

Page 526: ...memory types The flash memory array has the following features Software programmable block program erase restriction control for low mid and high address spaces Erase of selected blocks ECC with singl...

Page 527: ...emulate an external memory hence the name external emulation mode The upper five address lines are used to provide additional timing control that allows the FBIU response timing on the system bus whi...

Page 528: ...E00_0000 0x0E1F_FFFF 10011 19 0x0F00_0000 0x0F1F_FFFF 11011 27 0x1000_0000 0x101F_FFFF 00100 4 0x1100_0000 0x111F_FFFF 01100 12 0x1200_0000 0x121F_FFFF 10100 20 0x1300_0000 0x131F_FFFF 11100 28 0x1400...

Page 529: ...3_FFFF Low address space 256 KB User Array Base 0x04_0000 Array Base 0x07_FFFF Mid address space 256 KB User Array Base 0x08_0000 to Array Base 0x1F_FFFF MPC5554 or to Array Base 0x17_FFFF MPC5553 Hig...

Page 530: ...set configuration 4 Array Base 0xFF_FDFC 0xFF_FFFF For general use 516 1 Not available in the MPC5553 only available in the MPC5554 2 The shadow row does not support RWW See Section 13 4 2 5 Flash Sha...

Page 531: ...disabled Register Base 0x0020 FLASH_BIUAPR Flash bus interface unit access protection register 32 Register Base 0x0030 to Register Base 0x7FFF Reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0...

Page 532: ...correction this bit will not be set If EER is not set or remains 0 this indicates that all previous reads from the last reset or clearing of EER were correct Because this bit is an error flag it must...

Page 533: ...nabled Puts the flash into stop mode Changing the value in STOP from a 0 to a 1 places the flash module in stop mode A 1 to 0 transition of STOP returns the flash module to normal operation STOP may b...

Page 534: ...m erase after an interlock write under one of the following conditions Erase ERS 1 ESUS 0 Program ERS 0 ESUS 0 PGM 1 PSUS 0 Erase suspended program ERS 1 ESUS 1 PGM 1 PSUS 0 If a program operation is...

Page 535: ...e highest priority level will be written Setting two bits with the same priority level is prevented by existing write locks and will not put the flash in an illegal state For example setting FLASH_MCR...

Page 536: ...able Enables the locking register fields SLOCK MLOCK and LLOCK to be set or cleared by register writes This bit is a status bit only and may not be written or cleared and the reset value is 0 The meth...

Page 537: ...e the LOCK bits will default to locked and will not be writable The reset value will always be 1 independent of the shadow row and register writes will have no effect MLOCK is not writable unless LME...

Page 538: ...he password 0xB2B2_2222 must be written to FLASH_HLR 0 High address locks are disabled and cannot be modified 1 High address locks are enabled to be written 1 19 Reserved 20 31 HLOCK 11 0 High address...

Page 539: ...that may be used to lock the shadow row from programs and erases SSLOCK has the same description as SLOCK in Section 13 3 2 2 Low Mid Address Space Block Locking Register FLASH_LMLR SSLOCK is not writ...

Page 540: ...interlock write is completed or if a high voltage operation is suspended In the event that blocks are not present due to configuration or total memory size the corresponding SELECT bits will default t...

Page 541: ...Register FLASH_HSR Table 13 12 FLASH_HSR Field Descriptions Bits Name Description 0 19 Reserved 20 31 HBSEL 11 0 High address space block select Has the same characteristics as MSEL For more informati...

Page 542: ...t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr Base 0xC3F8_8000 0x0018 Figure 13 11 Address Register FLASH_AR Table 13 13 FLASH_AR Field Descriptions Bits Name Description 0 9 Reserved 10 28 ADDR 3 21 Dou...

Page 543: ...ate control Used to control the timing for array writes This field must be set to a value corresponding to the operating frequency of the system clock The required settings are documented in Table 13...

Page 544: ...eserved 31 BFEN FBIU line read buffers enable Enables or disables line read buffer hits It is also used to invalidate the buffers These bits are cleared by hardware reset 0 The line read buffers are d...

Page 545: ...1 1 1 1 1 1 1 1 1 1 1 1 Reg Addr Base 0xC3F8_8000 0x0020 Figure 13 13 Flash Bus Interface Unit Access Protection Register FLASH_BIUAPR Table 13 16 FLASH_BIUAPR Field Descriptions Bits Name Description...

Page 546: ...in the FLASH_BIUCR as well as the pipelining of addresses The FBIU also has the capability of extending the normal system bus access timing by inserting additional primary initial access wait states...

Page 547: ...ains valid data which has been provided to satisfy a burst type read Valid the buffer contains valid data which has been provided to satisfy a single type read Prefetched the buffer contains valid dat...

Page 548: ...bus termination will be extended In addition no line read buffer prefetches will be initiated and buffer hits will be ignored 13 4 2 Flash Memory Array User Mode In user normal operating mode the fla...

Page 549: ...sly executed to any other partition Partitions are listed in Table 13 4 Each partition in high address space comprises of two 128 KB blocks Note that the shadow block has unique RWW restrictions descr...

Page 550: ...bit to terminate the program sequence The program sequence is presented graphically in Figure 13 14 The program suspend operation detailed in Figure 13 14 is discussed in Section 13 4 2 3 2 Flash Pro...

Page 551: ...rence Manual Rev 5 13 28 Freescale Semiconductor WARNING Aborting a program operation will leave the flash core addresses being programmed in an indeterminate data state This may be recovered by execu...

Page 552: ...st Write MCR pgm Program Suspend Write MCR Abort User Mode Read State Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Step 7 Step 9 No Yes User Mode Read State PGM 0 EHV 1 WRITE DONE 1 PSUS 1 Yes Go to Step...

Page 553: ...return indeterminate data The program sequence is resumed by writing a logic 0 to FLASH_MCR PSUS FLASH_MCR EHV must be set to a 1 before clearing FLASH_MCR PSUS to resume operation When the operation...

Page 554: ...ng an erase on the affected blocks 13 4 2 4 1 Flash Erase Suspend Resume The erase sequence may be suspended to allow read access to the flash core The erase sequence may also be suspended to program...

Page 555: ...Microcontroller Reference Manual Rev 5 13 32 Freescale Semiconductor WARNING In an erase suspended program programming flash locations in blocks which were being operated on in the erase may corrupt...

Page 556: ...er Mode Read State ERS 0 EHV 1 EHV 0 ESUS 1 Yes Go to Step 2 No EHV 0 ERS 0 ESUS 0 Step 3 Program Step 2 PGM 1 Read MCR DONE 1 PEG 0 PEG 1 Failure Success High Voltage Active WRITE DONE 1 PEG DONE 0 W...

Page 557: ...lock may be locked unlocked against program or erase by using the FLASH_LMLR or FLASH_SLMLR discussed in Section 13 3 2 Register Descriptions Programming of the shadow row has similar restrictions to...

Page 558: ...e Logic BOOTCFG1 0 1 1 BOOTCFG 0 1 bits are located in the SIU_RSR Censorship Control 0x00FF_FDE0 Upper Half Serial Boot Control 0x00FF_FDE2 Lower Half Boot Mode Name Internal Flash State Nexus State2...

Page 559: ...s Memory array accesses must not be attempted until the flash transitions out of stop mode 13 4 4 Flash Memory Array Reset A reset is the highest priority operation for the flash and terminates all ot...

Page 560: ...ontroller that prefetches sequential lines of data from the flash array into the buffer Prefetch buffer hits allow no wait responses Normal flash array accesses are registered in the FBIU and are forw...

Page 561: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 13 38 Freescale Semiconductor...

Page 562: ...manual provides a feature set overview a functional block diagram and transceiver connection information for both the 10 and 100 Mbps MII media independent interface as well as the 7 wire serial inter...

Page 563: ...are compliant with industry and IEEE 802 3 standards Figure 14 1 FEC Block Diagram Slave Interface CSR FIFO DMA Descriptor Controller MII Receive Transmit Bus Controller Controller FEC_MDC FEC_MDIO FE...

Page 564: ...roller and is divided into transmit and receive FIFOs The FIFO boundaries are programmable using the FRSR register User data flows to from the DMA block from to the receive transmit FIFOs Transmit dat...

Page 565: ...n Frames with broadcast address may be always accepted or always rejected Exact match for single 48 bit individual unicast address Hash 64 bit hash check of individual unicast addresses Hash 64 bit ha...

Page 566: ...romiscuous broadcast reject individual address hash or exact match and multicast hash match Address recognition options are discussed in detail in Section 14 4 8 Ethernet Address Recognition 14 2 4 In...

Page 567: ...the system However even errant writes to documented FEC memory locations can cause the same corruption Table 14 2 FEC Register Memory Map Address Offset Base Name Width1 Description 0x0004 EIR 32 Inte...

Page 568: ...ion some of the recommended package objects which are supported do not require MIB counters Counters for transmit and receive full duplex flow control frames are included as well 0x0150 FRSR 32 FIFO R...

Page 569: ...s Transmitted with Excessive Collisions 0x0264 IEEE_T_MACERR Frames Transmitted with Tx FIFO Underrun 0x0268 IEEE_T_CSERR Frames Transmitted with Carrier Sense Error 0x026C IEEE_T_SQE Frames Transmitt...

Page 570: ...Rx Octets 0x02C8 IEEE_R_DROP Count of frames not counted correctly 0x02CC IEEE_R_FRAME_OK Frames Received OK 0x02D0 IEEE_R_CRC Frames Received with CRC Error 0x02D4 IEEE_R_ALIGN Frames Received with A...

Page 571: ...or writes to burst those transfers on the system bus The FBOMCR determines the XBAR ports for which this bursting is enabled as well as whether the bursting is for reads writes or both FBOMCR also co...

Page 572: ...rst enable to XBAR slave port designated by FXSBEn 0 Write bursting to all XBAR slave ports is disabled 1 Write bursting is enabled to any XBAR slave port whose FXSBEn bit is asserted 10 ACCERR Accumu...

Page 573: ...ms detected in the network or transceiver are HBERR BABR BABT LC and RL Interrupts resulting from internal errors are HBERR and UN Some of the error interrupts are independently counted in the MIB blo...

Page 574: ...responding buffer descriptor has been updated 5 TXB Transmit buffer interrupt This bit indicates that a transmit buffer descriptor has been updated 6 RXF Receive frame interrupt This bit indicates tha...

Page 575: ...receive frames provided ECR ETHER_EN is also set After the FEC polls a receive descriptor whose empty bit is not set then the FEC will clear R_DES_ACTIVE and cease receive descriptor ring polling unt...

Page 576: ...transmit descriptor ring polling until the user sets the bit again signifying additional descriptors have been placed into the transmit descriptor ring The TDAR register is cleared at reset when ECR...

Page 577: ...ress Base 0x0014 Figure 14 6 Transmit Descriptor Active Register TDAR Table 14 8 TDAR Field Descriptions Bits Name Description 0 6 Reserved should be cleared 7 X_DES_ACTIVE Set to one when this regist...

Page 578: ...transmitted frame The buffer descriptors for an aborted transmit frame are not updated after clearing this bit When ETHER_EN is deasserted the DMA buffer descriptor and FIFO control logic are reset i...

Page 579: ...ntents are serially shifted and will be unpredictable if read by the user After the read management frame operation has completed the MII interrupt will be generated At this time the contents of the M...

Page 580: ...3 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address Base 0x0044 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 DIS_PREAMBLE MII_SPEED 0 W Reset...

Page 581: ...erational mode of the receive block and should be written only when ECR ETHER_EN 0 initialization time 100 MHz 0xA 2 5 MHz 132 MHz 0xD 2 5 MHz 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MIB_DISABLE MIB_I...

Page 582: ...LG bit in the end of frame receive buffer descriptor The recommended default value to be programmed by the user is 1518 or 1522 if VLAN Tags are supported 16 25 Reserved should be cleared 26 FCE Flow...

Page 583: ...tem clock is substituted for the FEC_CLK when LOOP is asserted DRT must be set to zero when asserting LOOP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0...

Page 584: ...modified when ETHER_EN is deasserted 30 HBC Heartbeat control If set the heartbeat check is performed following end of transmission and the HB bit in the status register will be set if the collision i...

Page 585: ...ODE field is a constant value 0x0001 When another node detects a PAUSE frame that node will pause transmission for the duration specified in the pause duration field This register is not reset and mus...

Page 586: ...18 19 20 21 22 23 24 25 26 27 28 29 30 31 R PAUSE_DUR W Reset U U U U U U U U U U U U U U U U Address Base 0x00EC 1 U signifies a bit that is uninitialized Figure 14 15 Opcode Pause Duration Register...

Page 587: ...tialized by the user 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R IADDR1 W Reset U U U U U U U U U U U U U U U U Address Base 0x0118 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IADDR1 W Reset U U U U...

Page 588: ...itialized by the user 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R IADDR2 W Reset U U U U U U U U U U U U U U U U Address Base 0x011C 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IADDR2 W Reset U U U...

Page 589: ...R GADDR1 W Reset U U U U U U U U U U U U U U U U Address Base 0x0120 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R GADDR1 W Reset U U U U U U U U U U U U U U U U Address Base 0x0120 1 U signifies...

Page 590: ...system bus Setting the watermark to a high value will minimize the risk of transmit FIFO underrun due to contention for the system bus The byte counts associated with the TFWR field may need to be mo...

Page 591: ...20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X_WMRK W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address Base 0x0144 Figure 14 20 FIFO Transmit FIFO Watermark Register TFWR Table 14 23...

Page 592: ...the circular receive buffer descriptor queue in external memory This pointer must be 32 bit aligned however it is recommended it be made 128 bit aligned evenly divisible by 16 Table 14 24 FRBR Field D...

Page 593: ...hould be written to 0 by the user Non zero values in these two bit positions are ignored by the hardware This register is not reset and must be initialized by the user prior to operation 0 1 2 3 4 5 6...

Page 594: ...R must be evenly divisible by 16 To insure this bits 28 31 are forced low To minimize bus utilization descriptor fetches it is recommended that EMRBR be greater than or equal to 256 bytes The EMRBR re...

Page 595: ...y hardware A hardware reset deasserts output signals and resets general configuration bits Other registers reset when the ECR ETHER_EN bit is cleared ECR ETHER_EN is deasserted by a hard reset or may...

Page 596: ...Reset Value XMIT block Transmission is aborted bad CRC appended RECV block Receive activity is aborted DMA block All DMA activity is terminated RDAR Cleared TDAR Cleared Descriptor Controller block Ha...

Page 597: ...I interface for 10 100 Mbps Ethernet and a 7 wire serial interface for 10 Mbps Ethernet The interface mode is selected by the RCR MII_MODE bit In MII mode RCR MII_MODE 1 there are 18 signals defined b...

Page 598: ...occurs during transmission of the frame half duplex mode the Ethernet controller follows the specified backoff procedures and attempts to retransmit the frame until the retry limit is reached The tran...

Page 599: ...21 the data sequence is monitored for a valid SFD 11 If a 00 is detected the frame is rejected When a 11 is detected the PA SFD sequence is complete In MII mode the receiver checks for at least one b...

Page 600: ...rs the receiver accepts the frame If flow control is enabled the microcontroller will do an exact address match check between the DA and the designated PAUSE DA 01 80 C2 00 00 01 If the receive block...

Page 601: ...t False True False BC_REJ 1 Frame Hash Match Exact Match Pause Frame False False False False True True True True Receive Frame Receive Frame Receive Frame Receive Frame Reject Frame Reject Frame PROM...

Page 602: ...CRC generator selects a bit that is set in the hash table the frame is accepted otherwise it is rejected For example if eight group addresses are stored in the hash table and random group addresses ar...

Page 603: ...2 2 35 ff ff ff ff ff 0x3 3 B5 ff ff ff ff ff 0x4 4 95 ff ff ff ff ff 0x5 5 D5 ff ff ff ff ff 0x6 6 F5 ff ff ff ff ff 0x7 7 DB ff ff ff ff ff 0x8 8 FB ff ff ff ff ff 0x9 9 BB ff ff ff ff ff 0xA 10 8B...

Page 604: ...f ff 0x27 39 7F ff ff ff ff ff 0x28 40 4F ff ff ff ff ff 0x29 41 1F ff ff ff ff ff 0x2A 42 3F ff ff ff ff ff 0x2B 43 BF ff ff ff ff ff 0x2C 44 9F ff ff ff ff ff 0x2D 45 DF ff ff ff ff ff 0x2E 46 EF ff...

Page 605: ...or tracking the appropriate collision backoff time in half duplex mode The pause timer increments once every slot time until OPD PAUSE_DUR slot times have expired On OPD PAUSE_DUR expiration TCR GTS i...

Page 606: ...s within 512 bit times the retry process is initiated The transmitter waits a random number of slot times A slot time is 512 bit times If a collision occurs after 512 bit times then no retransmission...

Page 607: ...4 Heartbeat Some transceivers have a self test feature called heartbeat or signal quality error To signify a good self test the transceiver indicates a collision to the FEC within 4 microseconds afte...

Page 608: ...EC DMA engine Software produces buffers by allocating initializing memory and initializing buffer descriptors Setting the RxBD E or TxBD R bit produces the buffer Software writing to either the TDAR o...

Page 609: ...the hardware consumer is finished with the buffer 14 5 1 2 Driver DMA Operation with Receive BDs Unlike transmit the length of the receive frame is unknown by the driver ahead of time Therefore the dr...

Page 610: ...RxBD Table 14 37 Receive Buffer Descriptor Field Definitions Halfword Location Field Name Description Offset 0 Bit 0 E Empty Written by the FEC 0 and user 1 0 The data buffer associated with this BD h...

Page 611: ...CR bit will not be set Offset 0 Bit 12 Reserved Offset 0 Bit 13 CR Receive CRC error Written by the FEC This frame contains a CRC error and is an integral number of octets in length This bit is valid...

Page 612: ...more details 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset 0 R TO1 W TO2 L TC ABC Offset 2 Data Length Offset 4 Tx Data Buffer Pointer A 0 15 Offset 6 Tx Data Buffer Pointer A 16 31 Figure 14 29 Trans...

Page 613: ...t the CRC sequence after the last data byte Offset 0 Bit 6 ABC Append bad CRC Written by user only valid if L 1 0 No effect 1 Transmit the CRC sequence inverted after the last data byte regardless of...

Page 614: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 Freescale Semiconductor 14 53 Table 14 40 Changes to MPC5553 5554 RM for Rev 5 0 Release Description of Change No change for Rev 5 release...

Page 615: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 14 54 Freescale Semiconductor...

Page 616: ...supply pin for standby operation 15 1 3 Features The SRAM controller includes the following features Supports read write accesses mapped to the SRAM memory from any master 32 KB block powered by separ...

Page 617: ...te portion of a read write R W operation Because the ECC bits can contain random data after the device is powered on the user must initialize the SRAM by executing 64 bit write instructions to the ent...

Page 618: ...resulting 64 bits formed in the previous step 4 The 8 bit ECC result is appended to the 64 bits from the data bus and the 72 bit value is then written to SRAM 15 6 1 Access Timing The system bus is a...

Page 619: ...cess Operation Previous Access Operation Number of Wait States Used Read Operation Read Idle 1 Pipelined Read Burst Read 64 bit Write 2 8 16 32 bit Write 0 read from the same address 1 read from a dif...

Page 620: ...C reporting 15 7 1 Example Code For proper initialization perform a 64 bit write to all SRAM locations The Power Architecture embedded category instruction set provides the store multiple word stmw in...

Page 621: ...word aligned is read which causes a check of ECC on all 64 bits If a correctable error is detected it will be corrected prior to merging in the write data If a non correctable error occurs during the...

Page 622: ...gment the following occurs 1 The ECC mechanism checks the entire 64 bit data bus for errors detecting and either correcting or flagging errors 2 The write data bytes 1 2 or 4 byte segment are merged w...

Page 623: ...will check the ECC value upon the read See Section 15 4 1 SRAM ECC Mechanism NOTE The SRAM must be initialized even if the application does not use ECC reporting To To use the SRAM the ECC must check...

Page 624: ...ernal memory with bus arbitration serial boot via SCI or CAN interfaces The BAM program is executed by the e200z6 core just after the MCU reset Depending on the boot mode the program initializes appro...

Page 625: ...ser code may enable the external bus interface if required 16 1 4 4 External Boot Modes This mode of operation is intended for systems that have user code and configuration information in an external...

Page 626: ...serial boot mode The eDMA during serial boot mode 16 3 2 BAM Program Operation BAM is accessed by the MCU core after the negation of RSTOUT before user code starts First the BAM program configures e2...

Page 627: ...njunction with the BOOTCFG pins to enable disable the internal flash memory and the Nexus interface The memory address of the censorship word is 0x00FF_FDE0 The censorship word consists of two fields...

Page 628: ...ted and cause a bus error Then the BAM program tries to find a valid RCHW in six predefined locations If a valid RCHW is found the BAM program enables the e200z6 watchdog timer with the RCHW WTE bit I...

Page 629: ...application should have a valid instruction at the reset boot vector address Figure 16 4 Reset Boot Vector The watchdog timeout is set to 2 5 217 system clock periods if the watchdog is enabled 16 3 2...

Page 630: ...or the two modes 16 3 2 2 3 External Boot Single Master with no Arbitration EBI Configuration The BAM program configures 1 Chip select CS0 region as a 16 bit port with a base address of 0x2000_0000 no...

Page 631: ...either external boot mode because a valid RCHW was not found the EBI remains configured according to these columns External Boot with External Arbitration 2 Multi Master Mode Function Function Functi...

Page 632: ...nfiguration In serial boot mode the BAM program configures CAN_A and eSCI_A to receive messages The CNRX_A signal and the RXD_A signals are configured as inputs to the CAN and eSCI modules The CNTX_A...

Page 633: ...gure 16 5 CAN Bit Timing The eSCI is configured for 1 start bit 8 data bits no parity and 1 stop bit and to operate at a baud rate equal to the system clock divided by 1250 See Table 16 8 for examples...

Page 634: ...d 64 bit password 2 Download start address and size of download 3 Download data 4 Execute code from start address Table 16 8 Serial Boot Mode Baud Rate and Watchdog Summary Crystal Frequency MHz Syste...

Page 635: ...ogram refreshes the e200z6 watchdog timer and the next step in the protocol can be performed 2 Download start address and size of download The host computer must send a CAN message with ID 0x012 and c...

Page 636: ...NOTE The code that is downloaded and executed must periodically refresh the e200z6 watchdog timer or change the timeout period to a value that does not cause resets during normal operation 16 3 2 3 4...

Page 637: ...start address and size of download The next 8 bytes of eSCI data the host computer sends must contain a 32 bit address in internal SRAM indicating where the following data should be stored in the memo...

Page 638: ...against stored password e200z6 watchdog timer is refreshed if the password check is successful 2 32 bit store address 32 bit number of bytes MSB first 32 bit store address 32 bit number of bytes Load...

Page 639: ...U Configuration for Internal Flash Boot for the TLB entry 2 EBI region updated the Physical Base Address to 0x2000_0000 In section CAN and eSCI Configuration updated the watchdog timer time out period...

Page 640: ...cale Semiconductor 17 1 Chapter 17 Enhanced Modular Input Output Subsystem eMIOS 17 1 Introduction This chapter describes the enhanced modular input output subsystem eMIOS of the MPC5553 MPC5554 which...

Page 641: ...nified STAC Client Submodule BIU Slave Interface Clock Prescaler Output Disable Control Bus Note 1 Connection between UC n 1 and UCn necessary to implement QDEC mode Input Output Subsystem Channel 23...

Page 642: ...all unified channels UCs 0 to 7 8 to 15 and 16 to 23 can share counter buses B C and D respectively One global prescaler Shared time bases through the counter buses Synchronization among internal and...

Page 643: ...iption Table 17 1 Unified Channel Modes Mode MPC5554 MPC5553 General purpose input output Yes Yes Single action input capture Yes Yes Single action output compare Yes Yes Input pulse width measurement...

Page 644: ...ing to Section 17 2 1 2 Output Disable Input eMIOS Output Disable Input Signals 17 2 1 1 External Signals When configured as an input EMIOSn is synchronized and filtered by the programmable input filt...

Page 645: ...rogrammed to disable the output of any eMIOS channel if that channel has selected output disable capability by the setting of its EMIOS_CCRn ODIS bit and by specifying the output disable input in its...

Page 646: ...256 Base 0x0060 UC2 Unified Channel 2 Registers 256 Base 0x0080 UC3 Unified Channel 3 Registers 256 Base 0x00A0 UC4 Unified Channel 4 Registers 256 Base 0x00C0 UC5 Unified Channel 5 Registers 256 Bas...

Page 647: ...0x0000 EMIOS_CADRn Channel A Data Register 32 UCn Base 0x0004 EMIOS_CBDRn Channel B Data Register 32 UCn Base 0x0008 EMIOS_CCNTRn Channel Counter Register 32 UCn Base 0x000C EMIOS_CCRn Channel Control...

Page 648: ...from the module and provide a method to start time bases of several modules simultaneously 0 Global time base enable out signal negated 1 Global time base enable out signal asserted Note The global ti...

Page 649: ...The EMIOS_OUDR serves to disable transfers from the A2 to the A1 channel registers and from the B2 to the B1 channel registers when values are written to these registers and the channel is running in...

Page 650: ...U8 OU7 OU6 OU5 OU4 OU3 OU2 OU1 OU0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr Base 0x0008 Figure 17 4 eMIOS Output Update Disable Register EMIOS_OUDR Table 17 8 EMIOS_OUDR Field Descriptions Bit...

Page 651: ...Rn must not be read speculatively For future compatibility the TLB entry covering the EMIOS_CBDRn must be configured to be guarded 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 B W Reset 0 0...

Page 652: ...re the setting of a channel prescaler channel mode selection input trigger sensitivity and filtering interrupt and DMA request enabling and output mode control WPTA A1 A1 B1 B1 MC Normal1 A2 A1 B2 B2...

Page 653: ...m debug functions 0 Normal operation 1 Freeze UC registers values 1 ODIS Output disable Allows output disable in any output mode except GPIO 0 The output pin operates normally 1 If the selected output...

Page 654: ...not support DMA eMIOS channels 6 7 10 11 16 17 18 and 19 DMA support is only for MPC5554 Table 17 10 EMIOS_CCRn Field Description Continued Bits Name Description eMIOS Channel DMA 0 DMA 1 0 Interrupt...

Page 655: ...reset and is always read as zero This bit is valid for every output operating mode which uses comparator A otherwise it has no effect 0 Has no effect 1 Force a match at comparator A For input modes t...

Page 656: ...n in the mode of operation description this bit has no effect 0 Single edge triggering defined by the EDPOL bit 1 Both edges triggering For GPIO input mode the EDSEL bit selects if a FLAG can be gener...

Page 657: ...ts the count direction according to the phase difference 0 Internal counter decrements if phase_A is ahead phase_B signal 1 Internal counter increments if phase_A is ahead phase_B signal NOTE In order...

Page 658: ...01 Modulus counter up down counter no change in counter direction upon match of input counter and register B1 external clock source 0010110 Modulus counter up down counter change in counter direction...

Page 659: ...d comparator A or comparator B next period update 1100100 1111111 Reserved 1010000 Modulus up counter buffered internal clock 1010001 Modulus up counter buffered external clock 1010010 1010001 Reserve...

Page 660: ...1 12 13 14 15 R OVR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr UCn Base 0x0010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R OVFL 0 0 0 0 0 0 0 0 0 0 0 0 UC...

Page 661: ...between the internal bus and the slave interface allowing communication among all submodules and the slave interface The BIU allows 8 16 and 32 bit accesses They are performed over a 32 bit data bus...

Page 662: ...submodule Figure 17 10 STAC Client Submodule Block Diagram Bits SRV 0 3 in register EMIOS_MCR selects the desired time slot of the STAC bus to be output Figure 17 11 shows a timing diagram for the STA...

Page 663: ...unter bus selector that selects the time base to be used by the channel for all timing functions Programmable clock prescaler Two double buffered data registers A and B that allow up to two input capt...

Page 664: ...0 1 BSL 0 1 Detection Comparator B Register CADR EN EN FORCMB RWCB RQB See Note 2 Internal Counter Clock See Note 1 Counter Bus B C or D Counter Bus A FORCMA MODE 0 6 UPDATE Output Disable Control Bus...

Page 665: ...ection 17 4 3 Global Clock Prescaler Submodule GCP output signal to generate a clock enable for the internal counter of the unified channel It is a programmable 2 bit down counter The global clock pre...

Page 666: ...the single buffered MC OPWFM OPWM and OPWMC modes Section 17 4 4 4 2 Single Action Input Capture Mode SAIC through Section 17 4 4 4 18 Output Pulse Width Modulation Buffered Mode OPWMB MPC5553 Only be...

Page 667: ...e unified channel can be used for input capture Figure 17 15 Single Action Input Capture Example 17 4 4 4 3 Single Action Output Compare Mode SAOC In SAOC mode a match value is loaded in register A2 a...

Page 668: ...A2 Successive captures are done on consecutive edges of opposite polarity The leading edge sensitivity that is pulse polarity is selected by EDPOL bit in the EMIOS_CCRn Registers EMIOS_CADRn and EMIO...

Page 669: ...od of an input signal by capturing two consecutive rising edges or two consecutive falling edges Successive input captures are done on consecutive edges of the same polarity The edge polarity is defin...

Page 670: ...il a match occurs on that comparator when it is disabled again In order to update registers A1 and B1 a write to A2 and B2 must occur and the EMIOS_CCRn ODIS bit must be cleared The output flip flop i...

Page 671: ...Double Action Output Compare with FLAG Set on the Second Match Figure 17 21 Double Action Output Compare with FLAG Set on Both Matches Selected Counter Bus FLAG Set Event A1 Match 0xxxxxxx0x001000 0x0...

Page 672: ...rantee coherent access reading EMIOS_CADRn disables transfers between B2 and B1 until reading EMIOS_CBDRn register then any pending transfer is re enabled Triggering of the counter clock input event i...

Page 673: ...xxxxxxx 0x001000 0x000090 0xFFFFFF 0x001500 EMIOS_CCNTRn1 FLAG Set Event MODE 6 0 Write to A1 A1 Match A1 Match A1 Value3 B1 Value Notes 1 Cleared on the first input event after writing to register A1...

Page 674: ...matches comparator B1 the internal counter is disabled and the FLAG bit is set Reading the EMIOS_CCNTRn returns the amount of detected pulses For continuous operation MODE 6 cleared the next match bet...

Page 675: ...ORCMA and FORCMB bits have no effect when the unified channel is configured for PEC mode Figure 17 24 and Figure 17 25 show how the unified channel can be used for continuous or single shot pulse edge...

Page 676: ...coder UCn EDPOL bit selects count direction according to direction signal and UC n 1 EDPOL bit selects if the internal counter is clocked by the rising or falling edge of the count signal When operati...

Page 677: ...holds the start time and register B1 holds the stop time of the programmable time interval When a match occurs between register A and the selected timebase the internal counter is cleared and it Direc...

Page 678: ...ime Figure 17 28 Windowed Programmable Time Accumulation Example 17 4 4 4 11 Modulus Counter Mode MC Table 17 23 Mode of Operation MC Mode MODE 0 6 Unified Channel Mode of Operation 0b0010000 Modulus...

Page 679: ...e FLAG and changes the counter direction from increment to decrement A match between register B1 and the internal counter changes the counter direction from decrement to increment and sets the FLAG on...

Page 680: ...cy modulation FLAG set at match of internal counter and comparator A or comparator B immediate update 0b0011011 Output pulse width and frequency modulation FLAG set at match of internal counter and co...

Page 681: ...e PWFM pulses continue to be output regardless of the state of the FLAG bit In order to achieve 0 duty cycle both registers A1 and B1 must be set to the same value When a simultaneous match occurs on...

Page 682: ...es 1 Writing EMIOS_An writes to A2 2 Writing EMIOS_Bn writes to B2 A2 value transferred to A1 according to OUn bit B2 value transferred to B1 according to OUn bit A1 Value1 B1 Value B2 Value2 0x001000...

Page 683: ...ut 0 1000 1000 25 250 1000 50 500 1000 75 750 1000 100 0 1000 1 active low output 0 1000 1000 25 250 1000 50 500 1000 75 750 1000 100 0 1000 Table 17 26 Mode of Operation OPWMC Mode MODE 0 6 Unified C...

Page 684: ...d the time base is switched to the selected counter bus In the next match between register A1 and the selected time base the output flip flop is set to the complement of the EDPOL bit This sequence re...

Page 685: ...new cycle to begin at any time as previously described In both cases FLAG is generated regardless of MODE 5 bit NOTE If A1 and B1 are set to the 0x000000 a 0 duty cycle waveform is produced NOTE Any u...

Page 686: ...ator B immediate update 0b0100001 Output pulse width modulation FLAG set at match of internal counter and comparator B next period update 0b0100010 Output pulse width modulation FLAG set at match of i...

Page 687: ...flop is set at every period to the value of EDPOL bit 0 duty cycle is possible by writing 0x000000 to register A When a match occurs the output flip flop is set at every period to the complement of ED...

Page 688: ...Mode of Operation 0b1010000 Modulus up counter buffered internal clock 0b1010001 Modulus up counter buffered external clock 0b1010010 0b1010001 Reserved 0b1010100 Modulus up down counter buffered FLA...

Page 689: ...the A1 value In up down counter mode the period is defined by the formula 2 A1 2 Figure 17 37 illustrates the counter cycle for several A1 values Register A1 is loaded with the A2 value at the cycle b...

Page 690: ...Operation A1 Register Update Figure 17 40 illustrates the A1 register update process in up down counter mode Note that A2 can be written at any time within cycle n in order to be used in cycle n 1 Thu...

Page 691: ...ent of EDPOL A B1 match also causes the internal counter to transition to 1 thus re starting the counter cycle Figure 17 41 shows an example of OPWFMB mode operation Note that the output flip flop tra...

Page 692: ...instead of the positive edge that is used when A1 1 Note that the A1 positive edge match signal from cycle n 1 occurs at the same time as the B1 match negative edge from cycle n This allows the use o...

Page 693: ...ernal by pass allows the use of A2 instead of A1 for matches if A2 is either 0 or 1 thus allowing matches to be generated even when A1 is being loaded This approach allows a uniform channel operation...

Page 694: ...A1 Value B1 Value B2 Value 0x000008 0x000002 0x000006 0x000008 0x000001 0x000004 0x000006 MODE 0 1 A2 Value 0x000002 0x000004 0x000006 0x000002 0x000004 0x000006 0x000008 0x000006 Output Flip Flop Wri...

Page 695: ...n A1 match thus the output flip flop is set to the complement of EDPOL This cycle corresponds to a 100 duty cycle signal The same output signal can be generated for any A1 value greater than or equal...

Page 696: ...recommended that the internal prescaler of the OPWMCB channel be set to the same value as the MCB channel prescaler and the prescalers should also be synchronized This allows the A1 and B1 registers t...

Page 697: ...hat both A1 and B1 register values are changing within the same cycle which allows the duty cycle and dead time values to be changed at simultaneously Figure 17 47 eMIOS PWMCB Mode Example Lead Dead T...

Page 698: ...DPOL In trailing dead time insertion mode the output flip flop is forced to the value of EDPOL If FORCMB is set the output flip flop value depends on the selected dead time insertion mode In leading d...

Page 699: ...dead time insertion mode a B1 match from cycle n could eventually cross the cycle boundary and occur in cycle n 1 In this case the B1 match is masked out and does not cause the output flip flop to tra...

Page 700: ...n on A1 and B1 register updates Flags are generated at B1 matches when MODE 5 is cleared or on both A1 and B1 matches when MODE 5 is set If subsequent matches occur on comparators A and B the PWM puls...

Page 701: ...or 0 duty cycle Note that the A1 match signal positive edge occurs at the same time as the B1 8 signal negative edge In this case the A1 match has precedence over the B1 match causing the output flip...

Page 702: ...or B1 match The output disable does not modify the flag bit behavior Note that there is one system clock delay between the assertion of the output disable signal and the transition of the output flip...

Page 703: ...hes In this example if B1 0x000009 a B1 match does not occur and thus a 0 duty cycle signal is generated Cycle n Cycle n 1 Cycle n 2 A1 Value B1 Value B2 Value 0x000008 0x000002 0x000006 0x000008 0x00...

Page 704: ...t be set up before enabling the global prescaler If the internal prescalers are set after enabling the global prescaler the internal counters may increment in the same ratio but at a different clock c...

Page 705: ...Signal Match Value Clock Prescaled Clock Ratio 1 Bypassed 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 NOTE The period of the time base includes the match value When a match occurs the first clock cy...

Page 706: ...se Mode of Operation tables for all modes Added this first sentence to the OPWFM mode In this mode the duty cycle is register A1 1 and the period is register B1 1 Table 17 33 Changes to MPC5553 5554 R...

Page 707: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 17 68 Freescale Semiconductor...

Page 708: ...of the eTPU engine that reduces service time Because responding to hardware service requests is primarily done by the eTPU engine the host is free to handle higher level operations 18 1 1 The MPC5553...

Page 709: ...within this chapter as well as in the Enhanced Time Processing eTPU Reference Manual 18 1 2 Block Diagram Figure 18 1 shows a top level eTPU block diagram It displays the MPC5554 s dual eTPU engine co...

Page 710: ...uest The service request microcode may send an interrupt to the MPC5553 MPC5554 core but the core cannot be directly interrupted by I O channel events Each channel is associated with a function that d...

Page 711: ...by an asynchronous counter such as an angle clock that may be tracking the angle of a rotating shaft Each eTPU engine consists of the following blocks 32 independent timer channels a task scheduler a...

Page 712: ...nality Single input capture with single match time out TPU3 functionality Single input capture with double match time out with several double match submodes Double input capture with single or double...

Page 713: ...bits that is the most significant bit of the word s second most significant byte byte addresses is copied in all 8 bits of the most significant read byte Figure 18 4 PSE Accesses Each eTPU channel ca...

Page 714: ...priority mechanism implemented in hardware ensures that all requesting channels are serviced 18 1 3 1 6 Microengine The eTPU microengine is a simple RISC implementation that performs each instruction...

Page 715: ...bit match registers 24 bit greater equal or equal only comparator Two independent 24 bit time bases for channel synchronization The first time base may be clocked by the system clock with programmable...

Page 716: ...d microengine time Hardware scheduler works as a task management unit dispatching event service routines by predefined host configured priority Hardware breakpoints on data access qualified by address...

Page 717: ...dently Module disable mode stops only the engine clock so that the shared BIU and global channel registers can be accessed and interrupts and DMA requests can be cleared and enabled disabled An engine...

Page 718: ...C5553 MPC5554 s eTPU while still maintaining the eTPU s functionality the eTPU is also internally wired to the DSPI 20 1 Introduction The DSPI connections are shown in the column labeled DSPI Serial C...

Page 719: ...SPI_D 11 10 1 GPIO 142 143 30 31 I D1 D2 30 31 not connected eTPU_A 30 31 GPIO 144 145 O 1 The channel numbers for some of the DSPI channels connections are reversed for example if eTPU_A 16 19 is map...

Page 720: ...have their outputs forced to the opposite of the value specified in the ETPU_CnCR OPOL bit Therefore individual channels can be selected to be affected by the output disable signals as well as their...

Page 721: ...able Channel Groups eMIOS Channel Engine eTPU Channels Disabled 11 A 0 7 10 8 15 9 16 23 8 24 31 20 B 0 7 21 8 15 22 16 23 23 24 31 Table 18 5 eTPU High Level Memory Map Address Register Description B...

Page 722: ...r 1 Parameter Sign Extension access area See the eTPU reference manual Table 18 6 Detailed Memory Map Address Register Name Register Description Size bits Base 0xC3FC_0000 ETPU_MCR eTPU module configu...

Page 723: ...register 32 Base 0x0_0224 ETPU_CIOSR_B1 eTPU B channel interrupt overflow status register 32 Base 0x0_0228 Reserved Base 0x0_022C Reserved Base 0x0_0230 ETPU_CDTROSR_A eTPU A channel data transfer re...

Page 724: ...n register 32 Base 0x0_05F4 ETPU_C31SCR_A eTPU A channel 31 status and control register 32 Base 0x0_05F8 ETPU_C31HSRR_A eTPU A channel 31 host service request register 32 Base 0x0_05FC Base 0x0_07FF R...

Page 725: ...Base 0x0_FFFF Reserved Base 0x1_0000 Base 0x1_2FFF SCM Shared code memory3 12 Kbytes MPC5553 16 Kbytes MPC5554 Base 0x1_3000 Base 0x1_FFFF Reserved 1 The register at this address is available only on...

Page 726: ...ation dependent it can be coded in an SDM status parameter for instance This bit is cleared by writing 1 to GEC 0 No microcode requested global exception pending 1 Global exception requested by microc...

Page 727: ...23 24 Reserved 25 VIS SCM visibility Determines SCM visibility to the slave bus interface and resets the MISC state but SCMMISEN keeps its value 0 SCM is not visible to the slave bus Accessing SCM add...

Page 728: ...ransfer base This field concatenates with fields PARM0 PARM1 to determine the absolute offset from the SDM base of the parameters to be transferred Parameter 0 address CTBASE PARM0 4 SDM base Paramete...

Page 729: ...ent data transfer 0 Read operation Data transfer is from the selected parameter RAM address to the PB 1 Write operation Data transfer is from the PB to the selected parameter RAM address 25 31 PARM1 0...

Page 730: ...1 1 0 1 1 1 0 1 1 1 Reg Addr Base 0x0_0010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R ETPUSCMOFFDATA 16 31 W Reset 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 Reg Addr Base 0x0_0010 Figure 18 8 eTPU SCM Of...

Page 731: ...when the thread is complete 0 eTPU engine runs 1 Commands engine to stop its clocks Stop completes on the next system clock after the stop condition is valid The MDIS bit is write protected when ETPU_...

Page 732: ...manual Changing CDFC during eTPU normal input channel operation is not recommended because it changes the behavior of the transition detection logic while executing its operation Table 18 11 ETPU_ECR...

Page 733: ...0 4 Entry table base Determines the location of the microcode entry table for the eTPU functions in SCM More information about entry points is located in the eTPU reference manual The following table...

Page 734: ...ngine TCRCLKA and TCRCLKB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TCR2CTL TCRCF 0 AM 0 0 0 TCR2P W Reset 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 Reg Addr eTPU A Base 0x0_0020 eTPU B Base 0x0_0040 16 17 18 19...

Page 735: ...TCR2 clock sources are listed in the following table TCR2CTL AM 0 TCR2 Clock AM 1 Angle Tooth Detection 000 Gated DIV8 clock system clock 8 When the external TCRCLK signal is low the DIV8 clock is blo...

Page 736: ...he EAC works and stores tooth counter and angle tick counter data in TCR2 MPC5554 If TCR1 or TCR2 is a STAC bus client EAC operation is forbidden Therefore if AM is set the angle logic will not work p...

Page 737: ...s Manual 24 31 TCR1P Timer count register 1 prescaler control Clocked from the output of a prescaler The input to the prescaler is the internal eTPU system clock divided by 2 or the output of TCRCLK f...

Page 738: ...gures the eTPU STAC bus interface module and operation For more information on the STAC interface refer to the eTPU reference manual Table 18 13 ETPU_TB1R Field Descriptions Bits Name Description 0 7...

Page 739: ...CR For a client mode the SRV1 field determines the server address to which the client listens 0 Resource client operation 1 Resource server operation 2 3 Reserved 4 7 SERVER_ID 1 STAC bus address for...

Page 740: ...elects the address of the specific STAC server the local TCR2 listens to when configured as a STAC Client For more information on the STAC interface refer to the eTPU reference manual 1 Resource ident...

Page 741: ...ropriate field Table 18 16 ETPU_CISR Field Descriptions Bits Name Description 0 31 CISn Channel n interrupt status 0 indicates that channel n has no pending interrupt to the host core 1 indicates that...

Page 742: ...ite 1 to it For details about data transfer requests refer to the eTPU reference manual 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CIOS 31 CIOS 30 CIOS 29 CIOS 28 CIOS 27 CIOS 26 CIOS 25 CIOS 24 CIOS 23...

Page 743: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R DTROS 31 DTROS 30 DTROS 29 DTROS 28 DTROS 27 DTROS 26 DTROS 25 DTROS 24 DTROS 23 DTROS 22 DTROS 21 DTROS 20 DTROS 19 DTROS 18 DTROS 17 DTROS 16 W w1c w1c w1c w1c...

Page 744: ...IE 2 CIE 1 CIE 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr eTPU A Base 0x0_0240 eTPU B Base 0x0_0244 Figure 18 18 eTPU Channel Interrupt Enable Register ETPU_CIER Table 18 20 ETPU_CIER Field De...

Page 745: ...for channel n 1 Data transfer request enabled for channel n For details about interrupts refer to the eTPU reference manual 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R SR31 SR30 SR29 SR28 SR27 SR26 SR25 S...

Page 746: ...ter can be changed by the service thread microcode 18 4 2 4 Channel Configuration and Control Registers Each channel for both eTPU engines has a group of three registers used to control configure and...

Page 747: ...ate interrupt requests even if their request status bits assert in registers ETPU_CDTRSR and ETPU_CnSCR 0x08 eTPU channel host service request register ETPU_CnHSRR 0x0C Reserved Table 18 25 eTPU Chann...

Page 748: ...8 9 10 11 12 13 14 15 R CIE DTRE CPR 0 0 ETPD1 1 ETPD is only offered in the MPC5553 ETCS 0 0 0 CFS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr Channel_Register_Base 0x00 16 17 18 19 20 21 22 23...

Page 749: ...ry table condition encoding scheme 0 Select standard entry table condition encoding scheme For details about entry table and condition encoding schemes refer to the eTPU reference manual 8 10 Reserved...

Page 750: ...tatus bits assert in registers ETPU_CDTRSR and ETPU_CnSCR 18 20 Reserved 21 31 CPBA 0 10 Channel n parameter base address The value of this field multiplied by 8 specifies the SDM parameter base host...

Page 751: ...eTPU reference manual The core must write 1 to clear CIOS 2 7 Reserved 8 DTRS Data transfer request status 0 Channel has no pending data transfer request 1 Channel has a pending data transfer request...

Page 752: ...ddr Channel_Register_Base 0x08 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 HSR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr Channel_Register_Base 0x08 Figure 18 24...

Page 753: ...res added this bullet The second time base has a programmable prescaler that applies to all TCR2 clock inputs except the angle counter In Section 18 1 4 Features changed FROM 32 bit microengine regist...

Page 754: ...le Semiconductor 18 47 Table 18 30 Changes to MPC5553 5554 RM for Rev 5 0 Release Description of Change In Section 18 4 2 2 4 STAC Bus Configuration Register ETPU_REDCR changed SERVER_ID1 and SERVER_I...

Page 755: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 18 48 Freescale Semiconductor...

Page 756: ...e MPC5553 MPC5554 provides accurate and fast conversions for a wide range of applications The eQADC provides a parallel interface to two on chip analog to digital converters ADCs and a single master t...

Page 757: ...es empty An RFIFO overflow occurs when an RFIFO is full and more data is ready to be moved to the RFIFO by the host CPU or by eDMA Accordingly the eQADC generates eDMA or interrupt requests to control...

Page 758: ...ion between the eQADC and an external device Figure 19 1 also depicts data flow through the eQADC Commands are contained in system memory in a user defined queue data structure Command data is moved f...

Page 759: ...pt when command coherency is not achieved External hardware triggers Supports rising edge falling edge high level and low level triggers Supports configurable digital filter Supports four external 8 t...

Page 760: ...d Command transfer is in progress eQADC will complete the transfer and update CFIFO status before halting future command transfers from any CFIFO Command transfers to the external device are considere...

Page 761: ...mand transfers from any CFIFO The message of the CFIFO that caused the abort of the previous serial transmission will only be transmitted after stop mode is exited Command transfer is in progress The...

Page 762: ...nput 5 Negative Terminal Differential Input I I AN5 Analog 416 324 208 AN6 DAN3 Single Ended Analog Input 6 Positive Terminal Differential Input I I AN6 Analog 416 324 208 AN7 DAN3 Single Ended Analog...

Page 763: ...ingle Ended Analog Input I I AN 22 25 Analog 416 324 208 AN26 Single Ended Analog Input I I AN26 Analog 416 324 AN 27 28 Single Ended Analog Input I I AN 27 28 Analog 416 324 208 AN29 Single Ended Ana...

Page 764: ...ed Down weak pulldown enabled Low output driven low High output driven high A dash on the left side of the slash denotes that both the input and output buffers for the pin are off A dash on the right...

Page 765: ...Base 0x0048 Reserved Base 0x004C Reserved Base 0x0050 EQADC_CFCR0 eQADC command FIFO control register 0 16 Base 0x0052 EQADC_CFCR1 eQADC command FIFO control register 1 16 Base 0x0054 EQADC_CFCR2 eQA...

Page 766: ...ase 0x009A EQADC_CFTCR5 eQADC command FIFO transfer counter register 5 16 Base 0x009C Reserved Base 0x00A0 EQADC_CFSSR0 eQADC command FIFO status snapshot register 0 32 Base 0x00A4 EQADC_CFSSR1 eQADC...

Page 767: ...egisters 0 3 32 Base 0x0310 Base 0x033C Reserved Base 0x0340 Base 0x034C EQADC_RF1Rn eQADC RFIFO1 registers 0 3 32 Base 0x0350 Base 0x37C Reserved Base 0x380 Base 0x038C EQADC_RF2Rn eQADC RFIFO2 regis...

Page 768: ...9 30 31 R 0 0 0 0 0 0 0 0 0 0 0 ESSIE 0 DBG W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr Base 0x0000 Figure 19 2 eQADC Module Configuration Register EQADC_MCR Table 19 3 EQADC_MCR Field Descriptio...

Page 769: ...19 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 NMF W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr Base 0x0008 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R NMF W Reset 0 0 0 0 0 0...

Page 770: ...Filter Register EQADC_ETDFR Table 19 5 EQADC_ETDFR Field Description Table Bits Name Description 0 27 Reserved 28 31 DFL 0 3 Digital filter length Specifies the minimum number of system clocks that m...

Page 771: ...136541 67 0b1111 32769 273075 00 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W CF_PUSHn Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr Base 0x0010 EQADC_CFPR0 Base 0x0014 E...

Page 772: ...On is full the eQADC ignores any write to the CF_PUSHn Reading the EQADC_CFPRn always returns 0 Note Only whole words must be written to EQADC_CFPR Writing halfwords or bytes to EQADC_CFPR will still...

Page 773: ...d does not decrement the RFCTRn value Writing to EQADC_RFPRn has no effect 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 MODEn 0 0 0 0 W SSEn CFINVn Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg...

Page 774: ...ODEn 0 3 CFIFO operation mode n Selects the CFIFO operation mode for CFIFOn Refer to Section 19 4 3 5 CFIFO Scan Trigger Modes for more information on CFIFO trigger mode Note If MODEn is not disabled...

Page 775: ...requests of all CFIFOs are ORed When RFOIEn CFUIEn and TORIEn are all asserted this combined interrupt request is asserted whenever one of the following 18 flags becomes asserted RFOFn CFUFn and TORFn...

Page 776: ...8 is asserted Apart from generating an independent interrupt request for an RFIFOn overflow event the eQADC also provides a combined interrupt at which the result FIFO overflow Interrupt the command F...

Page 777: ...by CFIFOn is coherent 1 Command sequence being transferred by CFIFOn became non coherent Note Non coherency means that a command in the command FIFO was not immediately executed but delayed This may...

Page 778: ...pause bit was transferred from CFIFOn CFIFO in edge trigger mode or CFIFO status changes from the TRIGGERED state due to detection of a closed gate CFIFO in level trigger mode Note In edge trigger mod...

Page 779: ...ode for further details The SSSn bit is set by writing a 1 to the SSEn bit see Section 19 3 2 6 The eQADC clears the SSSn bit when a command with an asserted EOQ bit is transferred from a CFIFO in sin...

Page 780: ...RFDFn are both asserted an interrupt or an eDMA request will be generated depending on the status of the RFDSn bit When RFDSn is negated interrupt requests selected software clears RFDFn by writing a...

Page 781: ...0 0 0 0 0 0 0 0 0 0 Reg Addr EQADC_BASE 0x0090 EQADC_CFTCR0 EQADC_BASE 0x0092 EQADC_CFTCR1 EQADC_BASE 0x0094 EQADC_CFTCR2 EQADC_BASE 0x0096 EQADC_CFTCR3 EQADC_BASE 0x0098 EQADC_CFTCR4 EQADC_BASE 0x00...

Page 782: ...apture the status registers before the status registers change because of the transfer of the current command that is about to be popped from the CFIFO The EQADC_CFSSRs are read only Writing to the EQ...

Page 783: ...ted This field has no meaning when LCFT0 is 0b1111 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CFS0_T1 CFS1_T1 CFS2_T1 CFS3_T1 CFS4_T1 CFS5_T1 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr Base...

Page 784: ...uffer LCFT1 has the following values 21 31 TC_LCFT1 0 10 Transfer counter for last CFIFO to transfer commands to ADCn command buffer Indicates the number of commands which have been completely transfe...

Page 785: ...Register 2 EQADC_CFSSR2 Table 19 16 EQADC_CFSSR2 Field Descriptions Bits Name Description 0 11 CFSn_TSSI 0 1 CFIFO Status at Transfer through the eQADC SSI Indicates the CFIFOn status at the time a s...

Page 786: ...LCFTSSI is a copy of the corresponding TC_CFn in EQADC_CFTCRn see Section 19 3 2 9 captured at the time a command transfer to an external command buffer is initiated This field has no meaning when LCF...

Page 787: ...of the user defined command queue in single scan mode Reserved 0b01 Not applicable WAITING FOR TRIGGER 0b10 CFIFO mode is modified to continuous scan edge or level trigger mode CFIFO mode is modified...

Page 788: ...ial transmissions from the eQADC SSI are disabled See EQADC_MCR ESSIE field in Section 19 3 2 1 24 27 Reserved 28 31 BR 0 3 Baud rate Selects system clock divide factor as shown in Table 19 21 The bau...

Page 789: ...24 25 26 27 28 29 30 31 R R_DATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr Base 0x00B8 Figure 19 16 eQADC SSI Receive Data Register EQADC_SSIRDR Table 19 22 EQADC_SSIRDR Field Descriptions Bits...

Page 790: ...CF1R3 CFIFO2 Base 0x0180 CF2R0 Base 0x0184 CF2R1 Base 0x0188 CF2R2 Base 0x018C CF2R3 CFIFO3 Base 0x01C0 CF3R0 Base 0x01C4 CF3R1 Base 0x01C8 CF3R2 Base 0x01CC CF3R3 CFIFO4 Base 0x0200 CF4R0 Base 0x0204...

Page 791: ...on 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr RFIFO0 Base 0x0300 RF0R0 Base 0x0304 RF0R1 Base 0x0308 RF0R2 Base 0x030C RF0...

Page 792: ...TSCR 1 1 This register is also accessible by configuration commands sent to the ADC1 command buffer Write Read 0x03 ADC Time Base Counter Register ADC_TBCR 1 Write Read 0x04 ADC0 Gain Calibration Cons...

Page 793: ...ed the ADC clock will not stop until it reaches its low phase 1 3 Reserved 4 ADCn_EMUX ADCn external multiplexer enable When ADCn_EMUX is asserted the MA pins will output digital values according to t...

Page 794: ...ck Divide Factor 0b00000 2 0b00001 4 0b00010 6 0b00011 8 0b00100 10 0b00101 12 0b00110 14 0b00111 16 0b01000 18 0b01001 20 0b01010 22 0b01011 24 0b01100 26 0b01101 28 0b01110 30 0b01111 32 0b10000 34...

Page 795: ...TSCR are not allowed 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 TBC_CLK_PS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr 0x02 Figure 19 20 ADC Time Stamp Control Register ADC_T...

Page 796: ...ltaneous write accesses from ADC0 and ADC1 to ADC_TBCR are not allowed 0b1011 128 0 94 0b1100 256 0 47 0b1101 512 0 23 0b1110 0b1111 Reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TBC_VALUE W Reset...

Page 797: ...n scheme used in the eQADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 GCC0 W Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr 0x04 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 GCC1 W Reset 0 1 0 0 0 0 0 0 0...

Page 798: ...EOQ bit set in the last transfer After an EOQ bit is detected software involvement is required to rearm the CFIFO so that it can detect new trigger events When a CFIFO is configured for continuous sca...

Page 799: ...device are executed and the type of results that can be expected depends on the architecture of that device with the exception of unsolicited data like null messages for example NOTE While the eQADC...

Page 800: ...SSI eQADC ADC eQADC SSI External Device Logic Buffers DMA Transaction Done Signals Host CPU or DMAC DMA or Interrupt Requests NOTES n 0 1 2 3 4 5 ADC Command CFIFO Header Command Message Result Queue...

Page 801: ...bit of the ADC command see Section Command Message Format for External Device Operation An external device that only implements one command buffer can ignore the BN bit The limit of two command buffe...

Page 802: ...tion This section describes the command result message formats used for on chip ADC operation NOTE Although this subsection describes how the command and result messages are formatted to communicate w...

Page 803: ...of a command with an asserted pause bit the CFIFO enters the WAITING FOR TRIGGER state Refer to Section 19 4 3 6 1 CFIFO Operation Status for a description of the state transitions The pause bit is on...

Page 804: ...for the current conversion command after the conversion result is sent to the RFIFOs See Section 19 4 5 3 Time Stamp Feature for details 0 Return conversion result only 1 Return conversion time stamp...

Page 805: ...DCs into the 16 bit format which is sent to the RFIFOs See Section ADC Result Format for On Chip ADC Operation for details 0 Right justified unsigned 1 Right justified signed 16 23 CHANNEL_ NUMBER 0 7...

Page 806: ...IFO operation mode is configured to single or continuous scan edge trigger mode 0 Do not enter WAITING FOR TRIGGER state after transfer of the current command message 1 Enter WAITING FOR TRIGGER state...

Page 807: ...tion of an asserted EOQ bit on the last transferred command See Section 19 4 3 5 CFIFO Scan Trigger Modes for details 0 Not the last entry of the command queue 1 Last entry of the command queue Note I...

Page 808: ...ration command 0 Write 1 Read 8 11 MESSAGE_TAG 0 3 MESSAGE_TAG field Allows the eQADC to separate returning results into different RFIFOs When the eQADC transfers a command the MESSAGE_TAG is included...

Page 809: ...re 19 30 Correspondence between the analog voltage in a channel and the calculated digital values is shown in Table 19 39 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SIGN_EXT CONVERSION_RESULT With inverted...

Page 810: ...o which external command buffer the corresponding command should be sent The remaining 25 bits can be anything decodable by the external device Only the ADC command portion of a command message is tra...

Page 811: ...o create sub queues within a command queue When the eQADC completes the transfer of a command with an asserted pause bit the CFIFO enters the WAITING FOR TRIGGER state Refer to Section 19 4 3 6 1 CFIF...

Page 812: ...ansfer commands to the external command buffers 6 BN Refer to Section Conversion Command Message Format for On Chip ADC Operation 7 31 OFF_CHIP_ COMMAND 0 24 OFF CHIP COMMAND Field The OFF_CHIP_COMMAN...

Page 813: ...ce Operation for more information The MESSAGE_TAG field must be set to the null message tag 0b1000 The eQADC does not store into an RFIFO any incoming message with a null message tag 12 15 BUSYn 0 1 B...

Page 814: ...for examples of how command queues and result queues can be used 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CONTENTS OF EQADC_NMSFR REGISTER 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 CONTENTS OF EQAD...

Page 815: ...ointer points to the next entry to be removed from CFIFOn when it completes a transfer The CFIFO transfer counter control logic counts the number of entries in the CFIFO and generates eDMA or interrup...

Page 816: ...er n then is incremented by 1 or wrapped around to point to the next entry in the CFIFO When the EQADC_CFPRn is written but CFIFOn is full the eQADC will not increment the counter value and will not o...

Page 817: ...t is not full and it is the highest priority triggered CFIFO sending commands to that buffer First In Transfer Next Data Pointer Last In Push Next Data Pointer CFIFOn Transfer Next Data Pointer Push N...

Page 818: ...ion No data from these CFIFOs will be sent to either of the on chip ADCs or to either of the external command buffers nor will they stop lower priority CFIFOs from transferring commands Whenever ADC0...

Page 819: ...mmand is being transmitted the serial transmission is aborted when all following conditions are met CFIFO0 is in the TRIGGERED state is not underflowing and its current command is bound for an externa...

Page 820: ...from eTPU or eMIOS Channels The six eQADC external trigger inputs can be connected to either an external pin an eTPU channel or an eMIOS channel The input source for each eQADC external trigger is ind...

Page 821: ...ive when MODEn is set to a value different from disabled and in case MODEn is set to single scan mode when the SSS bit is asserted Note that the time necessary for a external trigger event to result i...

Page 822: ...If MODEn is not disabled it must not be changed to any other mode besides disabled If MODEn is disabled and the CFIFO status is IDLE MODEn can be changed to any other mode If MODEn is changed to disab...

Page 823: ...highest priority CFIFO using an available on chip ADC or an external command buffer that is not full When an asserted EOQ bit is encountered the eQADC will clear the SSS bit Setting the SSS bit is req...

Page 824: ...nuous scan mode the EQADC_CFCRn SSE see Section 19 3 2 6 does not have any effect Continuous Scan Software Trigger When a CFIFO is programmed to continuous scan software trigger mode the CFIFO is trig...

Page 825: ...ion of a command to the external device it will have no effect on the CFIFO status until the transmission completes After the transmission is completed the TC_CF counter is updated the PF flag is asse...

Page 826: ...19 4 3 6 3 Pause Status for more information on pause Other Command Transfer Stop Condition3 4 3 The eQADC always stops command transfers from a CFIFO when the CFIFO operation mode is disabled 4 The...

Page 827: ...is programmed to continuous scan edge or level trigger mode OR CFIFO mode is programmed to single scan edge or level trigger mode and SSS is asserted OR CFIFO mode is programmed to single scan softwar...

Page 828: ...f command transfer and CFIFO mode is not modified to disabled OR CFIFO in single scan level trigger mode and the gate closes while no commands are being transferred from the CFIFO and CFIFO mode is no...

Page 829: ...erformed If a closed gate is detected while no command transfers are taking place it will have immediate effect on the CFIFO status If a closed gate is detected during the serial transmission of a com...

Page 830: ...transfers its first command to an on chip ADC The CFIFO is constantly transferring commands and the previous command sequence ended The CFIFO resumes command transfers after being interrupted And a co...

Page 831: ...even command sequences all containing a single command but NCF would never get set CFn_ADCa_CMDn Command n in CFIFOn bound for ADCa ADC3 and ADC4 are external devices associated with external command...

Page 832: ...s always outdated by at least the length of one serial transmission This prevents a CFIFO from immediately becoming non coherent when it starts transferring commands to an empty external command buffe...

Page 833: ...coherency hardware will behave as if the command sequence started from that point Figure 19 45 depicts how the non coherency hardware will behave when a non coherency event is detected NOTE If MODEn i...

Page 834: ...DC1 and both are not triggered a CFIFO5 CF5_ADC1_CM3 3 CF5_ADC1_CM2 2 Sent 1 Sent 0 TNXTPTR ADC1 CF5_ADC1_CM1 1 CF5_ADC1_CM0 0 CFIFO5 becomes triggered and transfers CFIFO0 CF0_ADC1_CM3 3 CF0_ADC1_CM2...

Page 835: ...CM3 3 CF0_2_CM2 2 Sent 1 Sent 0 TNXTPTR command buffer 2 CFIFO5 cannot send commands to external command buffer 3 because the eQADC SSI is b Command Buffer 3 CF5_3_CM1 1 Empty 0 eQADC SSI busy transfe...

Page 836: ...rom the RFIFO pop registers for every asserted eDMA request it acknowledges Refer to Section 19 5 2 EQADC eDMA Controller Interface for eDMA controller configuration guidelines Figure 19 46 describes...

Page 837: ...d and the receive next data pointer n is not incremented or wrapped around RFIFOn is full when the receive next data pointer n equals the pop next data pointer n and RFCTRn is not 0 RFIFOn is empty wh...

Page 838: ...ores the 16 bit data into the appropriate RFIFO if the MESSAGE_TAG indicates a valid RFIFO number or First In Pop Next Data Pointer Last In Receive Next Data Pointer RFIFOn Pop Next Data Pointer Recei...

Page 839: ...tarted and the bias generator circuit is turned on When the enable bits of both ADCs are negated the bias circuit generator is stopped NOTE Conversion commands sent to a disabled ADC are ignored by th...

Page 840: ...ximum conversion speed for differential and single ended conversions are 800ksamp s and 750ksamp s respectively Table 19 47 shows an example of how the ADC0 1_CLK_PS can be set when using a 120 MHz sy...

Page 841: ...N A 0b00010 6 N A N A N A 0b00011 8 N A N A N A 0b00100 10 12 0 800 750 0b00101 12 10 0 667 625 0b00110 14 8 57 571 536 0b00111 16 7 5 500 469 0b01000 18 6 67 444 417 0b01001 20 6 0 400 375 0b01010 2...

Page 842: ...or disabled The time base counter can be reset by writing 0x0000 to the ADC_TBCR Section 19 3 3 3 with a write configuration command 19 4 5 4 ADC Calibration Feature 19 4 5 4 1 Calibration Overview Th...

Page 843: ...it diagram is shown in Figure 19 49 Each on chip ADC has a separate MAC unit to calibrate its conversion results Figure 19 49 MAC Unit Diagram The OCCn operand is a 14 bit signed value and it is the u...

Page 844: ...15 0 GCC_INT GCC_FRAC Figure 19 50 Gain Calibration Constant Format Table 19 48 Gain Calibration Constant Format Field Descriptions Bits Name Description 0 Reserved 1 GCC_INT 0 Integer part of the gai...

Page 845: ...ENTRY0 This is explained below A D conversion accuracy can be affected by the settling time of the input channel multiplexers Some time is required for the channel multiplexer s internal capacitances...

Page 846: ...on Registers EMUX0 EMUX1 Entry1 LST0 Entry0 ADC0 Buffer Entry1 LST1 Entry0 ADC1 Buffer Register Data 0 1 CHANNEL_NUMBER0 CHANNEL_NUMBER1 MESSAGE_TAG1 FMT1 CAL1 MESSAGE_TAG0 FMT0 CAL0 Result Format Cal...

Page 847: ...ifferential conversions can only be initiated on four channels DAN0 DAN1 DAN2 and DAN3 Refer to Table 19 51 and Figure 19 52 for the channel numbers used to select differential conversions MUX Settle...

Page 848: ...nalog input pins but simultaneous conversions are not allowed Also when one ADC is performing a differential conversion on a pair of pins the other ADC must not access either of these two pins as sing...

Page 849: ...A1 and MA2 to select one of eight inputs These three multiplexed address signals are connected to all four external multiplexer chips The analog output of the four multiplex chips are each connected t...

Page 850: ...ield of a command message The eQADC also converts the proper input channel ANW ANX ANY and ANZ by interpreting the CHANNEL_NUMBER field As a result up to 32 externally multiplexed channels appear to t...

Page 851: ...tion 19 3 2 7 eQADC Interrupt and eDMA Control Registers 0 5 EQADC_IDCRn and the interrupt flag bits are described in Section 19 3 2 8 eQADC FIFO and Interrupt Status Registers 0 5 EQADC_FISRn Table 1...

Page 852: ...a 1 to the bit Result FIFO Overflow Interrupt2 2 Apart from generating an independent interrupt request for when a RFIFO overflow interrupt a CFIFO underflow interrupt and a CFIFO trigger overrun int...

Page 853: ...RFDFn RFDSn RFIFO Drain DMA Request DMA Request Generation Logic CFFEn CFFFn CFFSn CFIFO Fill Interrupt Request NCIEn NCFn Non Coherency Interrupt Request PIEn PFn Pause Interrupt Request EOQIEn EOQFn...

Page 854: ...s are disabled ESSIE set to 0b10 no data will be transmitted to the external device but FCK will be free running This operation mode permits the control of the timing of the first serial transmission...

Page 855: ...ge Both the master and the slave drive new data on the serial lines on every FCK positive edge This process continues until all the initial 26 bits in the master shift register are moved into the slav...

Page 856: ...rity CFIFO with commands bound for an external command buffer that is not full Refer to Section 19 4 3 2 CFIFO Prioritization and Command Transfer for more information on aborts and CFIFO priority 19...

Page 857: ...Slave drives second bit due to detection of an asserted SDS on the negative edge of FCK 1 FCK SDS Slave Sample Input tDT Master s SDI 26 25 1 2 3 End Transmission Begin Transmission SDS is asserted be...

Page 858: ...gin an analog to digital conversion a differential input is passed into the analog RSD stage The signal is passed through the RSD stage and then from the RSD stage output back to its input to be passe...

Page 859: ...an entire AD conversion cycle the RSD adder uses these collected values to calculate the 12 bit digital output Figure 19 62 shows the transfer function for the RSD stage Note how the digital value AB...

Page 860: ...ication Also documented in this section are general guidelines on how to initialize the on chip ADCs and the external device and how to configure the command queues and the eQADC Table 19 56 Example A...

Page 861: ...7 eQADC Interrupt and eDMA Control Registers 0 5 EQADC_IDCRn a Set CFFS0 to configure the eQADC to generate an eDMA request to load commands from Queue0 to the CFIFO0 b Set CFFE0 to enable the eQADC t...

Page 862: ...s Step One Set up the command queues and result queues 1 Load the RAM with configuration and conversion commands Table 19 57 is an example of how command queue 1 commands should be set a Each trigger...

Page 863: ...validate the contents of CFIFO1 d Set RFDE3 and CFFE1 to enable the eQADC to generate eDMA requests Command transfers from the RAM to the CFIFO1 will start immediately e Set RFOIE3 to indicate if RFIF...

Page 864: ...t how this functionality is supported The corresponding eDMA channel should be disabled This might be desirable for CFIFOs in single scan mode The source address should be updated to pointed to a vali...

Page 865: ...rrupt enable5 CFUIE5 0 in EQADC_IDCR2 c Clear RFDS5 to configure the eQADC to generate interrupt requests to pop result data from RFIF05 d Set RFIFO drain enable5 RFDE5 1 in EQADC_IDCR5 2 Configure th...

Page 866: ...4 Load the new configuration and conversion commands into RAM Configure the eDMA to support the new command result queue but do not configure it yet to respond to eDMA requests from CFIFOn RFIFOn 5 I...

Page 867: ...have the CAL bit negated 1 VREF VRH VRL CQueue0 Write Command 0 No Results 0x0000 CQueue0 Read Command 1 Results to RQueue0 0x0004 CQueue0 Conversion Command 2 Results to RQueue0 0x0008 CQueue0 Conve...

Page 868: ...ts CAL bit negated and obtain the raw uncalibrated result for 25 VREF RAW_RES25 VREF 2 Convert channel 43 with a command that has its CAL bit negated and obtain the raw uncalibrated result for 75 VREF...

Page 869: ...on During Calibration 19 5 7 eQADC versus QADC This section describes how the eQADC upgrades the QADC functionality The section also provides a comparison between the eQADC and QADC in terms of their...

Page 870: ...FIFOs inside the eQADC much of the terminology or use of the register names register contents and signals of the eQADC involve FIFO instead of queue These register names register contents and signals...

Page 871: ...will pause the queue execution In the eQADC detecting a pause bit in the command will pause command transfers from a CFIFO Queue Operation Mode MQn CFIFO Operation Mode MODEn The eQADC supports all qu...

Page 872: ...oved section 9 2 Detailed Signals from this chapter because this information is contained in the Signals chapter of the Reference Manual Added this cross reference to the EQADC_NMSFR NMF bit Refer to...

Page 873: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 19 118 Freescale Semiconductor...

Page 874: ...ductor 20 1 Chapter 20 Deserial Serial Peripheral Interface DSPI 20 1 Introduction This chapter describes the deserial serial peripheral interface DSPI which provides a synchronous serial bus for comm...

Page 875: ...The DSPI has three configurations Serial peripheral interface SPI configuration where the DSPI operates as an SPI with support for queues Deserial serial interface DSI configuration where the DSPI ser...

Page 876: ...updates to SPI queues Programmable transfer attributes on a per frame basis Eight clock and transfer attribute registers Serial clock with programmable polarity and phase Programmable delays PCS to S...

Page 877: ...d serial chaining of DSPI modules Pin serialization deserialization with interleaved SPI frames for control and diagnostics 20 1 4 Modes of Operation The DSPI has four modes of operation These modes c...

Page 878: ...while the FRZ bit is negated the DSPI behavior is unaffected and remains dictated by the module specific mode and configuration of the DSPI For more information see Section 20 4 1 4 Debug Mode 20 2 Ex...

Page 879: ...are not used 20 2 2 3 Peripheral Chip Select 4 Master Trigger PCS4 MTRIG PCS4 is a peripheral chip select output signal in master mode In slave mode this signal is a master trigger 20 2 2 4 Periphera...

Page 880: ...nd transfer attributes register 6 32 Base 0x0028 DSPIx_CTAR7 DSPI clock and transfer attributes register 7 32 Base 0x002C DSPIx_SR DSPI status register 32 Base 0x0030 DSPIx_RSER DSPI DMA interrupt req...

Page 881: ...FRZ MTFE PCSSE ROOE 0 0 PCSIS 5 PCSIS 4 PCSIS 3 PCSIS 2 PCSIS 1 PCSIS 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr Base 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 MDIS DIS_ TXF DIS_ RXF...

Page 882: ...overwrite existing data If the RX FIFO is full and new data is received the data from the transfer that generated the overflow is either ignored or shifted in to the shift register If the ROOE bit is...

Page 883: ...LR_TXF bit is always read as zero 0 Do not clear the TX FIFO counter 1 Clear the TX FIFO counter 21 CLR_RXF Clear RX FIFO Flushes the RX FIFO Writing a 1 to CLR_RXF clears the RX counter The CLR_RXF b...

Page 884: ...sion on DSPI QSPI compatibility At the initiation of an SPI or DSI transfer control logic selects the DSPIx_CTAR that contains the transfer s attributes The user must not write to the DSPIx_CTARs whil...

Page 885: ...on Register DSPIx_DSICR When the DSPI is configured as a DSI bus slave the DSPIx_CTAR1 register is used In CSI configuration the transfer attributes are selected based on whether the current frame is...

Page 886: ...aud Rate Generator for details on how to compute the baud rate If the overall baud rate is divide by two or divide by three of the system clock then the continuous SCK enable or the modified timing fo...

Page 887: ...ve identical clock phase settings 0 Data is captured on the leading edge of SCK and changed on the following edge 1 Data is changed on the leading edge of SCK and captured on the following edge 7 LSBF...

Page 888: ...ompute the delay after transfer 14 15 PBR 0 1 Baud rate prescaler Selects the prescaler value for the baud rate This field is only used in master mode The baud rate is the frequency of the serial comm...

Page 889: ...ler values The PCS to SCK delay is a multiple of the system clock period and it is computed according to the following equation Note See Section 20 4 6 2 PCS to SCK Delay tCSC for more details Table 2...

Page 890: ...ler values The after SCK delay is a multiple of the system clock period and it is computed according to the following equation Note See Section 20 4 6 3 After SCK Delay tASC for more details Table 20...

Page 891: ...ame The table below lists the scaler values The delay after transfer is a multiple of the system clock period and it is computed according to the following equation Note See Section 20 4 6 4 Delay aft...

Page 892: ...ud rate scaler values The baud rate is computed according to the following equation Note See Section 20 4 6 1 Baud Rate Generator for more details 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TCF TXRXS 0 E...

Page 893: ...eared by writing 1 to it When the EOQF bit is set the TXRXS bit is automatically cleared 0 EOQ is not set in the executing command 1 EOQ bit is set in the executing SPI command Note EOQF does not func...

Page 894: ...counter Indicates the number of valid entries in the TX FIFO The TXCTR is incremented every time the DSPI _PUSHR is written The TXCTR is decremented every time an SPI command is executed and the SPI d...

Page 895: ...n the DSPIx_SR to generate an interrupt request 0 EOQF interrupt requests are disabled 1 EOQF interrupt requests are enabled 4 TFUF_RE Transmit FIFO underflow request enable The TFUF_RE bit enables th...

Page 896: ...e a request The RFDF_DIRS bit selects between generating an interrupt request or a DMA request 0 RFDF interrupt requests or DMA requests are disabled 1 RFDF interrupt requests or DMA requests are enab...

Page 897: ...the MPC5553 MPC5554 DSPI implementation Note The field is only used in SPI master mode 4 EOQ End of queue Provides a means for host software to signal to the DSPI that the current SPI transfer is the...

Page 898: ...er 0 Negate the PCSn signal 1 Assert the PCSn signal Note This bitfield is only used in SPI master mode 16 31 TXDATA 0 15 Transmit data Holds SPI data to be transferred according to the associated SPI...

Page 899: ...e DSPIx_RXFRn registers does not alter the state of the RX FIFO The MPC5553 MPC5554 uses four registers to implement the RX FIFO that is DSPIx_RXFR0 DSPIx_RXFR3 are used 0 1 2 3 4 5 6 7 8 9 10 11 12 1...

Page 900: ...30 31 R RXDATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr Base 0x007C DSPIx_RXFR0 0x0080 DSPIx_RXFR1 0x0084 DSPIx_RXFR2 0x0088 DSPIx_RXFR3 Figure 20 11 DSPI Receive FIFO Registers 0 3 DSPIx_RXFR...

Page 901: ...t signal ht The bit selects which edge will initiate a transfer in the DSI configuration See Section 20 4 4 5 DSI Transfer Initiation Control for more information 0 Falling edge will initiate a transf...

Page 902: ...s is used to provide transfer attributes in DSI configuration The DSICTAS field is used in DSI master mode In DSI slave mode the DSPIx_CTAR1 is always selected The table below shows how the DSICTAS va...

Page 903: ...30 31 R SER_DATA 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr Base 0x00C0 Figure 20 13 DSPI DSI Serialization Data Register DSPIx_SDR Table 20 13 DSPIx_SDR Field Description Bits Name Descrip...

Page 904: ...d 16 31 ASER_DATA 0 15 Alternate serialized data The ASER_DATA field holds the alternate data to be serialized 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0...

Page 905: ...nality of the SPI and DSI configurations The DCONF field in the DSPIx_MCR register determines the DSPI configuration See Table 20 3 for the DSPI configuration values The DSPIx_CTAR0 DSPIx_CTAR7 regist...

Page 906: ...of the configuration in Section 20 4 7 Transfer Formats The transfer rate and delay settings are described in section Section 20 4 6 DSPI Baud Rate and Clock Delay Generation See Section 20 4 10 Powe...

Page 907: ...configured in the DSPI slave for proper communications The SPI and DSI configurations are valid in slave mode CSI configuration is not available in slave mode In SPI slave mode the slave transfer att...

Page 908: ...ffer operations are described in Section 20 4 3 4 Transmit First In First Out TX FIFO Buffering Mechanism and Section 20 4 3 5 Receive First In First Out RX FIFO Buffering Mechanism The interrupt and...

Page 909: ...ftware transmit data and commands are written to the DSPIx_PUSHR and received data is read from the DSPIx_POPR When the TX FIFO is disabled the TFFF TFUF and TXCTR fields in DSPIx_SR behave as if ther...

Page 910: ...Receive First In First Out RX FIFO Buffering Mechanism The RX FIFO functions as a buffer for data received on the SIN pin The RX FIFO holds four received SPI data frames SPI data is added to the RX FI...

Page 911: ...set in the DSPIx_DSICR For more information on the DSPIx_DSICR refer to Section 20 3 2 10 DSPI DSI Configuration Register DSPIx_DSICR The DSPI is in DSI configuration when the DCONF field in the DSPI...

Page 912: ...e system clock The DSPIx_ASDR is written by host software and used as an alternate source of serialized data A copy of the last DSI frame shifted out of the shift register is stored in the DSPIx_COMPR...

Page 913: ...ange In Data Control For change in data control a transfer is initiated when the data to be serialized has changed since the transfer of the last DSI frame A copy of the previously transferred DSI dat...

Page 914: ...Register SIU_DISR for details on how the DSPI deserialized outputs can be used to trigger external interrupt requests 20 4 4 6 1 DSPI_A Connectivity MPC5554 Only The DSPI_A connects to the eTPU_B as...

Page 915: ...Input 1 on IMUX for External IRQ 3 4 eTPU_A Output Channel 19 4 Input 1 on IMUX for External IRQ 4 5 eTPU_A Output Channel 18 5 Input 1 on IMUX for External IRQ 5 6 eTPU_A Output Channel 17 6 Input 1...

Page 916: ...n Connected to 0 eTPU_A Output Channel 12 0 Input 2 on IMUX for External IRQ 15 1 eTPU_A Output Channel 13 1 Input 2 on IMUX for External IRQ 0 2 eTPU_A Output Channel 14 2 Input 2 on IMUX for Externa...

Page 917: ...IMUX for External IRQ15 2 eTPU_A Output Channel 19 2 N C 3 eTPU_A Output Channel 18 3 N C 4 eTPU_A Output Channel 17 4 Input 3 on IMUX for External IRQ 2 5 eTPU_A Output Channel 16 5 Input 3 on IMUX...

Page 918: ...d multiple bus slaves The bus master initiates and controls the transfers but the DSPI slaves generate trigger signals for the bus DSPI master when an internal condition in the slave warrants a transf...

Page 919: ...UX subblock of the SIU The SOUT MTRIG SCK and PCS0 outputs from the other three DSPIs connect to the multiplexers on the DSPI_A inputs DSPI_B DSPI_C and DSPI_D have similar multiplexers on their input...

Page 920: ...ct register SIU_DSR selects the source for each DSPI SIN SS SCK and ht signal individually 20 4 4 7 2 Parallel Chaining Parallel chaining allows the PCS and SCK signals from a master DSPI to be shared...

Page 921: ...sserts the MTRIG signal that propagates to DSPI_A MPC5554 DSPI_B MPC5553 which initiates the transfer In the MPC5554 DSPI_B propagates trigger signals from DSPI_C to DSPI_A In the MPC5554 DSPI_C propa...

Page 922: ...e DSPI_D and so on slave The SOUT of the last on chip DSPI slave is connected to the SIN of the external SPI slave The SOUT of the external SPI slave is connected to the SIN of DSPI_A master MPC5554 D...

Page 923: ...rames from the parallel input signals from the eTPU or eMIOS with SPI commands and data from the TX FIFO The data returned from the bus slave is either used to drive the parallel output signals to the...

Page 924: ...DSI Serialization Data Register DSPIx_SDR SPI frames written to the TX FIFO have priority over DSI data from the DSPIx_SDR and are transferred at the next frame boundary A copy of the most recently tr...

Page 925: ...DSPIx_CTAR BR to produce SCK with the possibility of doubling the baud rate The DBR PBR and BR fields in the DSPIx_CTARs select the frequency of SCK using the following formula Table 20 23 shows an e...

Page 926: ...nsfer is the length of time between negation of the PCS signal for a frame and the assertion of the PCS signal for the next frame See Figure 20 36 for an illustration of the delay after transfer The P...

Page 927: ...ASC field in the DSPIx_CTAR based on the following formula Table 20 27 shows an example of the computed tPCSSCK delay Table 20 28 shows an example of the computed the tPASC delay 20 4 7 Transfer Forma...

Page 928: ...e DSPI can sample the incoming data later than halfway through the cycle to give the peripheral more setup time The MTFE bit in the DSPIx_MCR selects between classic SPI format and modified transfer f...

Page 929: ...ondition of the master TCF and EOQF are set and the RXCTR counter is updated at the next to last serial clock edge of the frame edge 15 of Figure 20 36 For the CPHA 0 condition of the slave TCF is set...

Page 930: ...SI Transfer Format MTFE 1 CPHA 0 In this modified transfer format both the master and the slave sample later in the SCK period than in classic SPI mode to allow for delays in device pads and board tra...

Page 931: ...sfer format for CPHA 1 Only the condition where CPOL 0 is described At the start of a transfer the DSPI asserts the PCS signal to the slave device After the PCS to SCK delay has elapsed the master and...

Page 932: ...ous selection format is enabled for the SPI configuration by setting the CONT bit in the SPI command Continuous selection is enabled for the DSI configuration by setting the DCONT bit in the DSPIx_DSI...

Page 933: ...increased if a full half clock period is required Switching CTARs between frames while using continuous selection can cause errors in the transfer The PCS signal must be negated before CTAR is switche...

Page 934: ...be used When the DSPI is in DSI configuration the CTAR specified by the DSICTAS field shall be used at all times When the DSPI is in CSI configuration the CTAR selected by the DSICTAS field shall be...

Page 935: ...1 20 4 9 Interrupts DMA Requests The DSPI has five conditions which can only generate interrupt requests and two conditions that can generate interrupt or DMA request Table 20 30 lists the six conditi...

Page 936: ...he transfer of a serial frame The transfer complete request is generated at the end of each frame transfer when the TCF_RE bit is set in the DSPIx_RSER See the TCF bit description in Section 20 3 2 4...

Page 937: ...FIFO pop register will not change the state of the RX FIFO Likewise writing to the TX FIFO push register will not change the state of the TX FIFO Clearing either of the FIFOs will not have any affect...

Page 938: ...x_SR after each read operation of the DSPIx_POPR 7 Modify DMA descriptor of TX and RX channels for new queues 8 Flush TX FIFO by writing a 1 to the CLR_TXF bit in the DSPIx_MCR Flush RX FIFO by writin...

Page 939: ...caler Values DSPI_CTAR BR 2 25 0 MHz 16 7 MHz 10 0 MHz 7 14 MHz 4 12 5 MHz 8 33 MHz 5 00 MHz 3 57 MHz 6 8 33 MHz 5 56 MHz 3 33 MHz 2 38 MHz 8 6 25 MHz 4 17 MHz 2 50 MHz 1 79 MHz 16 3 12 MHz 2 08 MHz 1...

Page 940: ...es the customer can recompute the values using the information presented in Section 20 5 3 Delay Settings For BITSE 0 8 bits per transfer For DT 0 0 425 s delay For this value the closest value in the...

Page 941: ...over to the RX FIFO See Section 20 4 3 4 Transmit First In First Out TX FIFO Buffering Mechanism and Section 20 4 3 5 Receive First In First Out RX FIFO Buffering Mechanism for details on the FIFO op...

Page 942: ...d by the following equation Last in entry address RX FIFO base 4 RXCTR POPNXTPTR 1 modulo RX FIFO depth RX FIFO base base address of RX FIFO RXCTR RX FIFO counter POPNXTPTR pop next pointer RX FIFO de...

Page 943: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 20 70 Freescale Semiconductor Table 20 35 Changes added to MPC5553 5554 for Rev 5 0 Release Description of Change No change for Rev 5 release...

Page 944: ...I Block Diagram IRQ Generation Receive Wake up Control Receive Shift Register eSCI Data Register LIN Receive Register LIN Transmit Register DMA Interface TX DMA RX DMA RDRF OR IRQ ORING IRQ to CPU Dat...

Page 945: ...the slave bus The MDIS bit is intended to be used when the module is not required in the application 21 1 3 Features The eSCI includes these distinctive features Full duplex operation Standard mark s...

Page 946: ...s section provides a detailed description of all memory and registers 21 3 2 Module Memory Map The memory map for the eSCI module is given below in Table 21 2 The address offset is listed for each reg...

Page 947: ...0 0 0 SBR 0 SBR 1 SBR 2 SBR 3 SBR 4 SBR 5 SBR 6 SBR 7 SBR 8 SBR 9 SBR 10 SBR 11 SBR 12 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Reg Addr Base 0x0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R LO...

Page 948: ...racter or an idle condition on the RXD 0 Idle line wake up 1 Address mark wake up Note This is not a wake up out of a power save mode it refers solely to the receiver standby mode 21 ILT Idle line typ...

Page 949: ...Ix_SR RDRF and the overrun flag ESCIx_SR OR to generate interrupt requests The interrupt is suppressed in RX DMA mode 0 RDRF and OR interrupt requests disabled 1 RDRF and OR interrupt requests enabled...

Page 950: ...ESCIx_CR2 Field Description Bits Name Description 0 MDIS Module disable By default the module is enabled but can be disabled by writing a 1 to this bit DMA requests are negated if the device is in mo...

Page 951: ...at RT clock 13 see Section 21 4 5 3 Data Sampling 9 SBSTP SCI bit error stop Stops the SCI when a bit error is asserted This allows to stop driving the LIN bus quickly after a bit error has been detec...

Page 952: ...pt for RAF are cleared by writing 1 to them 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R R8 T8 0 0 0 0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr B...

Page 953: ...s set high when the TDRE flag is set and no data preamble or break character is being transmitted When TC is set the TXD out signal becomes idle logic 1 After the device is switched on by clearing the...

Page 954: ...If FBR 0 checking happens after a complete byte has been transmitted and received again If FBR 1 checking happens bit by bit This bit is only used for LIN mode BERR is also set if an unrequested byte...

Page 955: ...rect 0 No error 1 CRC error 22 CKERR Checksum error Checksum error on a received frame 23 FRC Frame complete LIN frame completely transmitted All LIN data bytes received 24 30 Reserved 31 OVFL ESCIx_L...

Page 956: ...cally resetting after an exception bit error physical bus error wake up flag has been received This is for debug purposes only 5 DSF Double stop flags When a bit error has been detected this will add...

Page 957: ...wards a new frame starts and the first byte needs to contain a header again Additionally it is possible to flush the ESCIx_LTR by setting the ESCIx_LCR LRES bit NOTE Not all values written to the ESCI...

Page 958: ...Reg Addr Base 0x10 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr Base 0x0010 Figure 21 7 LIN Transmit Register ESCI...

Page 959: ...d LIN 1 x slaves will only accept frames with 2 4 or 8 data bytes 8 31 Reserved Table 21 10 ESCIx_LTR Third Byte Field Descriptions Bits Name Description 0 HDCHK Header checksum enable Include the hea...

Page 960: ...t times The timeout period starts with the transmission of the LIN break character 8 31 Reserved Table 21 11 ESCIx_LTR Rx Frame Fourth Byte Field Descriptions Bits Name Description 0 7 Tn Timeout bit...

Page 961: ...on will not be available in the ESCIx_LRR unless they are treated as data It is possible to treat CRC and checksum bytes as data by deactivating the CSUM respectively CRC control bits in the ESCIx_LTR...

Page 962: ...ived data Figure 21 11 eSCI Operation Block Diagram 21 4 2 Data Format The eSCI uses the standard NRZ mark space data format Each data character is contained in a frame that includes a start bit eight...

Page 963: ...the eSCI control register 1 ESCIx_CR1 The baud rate clock is synchronized with the system clock and drives the receiver The baud rate clock divided by 16 drives the transmitter The receiver has an acq...

Page 964: ...554 57 600 0 01 0x00D0 615 385 38 462 38 400 0 16 0x01A1 306 954 19 185 19 200 0 08 0x022C 230 216 14 388 14 400 0 08 0x0341 153 661 9 604 9600 04 0x0683 76 785 4 799 4800 0 02 0x0D05 38 404 2 400 2 2...

Page 965: ...if this bit is set b Select a baud rate Write this value to the eSCI control register 1 ESCIx_CR1 to start the baud rate generator Remember that the baud rate generator is disabled when the ESCIx_CR1...

Page 966: ...n a message always wait for TDRE to go high after the last frame before clearing TE To separate messages with preambles with minimum idle line time use the following sequence between messages 1 Write...

Page 967: ...es data previously written to the eSCI data register to be lost Toggle the TE bit for a queued idle character while the TDRE flag is set and immediately before writing the next byte to the eSCI data r...

Page 968: ...Character Length The eSCI receiver can accommodate either 8 bit or 9 bit data characters The state of the M bit in eSCI control register 1 ESCIx_CR1 determines the length of data characters When rece...

Page 969: ...nchronized After every start bit After the receiver detects a data bit change from logic 1 to logic 0 This data bit change is detected when a majority of data samples return a valid logic 1 and a majo...

Page 970: ...bit samples are logic 1s following a successful start bit verification the noise flag NF is set To verify a stop bit and to detect noise recovery logic takes samples at RT8 RT9 and RT10 Table 21 20 su...

Page 971: ...to fall outside the actual stop bit A noise error will occur if the RT8 RT9 and RT10 samples are not all the same logical values A framing error will occur if the receiver clock is misaligned in such...

Page 972: ...nt and the transmitter count of a slow 9 bit character with no errors is 4 19 as is shown below 21 4 5 5 2 Fast Data Tolerance Figure 21 20 shows how much a fast received frame can be misaligned The f...

Page 973: ...idle line wake up or address mark wake up 21 4 5 6 1 Idle Input Line Wake up WAKE 0 Using the receiver idle input line wake up method allows an idle condition on the RXD signal clears the ESCIx_CR1 R...

Page 974: ...nsmitting Figure 21 21 Single Wire Operation LOOPS 1 RSRC 1 Enable single wire operation by setting the LOOPS bit and the receiver source bit RSRC in eSCI control register 1 ESCIx_CR1 Setting the LOOP...

Page 975: ...RSRC bit connects the transmitter output to the receiver input Both the transmitter and receiver must be enabled TE 1 and RE 1 21 4 8 Modes of Operation 21 4 8 1 Run Mode This is the normal mode of op...

Page 976: ...plete Receiver RDRF ESCIx_SR 2 RIE Indicates that received data is available in the eSCI data register Receiver IDLE ESCIx_SR 3 ILIE Indicates that receiver input has become idle Receiver OR ESCIx_SR...

Page 977: ...tes that the received data has been transferred to the eSCI data register and that the received data can now be read by the MCU The RDRF bit is cleared by writing a one to the RDRF bit location in the...

Page 978: ...p mode The LWAKE flag is cleared by writing a 1 to the bit 21 4 9 2 13 STO Description The slave timeout STO flag is set during an RX frame when the LIN slave has not transmitted all requested data by...

Page 979: ...provided by the LIN master TX frame or by the LIN slave RX frame The header fields will always be generated by the LIN master Figure 21 23 Typical LIN frame The LIN hardware is highly configurable Th...

Page 980: ...to the ESCIx_LTR must contain the LIN ID field The next write to ESCIx_LTR specifies the length of the frame 0 to 255 Bytes The third write to ESCIx_LTR contains the control byte frame direction check...

Page 981: ...interface or by polling to detect incoming data bytes The checksum byte normally does not appear in the ESCIx_LRR instead the LIN hardware will verify the checksum and issue an interrupt if the checks...

Page 982: ...ion software for example by setting a timer Both LIN masters and LIN slaves can cause the bus to exit sleep mode by sending a break signal The LIN hardware will generate such a break when WU bit in th...

Page 983: ...until the BERR flag has been cleared Set ESCIx_LCR LDBG 0 ESCIx_CR2 SBSTP 1 and ESCIx_CR2 BSTP 1 to accomplish these functions h Fast bit error detection provides superior error checking so ESCIx_CR2...

Page 984: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 Freescale Semiconductor 21 41...

Page 985: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 21 42 Freescale Semiconductor...

Page 986: ...er area network FlexCAN2 modules the MPC5553 contains two FlexCAN2 modules Each FlexCAN2 module is a communication controller implementing the CAN protocol according to CAN Specification version 2 0B...

Page 987: ...ng the specific requirements of this field real time processing reliable operation in the EMI environment of a vehicle cost effectiveness and required bandwidth The FlexCAN2 module is a full implement...

Page 988: ...Content related addressing 64 flexible message buffers of 0 to 8 bytes data length Each MB configurable as RX or TX all supporting standard and extended messages Includes 1024 bytes of RAM used for MB...

Page 989: ...is ignored and the transmit output CNTXx goes to the recessive state logic 1 FlexCAN behaves as it normally does when transmitting and treats its own transmitted message as a message received from a r...

Page 990: ...ap for a FlexCAN2 module with its 64 MBs is shown in Table 22 2 Except for the base addresses the three MPC5554 or two MPC5553 FlexCAN2 modules have identical memory maps Each individual register is i...

Page 991: ...andard frames 29 bit identifier and 11 bit identifier respectively used in the CAN specification version 2 0 Part B are represented Base 0x0060 Base 0x007F Reserved Base 0x0080 Base 0x017F MB0 MB15 Me...

Page 992: ...cates the current MB has a data frame to be transmitted 1 Indicates the current MB has a remote frame to be transmitted LENGTH Length of data in bytes This 4 bit field is the length in bytes of the RX...

Page 993: ...yet another new frame must be written the MB will be overwritten again and the code will remain OVERRUN Refer to Section 22 4 3 1 Matching Process for details about overrun behavior 0XY11 BUSY FlexCAN...

Page 994: ...ID of the incoming remote request frame with the ID of the MB If a match occurs this MB is allowed to participate in the current arbitration process and the CODE field is automatically updated to 111...

Page 995: ...s FlexCAN2 to exit from freeze mode 0 Not enabled to enter freeze mode 1 Enabled to enter freeze mode 2 Reserved 3 HALT Halt FlexCAN Assertion of this bit puts the FlexCAN2 module into freeze mode if...

Page 996: ...ed until current transmission and reception processes have finished Therefore the software can poll the FRZACK bit to know when FlexCAN2 has actually entered freeze mode If freeze mode request is nega...

Page 997: ...FF REC TSYN LBUF LOM PROPSEG W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr Base 0x0004 1 CANx_CR is unaffected by soft reset which occurs when CAN_MCR SOFTRST is asserted Figure 22 4 Control Regist...

Page 998: ...recovery mode Defines how FlexCAN2 recovers from bus off state If this bit is negated automatic recovering from bus off state occurs according to the CAN Specification 2 0B If the bit is asserted auto...

Page 999: ...internal request acknowledge procedure across clock domains is executed All this is transparent to the user except for the fact that the data will take some time to be actually written to the registe...

Page 1000: ...9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr Base 0x0008 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R TIMER W Reset 0 0 0 0 0 0 0 0 0 0...

Page 1001: ...7 8 9 10 11 12 13 14 15 R 0 0 0 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16 W Reset1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 Reg Addr Base 0x0010 CANx_RXGMASK Base 0x0014 CANx_RX14MASK Ba...

Page 1002: ...ver when the data was actually written FlexCAN2 responds to any bus state as described in the protocol transmitting for example an error active or error passive flag delaying its transmission start ti...

Page 1003: ...re those that occurred since the last time the CPU read this register The CPU read action clears BIT1ERR BIT0ERR ACKERR CRCERR FRMERR and STFERR TXWRN RXWRN IDLE TXRX FLTCONF BOFFINT and ERRINT are st...

Page 1004: ...ror Indicates when an inconsistency occurs between the transmitted and the received message in a bit A read clears BIT0ERR 0 No such occurrence 1 At least one bit sent as dominant is received as reces...

Page 1005: ...us is not in IDLE state This bit has no meaning when IDLE is asserted 0 FlexCAN2 is receiving a message IDLE 0 1 FlexCAN2 is transmitting a message IDLE 0 26 27 FLTCONF 0 1 Fault confinement state Thi...

Page 1006: ...33M BUF 32M W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr Base 0x0024 Figure 22 9 Interrupt Masks High Register CANx_IMRH Table 22 12 CANx_IMRH Field Descriptions Bits Name Description 0 31 BUFnM M...

Page 1007: ...e buffer MB31 to MB0 Interrupt 0 The corresponding buffer Interrupt is disabled 1 The corresponding buffer Interrupt is enabled Note Setting or clearing a bit in the IMRL register can assert or negate...

Page 1008: ...29 30 31 R BUF 15I BUF 14I BUF 13I BUF 12I BUF 11I BUF 10I BUF 09I BUF 08I BUF 07I BUF 06I BUF 05I BUF 04I BUF 03I BUF 02I BUF 01I BUF 00I W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c...

Page 1009: ...nd then transmitted The arbitration process is triggered in the following events During the CRC field of the CAN frame During the error delimiter field of the CAN frame During Intermission if the winn...

Page 1010: ...unning timer optional releases internal lock Reading the free running timer is not mandatory If not executed the MB remains locked unless the CPU starts reading another MB Note that only a single MB i...

Page 1011: ...has scanned the second 22 4 4 1 Notes on TX Message Buffer Deactivation There is a point in time until which the deactivation of a TX MB causes it not to be transmitted end of move out After this poi...

Page 1012: ...010 If there is a matching ID then this MB frame will be transmitted Note that if the matching MB has the RTR bit set then FlexCAN2 will transmit a remote frame as a response A received remote request...

Page 1013: ...hree segments1 reference Figure 22 13 and Table 22 16 SYNCSEG This segment has a fixed length of one time quantum Signal edges are expected to happen within this section Time segment 1 This segment in...

Page 1014: ...ons must be observed A valid CAN bit timing must be programmed as indicated in Figure 22 14 The system clock frequency cannot be smaller than the oscillator clock frequency i e the PLL cannot be progr...

Page 1015: ...se FlexCAN2 can operate in an unpredictable way In freeze mode all memory mapped registers are accessible Exiting freeze mode is done in one of the following ways CPU negates the FRZ bit in the CANx_M...

Page 1016: ...This interrupt gets generated when any of the MBs generates an interrupt In this case the CPU must read the CANx_IFRH and CANx_IFRL registers to determine which MB caused the interrupt The other two...

Page 1017: ...nitialization it is required that FlexCAN2 is put into freeze mode see Section 22 4 6 1 Freeze Mode The following is a generic initialization sequence applicable for the FlexCAN2 module Initialize CAN...

Page 1018: ...ived one and if a match occurs the frame is transferred move in to the first that is lowest entry matching MB To The matching process compares the IDs of all active RX message buffers to newly receive...

Page 1019: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 22 34 Freescale Semiconductor...

Page 1020: ...d POR module is shown in Figure 23 1 The diagram represents the various submodules as implemented on the MPC5553 MPC5554 Figure 23 1 Voltage Regulator Controller and POR Blocks 23 2 External Signal De...

Page 1021: ...for VRCCTL VRCSNS is a pad on the die that is connected to a VDD plane inside the package It is not a package ball 23 2 1 6 VRCCTL The VRCCTL sources base current to the external bypass transistor The...

Page 1022: ...n external power supply is used external 3 3 V must power VRC33 while the VRCCTL pad is unconnected In this case the internal 1 5 V POR will remain enabled If the VRC33 is not powered the device is su...

Page 1023: ...he user does not power VRC33 to the specified voltage the 1 5 V POR will be disabled and the user must follow the specified power sequence 23 4 2 2 3 3V POR Circuit The 3 3 V POR circuit is used to en...

Page 1024: ...external 1 5 V power supply and ties VRC33 to ground To avoid this power sequencing requirement the user should power up VRC33 within the specified operating range even if not using the on chip voltag...

Page 1025: ...ure that digital logic in the PLL on the 1 5 V supply will not begin to operate below the specified operation range lower limit of 1 35 V Because the internal 1 5 V POR is disabled the internal 3 3 V...

Page 1026: ...of whether VRC33 is powered The VDD33_LAG specification only applies during power up VDD33 has no lead or lag requirements when powering down 23 5 3 4 Pin Values after Negation of POR Depending on the...

Page 1027: ...te AN3254 for the size of the resistor Also in the Note below that changed it to See Application Note AN3524 In Section 23 5 2 Recommended Power Transistors made this change From Freescale recommends...

Page 1028: ...ion The JTAG port of the MPC5553 MPC5554 consists of four inputs and one output These pins include JTAG compliance select JCOMP test data input TDI test data output TDO test mode select TMS and test c...

Page 1029: ...e 24 1 is a block diagram of the JTAG Controller JTAGC Figure 24 1 JTAG Controller Block Diagram TCK TMS TDI Test Access Port TAP TDO 32 Bit Device Identification Register Boundary Scan Register Contr...

Page 1030: ...TAGC uses JCOMP and a power on reset indication as its primary reset signals Several IEEE 1149 1 2001 defined test modes are supported as well as a bypass mode 24 1 4 1 Reset The JTAGC is placed in re...

Page 1031: ...TAP_eTPUN3 and ACCESS_AUX_TAP_DMAN3 Instruction opcodes for each instruction are shown in Table 24 3 When the access instruction for an auxiliary TAP is loaded control of the JTAG pins is transferred...

Page 1032: ...s entry into the test logic reset state results in asynchronous loading of the IDCODE instruction During the capture IR TAP controller state the instruction shift register is loaded with the value 0b1...

Page 1033: ...54 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R PIN MIC 1 W Reset MPC5553 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 1 Reset MPC5554 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 Figure 24 3...

Page 1034: ...detail on TAP sharing via JTAGC instructions refer to Section 24 4 4 2 ACCESS_AUX_TAP_x Instructions Data is shifted between TDI and TDO though the selected register starting with the least significan...

Page 1035: ...ESET RUN TEST IDLE SELECT DR SCAN SELECT IR SCAN CAPTURE DR CAPTURE IR SHIFT DR SHIFT IR EXIT1 DR EXIT1 IR PAUSE DR PAUSE IR EXIT2 DR EXIT2 IR UPDATE DR UPDATE IR 1 0 1 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0...

Page 1036: ...able 24 3 This section gives an overview of each instruction refer to the IEEE 1149 1 2001 standard for more details Table 24 3 JTAG Instructions Instruction Code 4 0 Instruction Summary IDCODE 00001...

Page 1037: ...the overall shift path to a single bit the bypass register while conducting an EXTEST type of instruction through the boundary scan register CLAMP also asserts the internal system reset for the MCU to...

Page 1038: ...perform boundary scan tests This is achieved by shifting in initialization data to the boundary scan register during the shift DR state The initialization data is transferred to the parallel outputs o...

Page 1039: ...escale Semiconductor 24 6 Revision History Table 24 4 Changes to MPC5553 5554 RM for Rev 4 0 Release Description of Change No changes since the 3 1 release Table 24 5 Changes to MPC5553 5554 RM for Re...

Page 1040: ...ation about the NDEDI Nexus e200z6 core interface NZ6C3 In this chapter the NZ6C3 interface is discussed in Section 25 10 e200z6 Class 3 Nexus Module NZ6C3 through Section 25 11 NZ6C3 Memory Map Regis...

Page 1041: ...ns Auxiliary output port 1 MCKO message clock out pin 4 or 12 MDO message data out pins 2 MSEO message start end out pins 1 RDY ready pin 1 EVTO event out pin JCOMP Program Data Ownership Watchpoint T...

Page 1042: ...liary port Watchpoint trigger enable disable of data trace messaging eTPU development support features NDEDI IEEE ISTO 5001 2002 standard Class 3 compliant for the eTPU engines Data trace via data wri...

Page 1043: ...The message queues are marked as empty The auxiliary output port pins are negated if the NDI controls the pads The TDO output buffer is disabled if the NDI has control of the TAP The TDI TMS and TCK...

Page 1044: ...ation or to signify that an event has occurred The EVTO output of the NPC is generated based on the values of the individual EVTO signals from all Nexus modules that implement the signal 25 2 1 2 Even...

Page 1045: ...sserted otherwise the TAP controller remains in reset 25 2 1 7 Test Data Output TDO The TDO pin transmits serial output for instructions and data TDO is tri stateable and is actively driven in the SHI...

Page 1046: ...C_DTC 0b0000 14 e200z6 Data Trace Start Address 0 PPC_DTSA1 0b0000 15 e200z6 Data Trace Start Address 1 PPC_DTSA2 0b0000 18 e200z6 Data Trace End Address 0 PPC_DTEA1 0b0000 19 e200z6 Data Trace End Ad...

Page 1047: ...eTPU1 Breakpoint Watchpoint Data 1 NDEDI_eTPU1_BWD1 0b0010 39 eTPU1 Breakpoint Watchpoint Data 1 NDEDI_eTPU1_BWD2 0b0010 64 eTPU1 Program Trace Channel Enable NDI_eTPU1_PTCE 0b0010 69 eTPU1 Microinstr...

Page 1048: ...PU2_CFSR 0bxxxx 127 Port Configuration Register PCR eTPU CDC Control Status Registers 0b0100 13 eTPU CDC Data Trace Control NDEDI_CDC_DTC eTPU1 eTPU2 CDC Shared Control Status Registers 0b0010 or 0b00...

Page 1049: ...0000 Instruction Address Compare 1 IAC1 010 0001 Instruction Address Compare 2 IAC2 010 0010 Instruction Address Compare 3 IAC3 010 0011 Instruction Address Compare 4 IAC4 010 0100 Data Address Compar...

Page 1050: ...guration options Table 25 4 JTAG Client Select Instructions JTAGC Instruction Opcode Description ACCESS_AUX_TAP_NPC 10000 Enables access to the NPC TAP controller ACCESS_AUX_TAP_ONCE 10001 Enables acc...

Page 1051: ...mitted by the NDI include a SRC field This field is used to identify which source generated the message Figure 25 8 shows the values used for the SRC field by the different clients on the MPC5553 MPC5...

Page 1052: ...incorporates multiple modules that require development support Each of these modules implements a development interface based on the IEEE ISTO 5001 2001 standard and must share the input and output p...

Page 1053: ...re DR state the single bit shift register is set to a logic 0 Therefore the first bit shifted out after selecting the bypass register is always a logic 0 25 6 2 2 Instruction Register The NPC uses a 4...

Page 1054: ...r MPC5553 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 Reset for MPC5554 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Reg Index 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PIN MIC 1 W Reset for MPC5553 0 0 1 1 0 0 0 0 0 0 0 1 1...

Page 1055: ...0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Index 127 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSTAT _EN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Index 127 Figure 25...

Page 1056: ...ermines the frequency of MCKO relative to the system clock frequency when MCKO_EN is asserted The table below shows the meaning of MCKO_DIV values In this table SYS_CLK represents the system clock fre...

Page 1057: ...e used to signal the end of variable length packets and the end of messages They are not required to indicate the end of fixed length packets MDO and MSEO are sampled on the rising edge of MCKO Figure...

Page 1058: ...n following a fixed length field Super fields must end on a port boundary When a variable length field is sized such that it does not end on a port boundary it is necessary to extend and zero fill the...

Page 1059: ...e 25 14 The value of the NEXUS ENABLE instruction is 0b0000 Each unimplemented instruction acts like the BYPASS instruction The size of the NPC instruction register is 4 bits Data is shifted between T...

Page 1060: ...R state At this point the Nexus controller state machine shown in Figure 25 9 transitions to the REG_SELECT state The Nexus controller has three states idle register select and data access Table 25 15...

Page 1061: ...R state When reading a register there is no requirement to shift out the entire register contents Shifting may be terminated after the required number of bits have been acquired Table 25 16 illustrate...

Page 1062: ...perating frequencies include one half one quarter and one eighth system clock speed The MPC5553 can run at the full system clock frequency MCKO is enabled by setting the MCKO_EN bit in the PCR The NPC...

Page 1063: ...equired 1 Write the 7 bit register index and set the write bit to select the register with a pass through the SELECT DR SCAN path in the TAP controller state machine 2 Write the register value with a...

Page 1064: ...0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Reg Index 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PIN MIC 1 W Reset for MPC5553 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 Reset for MPC5554 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 Reg I...

Page 1065: ...s section references are made to the auxiliary port and its specific signals such as MCKO MSEO 0 1 MDO 11 0 and others In actual use the MPC5553 MPC5554 NPC module arbitrates the access of the single...

Page 1066: ...ssage DRM External visibility of data reads to memory mapped resources Data Write Message DWM External visibility of data writes to memory mapped resources Data Trace Messaging DTM External visibility...

Page 1067: ...ion refer to Table 25 5 For the e200z6 Class 3 Nexus module the OCMD value is 0b00_0111_1100 After it is enabled the module will be ready to accept control input via the JTAG pins See Section 25 4 1 E...

Page 1068: ...3 DSIZ Fixed data size Refer to Table 25 23 1 32 U ADDR Variable unique portion of the data write address 1 64 DATA Variable data write values see Section 25 11 13 Data Trace for details Data Trace D...

Page 1069: ...TA Variable data read values see Section 25 11 13 Data Trace for details Watchpoint Message 6 6 TCODE Fixed TCODE number 15 0x0F 4 4 SRC Fixed source processor identifier 4 4 WPHIT Fixed indicating wa...

Page 1070: ...8 I CNT Variable sequential instructions executed since last taken branch 1 32 HIST Variable branch predicate instruction history see Section 25 11 12 1 Branch Trace Messaging BTM 1 The user can sele...

Page 1071: ...the IEEE ISTO 5001 standard Table 25 24 details the register map for the NZ6C3 module Table 25 21 RCODE values TCODE 27 Resource Code RCODE Description 0001 Program trace branch predicate instruction...

Page 1072: ...hey are only present at the top level Nexus3 controller NPC not in the NZ6C3 module The device s CSC register is readable through Nexus3 but the PCR is shown for reference only 0x02 See NPC PCR Port c...

Page 1073: ...onfiguration 12 MDO pins 30 29 MCK_DIV 1 0 1 MCKO clock divide ratio 00 MCKO is 1x processor clock freq 01 MCKO is 1 2x processor clock freq 10 MCKO is 1 4x processor clock freq 11 MCKO is 1 8x proces...

Page 1074: ...et 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Nexus Reg 0x3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Nexus Reg 0x3 Figure 25 14 Development...

Page 1075: ...ess to memory mapped resources on the system bus either while the processor is halted or during runtime The RWCS register also provides read write access status information as shown in Table 25 29 31...

Page 1076: ...0 Read access 1 Write access 29 27 SZ 2 0 Word size 000 8 bit byte 001 6 bit halfword 010 32 bit word 011 64 bit doubleword only in burst mode 100 111 Reserved default to word 26 24 MAP 2 0 MAP select...

Page 1077: ...ed Write access completed without error 0 0 Read access error has occurred Write access error has occurred 1 0 Read access completed without error Write access has not completed 0 1 Not allowed Not al...

Page 1078: ...0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Nexus Reg 0xB Figure 25 19 Watchpoint Trigger Register WT Table 25 30 WT Field Descriptions Bits Name Description 31 29 PTS 2 0 Program trace start c...

Page 1079: ...watchpoint 1 IAC2 from Nexus1 011 Use watchpoint 2 IAC3 from Nexus1 100 Use watchpoint 3 IAC4 from Nexus1 101 Use watchpoint 4 DAC1 from Nexus1 110 Use watchpoint 5 DAC2 from Nexus1 111 Use watchpoin...

Page 1080: ...on address within range 1 Condition trace on address outside of range 6 RC2 Range control 2 0 Condition trace on address within range 1 Condition trace on address outside of range 5 4 Reserved 3 DI1...

Page 1081: ...s Reg 0xF Figure 25 22 Data Trace Start Address Register 2 DTSA2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Data Trace End Address W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Nexus Reg 0x12 15 14 1...

Page 1082: ...writing of a NZ6C3 register then requires two 2 passes through the data scan DR path of the JTAG state machine see Section 25 11 17 1 The first pass through the DR selects the NZ6C3 register to be ac...

Page 1083: ...ere is one condition that will cause an ownership trace message When new information is updated in the OTR register or process ID register by the e200z6 processor the data is latched within Nexus and...

Page 1084: ...200z6 virtual address bus between the CPU and MMU attribute signals and CPU status 25 11 12 1 Branch Trace Messaging BTM Traditional branch trace messaging facilitates program trace by providing the f...

Page 1085: ...its in the history field Branch history messages solve predicated instruction tracking and save bandwidth because only indirect branches cause messages to be queued 25 11 12 1 4 BTM Using Traditional...

Page 1086: ...Branch Messages Traditional If DC PTM is cleared indirect branch information is messaged out in the following format Figure 25 28 Indirect Branch Message Format 25 11 12 2 3 Direct Branch Messages Tra...

Page 1087: ...5 11 12 2 5 Debug Status Messages Debug status messages report low power mode and debug status Entering exiting debug mode as well as entering a low power mode will trigger a debug status message Debu...

Page 1088: ...nditions see Table 25 35 Initial program trace message upon the first direct indirect branch after exit from system reset or whenever program trace is enabled Upon direct indirect branch after returni...

Page 1089: ...queue being full The FIFO will discard messages until it has completely emptied the queue After it is emptied an error message will be queued The error encoding will indicate which types of messages...

Page 1090: ...ously decoded address gives the current address Previous address A1 0x0003FC01 New address A2 0x0003F365 Attempted Access to Secure Memory For devices which implement security any attempted branch to...

Page 1091: ...cond conditions 25 11 12 3 4 Sequential Instruction Count I CNT The I CNT packet is present in all BTM messages For traditional branch messages I CNT represents the number of sequential instructions o...

Page 1092: ...Address 0xA5 01 11 00 MDO 11 0 0000 0010 0000 0000 1010 0101 0000 0000 0100 TCODE 28 MCKO MSEO Source Processor 0b0000 Number of Sequential Instructions 0 Relative Address 0xA5 Branch History 0b1010_...

Page 1093: ...ll be traced Data trace messaging can be enabled in one of two ways Setting the TM field of the DC1 register to enable data trace DC1 TM Using WT DTS to enable data trace on watchpoint hits e200z6 wat...

Page 1094: ...f a watchpoint also attempts to be queued while the FIFO is being emptied then the error message will incorporate error encoding 01000 NOTE The OVC bits within the DC1 register can be set to delay the...

Page 1095: ...ssage is a data write read with sync message Data Trace Enabled The first data trace message after data trace has been enabled is a synchronization message Exit from Low Power Debug Upon exit from a l...

Page 1096: ...00z6 initiated read write accesses which fall inside or outside these address ranges as programmed are candidates to be traced 25 11 13 3 4 Data Access Instruction Access Data Tracing The Nexus3 modul...

Page 1097: ...ta Trace Timing Diagrams 8 MDO Configuration Figure 25 45 Data Trace Data Write Message e200z6 bus cycle accesses misaligned data across 64 bit boundary both 1st 2nd transactions within data trace ran...

Page 1098: ...essage Data Trace only encoded 00001110 11000000 01011001 11010001 00101000 00000000 01011100 MCKO MSEO 1 0 TCODE 14 Source Processor 0b0000 Data Size 000 Byte Full Access Address 0x0146_8ACE 00 MDO 7...

Page 1099: ...on watchpoint initialization When these watchpoints occur a watchpoint event signal from the Nexus1 module causes a message to be sent to the queue to be messaged out This message includes the watchpo...

Page 1100: ...out in the following format see Table 25 20 Figure 25 49 Error Message Format 25 11 14 4 Watchpoint Timing Diagram 2 MDO 1 MSEO Configuration Figure 25 50 Watchpoint Message Watchpoint Error Message 2...

Page 1101: ...Table 25 24 Configure the bits as follows Access Control RWCS AC 0b1 to indicate start access Map Select RWCS MAP 0b000 primary memory map Access Priority RWCS PR 0b00 lowest priority Read Write RWCS...

Page 1102: ...itialize the registers using a value of four doublewords for the CNT field and a RWCS SZ field indicating 64 bit access 2 Initialize the burst data buffer read write access data register through the a...

Page 1103: ...Y pin and sets the DV bit in the RWCS register This indicates that the device is ready for the next access 4 The data can then be read from the read write access data register RWD through the access m...

Page 1104: ...rt the RDY pin and the DV bit within the RWCS will be set to indicate the end of the block read access 8 The data can then be read from the burst data buffer read write access data register through th...

Page 1105: ...is terminated at the nearest completed access This method can be used to break early terminate block accesses 25 11 15 8 Read Write Access Error Message The read write access error message is sent ou...

Page 1106: ...0 0 0 0 0 0 I5 I4 I3 I2 0 1 End Packet 3 0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 1 End Packet End Message 4 X X S3 S2 S1 S0 T5 T4 T3 T2 T1 T0 0 0 Start of Next Message Table 25 39 Indirect Branch Messa...

Page 1107: ...address variable Dx Write data variable 8 16 or 32 bit Table 25 40 Direct Branch Message Example 12 MDO 2 MSEO Clock MDO 11 0 MSEO 1 0 State 11 10 9 8 7 6 5 4 3 2 1 0 0 X X X X X X X X X X X X 1 1 Idl...

Page 1108: ...r 7 1 UPDATE DR SELECT DR_SCAN 8 0 SELECT DR_SCAN CAPTURE DR Register value is transferred to Nexus shifter 9 0 CAPTURE DR SHIFT DR 10 0 31 TCK clocks issued to transfer register value to TDO pin whil...

Page 1109: ...13 Nexus Command write to read write access control status register RWCS 2 37 Write RWCS initialize write access mode and CNT value data input on TDI 3 13 Nexus Command write to read write address re...

Page 1110: ...auxiliary port and its specific signals such as MCKO MSEO 1 0 MDO 12 0 and others In actual use the MPC5553 MPC5554 NPC module arbitrates the access of the single auxiliary port To simplify the descri...

Page 1111: ...ection 25 7 2 2 1 Rules of Messages 25 13 2 Auxiliary Port Arbitration The NXDM module arbitrates for the shared Nexus port This arbitration is handled by the NPC See Section 25 5 based on prioritized...

Page 1112: ...1 BWA1 0x1E R W 0x3C 0x3D Breakpoint Watchpoint Address Register 2 BWA2 0x1F R W 0x3E 0x3F Reserved 0x20 0x3F 0x40 0x7E 0x41 0x7F 1 The CSC and PCR registers are shown in this table as part of the Nex...

Page 1113: ...8x system bus clock freq 28 27 EOC EVTO control 00 EVTO upon occurrence of watchpoint internal or external 01 EVTO upon entry into system level debug mode ipg_debug 1X Reserved 26 25 Reserved read as...

Page 1114: ...ration 00000000 No watchpoints trigger EVTO 1XXXXXXX Reserved X1XXXXXX Reserved XX1XXXXX Reserved XXX1XXXX Reserved XXXX1XXX Internal watchpoint 1 triggers EVTO XXXXX1XX Internal watchpoint 2 triggers...

Page 1115: ...Use internal watchpoint 1 BWA1 register 110 Use internal watchpoint 2 BWA2 register 111 Reserved 19 0 Reserved read as 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R RWT1 RWT2 0 0 0 0 0 0 0 0 W...

Page 1116: ...e on address outside of range endpoints exclusive 6 RC2 Range control 2 0 Condition trace on address within range endpoints inclusive 1 Condition trace on address outside of range endpoints exclusive...

Page 1117: ...it Value Range Selected DTSA or DTEA 0 DTSA DTEA DTSA or DTEA 1 DTSA DTEA DTSA DTEA N A Invalid range no trace 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R BWE1 BRW1 0 0 0 0 0 0 0 0 0 0 BWR1 W Re...

Page 1118: ...0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R BWT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25 60 Break Watchpoint Control Register 2 BWC2 Table 25 52 BW...

Page 1119: ...MP and system reset de assertion after the JTAG ID Register has been read by the tool 25 14 2 11 IEEE 1149 1 JTAG Test Access Port The NXDM module uses the IEEE 1149 1 TAP controller for accessing Nex...

Page 1120: ...er Access via JTAG Access to Nexus register resources is enabled by loading a single instruction NEXUS_ACCESS into the JTAG Instruction Register IR This IR is part of the IEEE 1149 1 TAP controller wi...

Page 1121: ...IR and then loading the corresponding OnCE OCMD register with the NEXUS_ACCESS instruction refer to Table 25 5 After it is enabled the module will be ready to accept control input via the JTAG pins Th...

Page 1122: ...6 TCODE Fixed TCODE number 8 4 4 SRC Fixed source processor identifier multiple Nexus configuration 5 5 ECODE Fixed error code refer to Table 25 56 Data Trace Data Write Message w Sync 6 6 TCODE Fixe...

Page 1123: ...nd attributes NOTE Data trace is ONLY performed on DMA accesses to the system bus 25 14 5 3 DTM Message Formats The NXDM block supports five types of DTM Messages data write data read data write synch...

Page 1124: ...01000 Error information is messaged out in the following format Figure 25 65 Error Message Format 25 14 5 3 3 Data Trace Synchronization Messages A data trace write read w sync Message is messaged vi...

Page 1125: ...r mode or debug mode the next data trace message will be converted to a data write read w sync message Queue Overrun An error message occurs when a new message cannot be queued due to the message queu...

Page 1126: ...addressing is the same as described for the NZ6C3 in Section 25 11 12 3 2 Relative Addressing 25 14 5 4 4 Data Trace Windowing Data write read messages are enabled via the RWT1 2 field in the data tra...

Page 1127: ...dicates the watchpoint number Figure 25 67 Watchpoint Message Format 25 14 6 2 Watchpoint Error Message An error message occurs when a new message cannot be queued due to the message queue being full...

Page 1128: ...pment tools to trace ownership flow 2 When the periodic 255 OTM message counter expires after 255 queued messages without an OTM an OTM will be sent The data will be sent from either the latched OTR d...

Page 1129: ...MPC5553 MPC5554 Microcontroller Reference Manual Rev 5 25 90 Freescale Semiconductor...

Page 1130: ...e A 25 Peripheral Bridge B PBRIDGE_B 0xFFF0_0000 Page A 35 System Bus Crossbar Switch XBAR 0xFFF0_4000 Page A 36 Error Correction Status Module ECSM 0xFFF4_0000 Page A 37 Enhanced Direct Memory Access...

Page 1131: ...latform peripheral access control register 1 PBRIDGE_A_OPACR1 32 bit Base 0x0044 Peripheral bridge A off platform peripheral access control register 2 PBRIDGE_A_OPACR2 32 bit Base 0x0048 Reserved Base...

Page 1132: ...alibration Option Register Bank 3 EBI_CAL_OR3 32 bit Base 0x005C Flash Module and Flash Bus Interface Unit FLASH 0xC3F8_8000 Chapter 13 Flash Memory Module configuration register FLASH_MCR 32 bit Base...

Page 1133: ...ration register 5 ADDR9 SIU_PCR5 16 bits Base 0x004A Pad configuration register 6 ADDR10 SIU_PCR6 16 bits Base 0x004C Pad configuration register 7 ADDR11 SIU_PCR7 16 bits Base 0x004E Pad configuration...

Page 1134: ...ase 0x0086 Pad configuration register 36 DATA8 SIU_PCR36 16 bits Base 0x0088 Pad configuration register 37 DATA9 SIU_PCR37 16 bits Base 0x008A Pad configuration register 38 DATA10 SIU_PCR38 16 bits Ba...

Page 1135: ..._PCR67 16 bits Base 0x00C6 Pad configuration register 68 OE SIU_PCR68 16 bits Base 0x00C8 Pad configuration register 69 TS SIU_PCR69 16 bits Base 0x00CA Pad configuration register 70 TA SIU_PCR70 16 b...

Page 1136: ...iguration register 100 PCSA4 SIU_PCR100 16 bits Base 0x0108 Pad configuration register 101 PCSA6 SIU_PCR101 16 bits Base 0x010A Pad configuration register 102 SCKB SIU_PCR102 16 bits Base 0x010C Pad c...

Page 1137: ...e 0x0146 Pad configuration register 132 ETPUA18 SIU_PCR132 16 bits Base 0x0148 Pad configuration register 133 ETPUA19 SIU_PCR133 16 bits Base 0x014A Pad configuration register 134 ETPUA20 SIU_PCR134 1...

Page 1138: ...0x0186 Pad configuration register 164 ETPUB17 SIU_PCR164 16 bits Base 0x0188 Pad configuration register 165 ETPUB18 SIU_PCR165 16 bits Base 0x018A Pad configuration register 166 ETPUB19 SIU_PCR166 16...

Page 1139: ...0x01C6 Pad configuration register 196 EMIOS17 SIU_PCR196 16 bits Base 0x01C8 Pad configuration register 197 EMIOS18 SIU_PCR197 16 bits Base 0x01CA Pad configuration register 198 EMIOS19 SIU_PCR198 16...

Page 1140: ...204 Pad configuration register 227 EVTO SIU_PCR227 16 bits Base 0x0206 Pad configuration register 228 TDO SIU_PCR228 16 bits Base 0x0208 Pad configuration register 229 CLKOUT SIU_PCR229 16 bits Base 0...

Page 1141: ...8 bits Base 0x061B GPIO pin data output register 28 SIU_GPDO28 8 bits Base 0x061C GPIO pin data output register 29 SIU_GPDO29 8 bits Base 0x061D GPIO pin data output register 30 SIU_GPDO30 8 bits Base...

Page 1142: ...8 bits Base 0x063B GPIO pin data output register 60 SIU_GPDO60 8 bits Base 0x063C GPIO pin data output register 61 SIU_GPDO61 8 bits Base 0x063D GPIO pin data output register 62 SIU_GPDO62 8 bits Base...

Page 1143: ...se 0x065B GPIO pin data output register 92 SIU_GPDO92 8 bits Base 0x065C GPIO pin data output register 93 SIU_GPDO93 8 bits Base 0x065D GPIO pin data output register 94 SIU_GPDO94 8 bits Base 0x065E G...

Page 1144: ...bits Base 0x067B GPIO pin data output register 124 SIU_GPDO124 8 bits Base 0x067C GPIO pin data output register 125 SIU_GPDO125 8 bits Base 0x067D GPIO pin data output register 126 SIU_GPDO126 8 bits...

Page 1145: ...bits Base 0x069B GPIO pin data output register 156 SIU_GPDO156 8 bits Base 0x069C GPIO pin data output register 157 SIU_GPDO157 8 bits Base 0x069D GPIO pin data output register 158 SIU_GPDO158 8 bits...

Page 1146: ...bits Base 0x06BB GPIO pin data output register 188 SIU_GPDO188 8 bits Base 0x06BC GPIO pin data output register 189 SIU_GPDO189 8 bits Base 0x06BD GPIO pin data output register 190 SIU_GPDO190 8 bits...

Page 1147: ...its Base 0x0804 GPIO pin data input register 5 SIU_GPDI5 8 bits Base 0x0805 GPIO pin data input register 6 SIU_GPDI6 8 bits Base 0x0806 GPIO pin data input register 7 SIU_GPDI7 8 bits Base 0x0807 GPIO...

Page 1148: ...8 bits Base 0x0824 GPIO pin data input register 37 SIU_GPDI37 8 bits Base 0x0825 GPIO pin data input register 38 SIU_GPDI38 8 bits Base 0x0826 GPIO pin data input register 39 SIU_GPDI39 8 bits Base 0...

Page 1149: ...8 bits Base 0x0844 GPIO pin data input register 69 SIU_GPDI69 8 bits Base 0x0845 GPIO pin data input register 70 SIU_GPDI70 8 bits Base 0x0846 GPIO pin data input register 71 SIU_GPDI71 8 bits Base 0...

Page 1150: ...864 GPIO pin data input register 101 SIU_GPDI101 8 bits Base 0x0865 GPIO pin data input register 102 SIU_GPDI102 8 bits Base 0x0866 GPIO pin data input register 103 SIU_GPDI103 8 bits Base 0x0867 GPIO...

Page 1151: ...bits Base 0x0884 GPIO pin data input register 133 SIU_GPDI133 8 bits Base 0x0885 GPIO pin data input register 134 SIU_GPDI134 8 bits Base 0x0886 GPIO pin data input register 135 SIU_GPDI135 8 bits Ba...

Page 1152: ...bits Base 0x08A4 GPIO pin data input register 165 SIU_GPDI165 8 bits Base 0x08A5 GPIO pin data input register 166 SIU_GPDI166 8 bits Base 0x08A6 GPIO pin data input register 167 SIU_GPDI167 8 bits Ba...

Page 1153: ...bits Base 0x08C4 GPIO pin data input register 197 SIU_GPDI197 8 bits Base 0x08C5 GPIO pin data input register 198 SIU_GPDI198 8 bits Base 0x08C6 GPIO pin data input register 199 SIU_GPDI199 8 bits Ba...

Page 1154: ...Input Output Subsystem eMIOS 0xC3FA_0000 Chapter 17 Enhanced Modular Input Output Subsystem eMIOS Module configuration register EMIOS_MCR 32 bit Base 0x0000 Global flag register EMIOS_GFR 32 bit Base...

Page 1155: ...0040 eTPU B time base 1 ETPU_TB1R_B2 32 bit Base 0x0044 eTPU B time base 2 ETPU_TB2R_B2 32 bit Base 0x0048 eTPU B STAC bus interface configuration register2 ETPU_REDCR_B2 32 bit Base 0x004C Reserved B...

Page 1156: ...SCR_A 32 bit Base 0x0404 eTPU A channel 0 host service request register ETPU_C0HSRR_A 32 bit Base 0x0408 Reserved Base 0x040C 0x040F eTPU A channel 1 configuration register ETPU_C1CR_A 32 bit Base 0x0...

Page 1157: ...U A channel 8 status and control register ETPU_C8SCR_A 32 bit Base 0x0484 eTPU A channel 8 host service request register ETPU_C8HSRR_A 32 bit Base 0x0488 Reserved Base 0x048C 0x048F eTPU A channel 9 c...

Page 1158: ...00 eTPU A channel 16 status and control register ETPU_C16SCR_A 32 bit Base 0x0504 eTPU A channel 16 host service request register ETPU_C16HSRR_A 32 bit Base 0x0508 Reserved Base 0x050C 0x050F eTPU A c...

Page 1159: ...0 eTPU A channel 24 status and control register ETPU_C24SCR_A 32 bit Base 0x0584 eTPU A channel 24 host service request register ETPU_C24HSRR_A 32 bit Base 0x0588 Reserved Base 0x058C 0x058F eTPU A ch...

Page 1160: ...U B channel 0 status and control register 2 ETPU_C0SCR_B2 32 bit Base 0x0804 eTPU B channel 0 host service request register 2 ETPU_C0HSRR_B2 32 bit Base 0x0808 Reserved Base 0x080C 0x080F eTPU B chann...

Page 1161: ...channel 8 status and control register 2 ETPU_C8SCR_B2 32 bit Base 0x0884 eTPU B channel 8 host service request register 2 ETPU_C8HSRR_B2 32 bit Base 0x0888 Reserved Base 0x088C 0088F eTPU B channel 9...

Page 1162: ...TPU B channel 16 status and control register 2 ETPU_C16SCR_B2 32 bit Base 0x0904 eTPU B channel 16 host service request register 2 ETPU_C16HSRR_B2 32 bit Base 0x0908 Reserved Base 0x090C 0x090F eTPU B...

Page 1163: ...eTPU B channel 24 status and control register 2 ETPU_C24SCR_B2 32 bit Base 0x0984 eTPU B channel 24 host service request register 2 ETPU_C24HSRR_B2 32 bit Base 0x0988 Reserved Base 0x098C 0x098F eTPU...

Page 1164: ...egister 2 ETPU_C31CR_B2 32 bit Base 0x09F0 eTPU B channel 31 status and control register 2 ETPU_C31SCR_B2 32 bit Base 0x09F4 eTPU B channel 31 host service request register 2 ETPU_C31HSRR_B2 32 bit Ba...

Page 1165: ...2 bit Base 0x0000 Reserved Base 0x0004 0x000F Slave general purpose control register 0 XBAR_SGPCR0 32 bit Base 0x0010 Reserved Base 0x0014 0x00FF Master priority register 1 XBAR_MPR1 32 bit Base 0x010...

Page 1166: ...Base 0x0047 Reserved Base 0x0048 0x0049 ECC error generation register ECSM_EEGR 16 bit Base 0x004A Reserved Base 0x004C 0x004F Flash ECC address register ECSM_FEAR 32 bit Base 0x0050 Reserved Base 0x...

Page 1167: ...01C Clear error register EDMA_CER 8 bit Base 0x001D Set START bit register EDMA_SSBR 8 bit Base 0x001E Clear DONE status bit register EDMA_CDSBR 8 bit Base 0x001F Interrupt request register high MPC55...

Page 1168: ...PR23 8 bit Base 0x0117 Channel priority register 24 EDMA_CPR24 8 bit Base 0x0118 Channel priority register 25 EDMA_CPR25 8 bit Base 0x0119 Channel priority register 26 EDMA_CPR26 8 bit Base 0x011A Cha...

Page 1169: ...it Base 0x0137 Channel priority register 56 EDMA_CPR56 8 bit Base 0x0138 Channel priority register 57 EDMA_CPR57 8 bit Base 0x0139 Channel priority register 58 EDMA_CPR58 8 bit Base 0x013A Channel pri...

Page 1170: ...t Base 0x12C0 Transfer control descriptor register 23 TCD23 256 bit Base 0x12E0 Transfer control descriptor register 24 TCD24 256 bit Base 0x1300 Transfer control descriptor register 25 TCD25 256 bit...

Page 1171: ...se 0x1680 Transfer control descriptor register 53 TCD53 256 bit Base 0x16A0 Transfer control descriptor register 54 TCD54 256 bit Base 0x16C0 Transfer control descriptor register 55 TCD55 256 bit Base...

Page 1172: ...register 1 INTC_PSR1 8 bit Base 0x0041 Priority select register 2 INTC_PSR2 8 bit Base 0x0042 Priority select register 3 INTC_PSR3 8 bit Base 0x0043 Priority select register 4 INTC_PSR4 8 bit Base 0x...

Page 1173: ..._PSR33 8 bit Base 0x0061 Priority select register 34 INTC_PSR34 8 bit Base 0x0062 Priority select register 35 INTC_PSR35 8 bit Base 0x0063 Priority select register 36 INTC_PSR36 8 bit Base 0x0064 Prio...

Page 1174: ..._PSR65 8 bit Base 0x0081 Priority select register 66 INTC_PSR66 8 bit Base 0x0082 Priority select register 67 INTC_PSR67 8 bit Base 0x0083 Priority select register 68 INTC_PSR68 8 bit Base 0x0084 Prio...

Page 1175: ...se 0x00A1 Priority select register 98 INTC_PSR98 8 bit Base 0x00A2 Priority select register 99 INTC_PSR99 8 bit Base 0x00A3 Priority select register 100 INTC_PSR100 8 bit Base 0x00A4 Priority select r...

Page 1176: ...R129 8 bit Base 0x00C1 Priority select register 130 INTC_PSR130 8 bit Base 0x00C2 Priority select register 131 INTC_PSR131 8 bit Base 0x00C3 Priority select register 132 INTC_PSR132 8 bit Base 0x00C4...

Page 1177: ...R161 8 bit Base 0x00E1 Priority select register 162 INTC_PSR162 8 bit Base 0x00E2 Priority select register 163 INTC_PSR163 8 bit Base 0x00E3 Priority select register 164 INTC_PSR164 8 bit Base 0x00E4...

Page 1178: ...R193 8 bit Base 0x0101 Priority select register 194 INTC_PSR194 8 bit Base 0x0102 Priority select register 195 INTC_PSR195 8 bit Base 0x0103 Priority select register 196 INTC_PSR196 8 bit Base 0x0104...

Page 1179: ...R225 8 bit Base 0x0121 Priority select register 226 INTC_PSR226 8 bit Base 0x0122 Priority select register 227 INTC_PSR227 8 bit Base 0x0123 Priority select register 228 INTC_PSR228 8 bit Base 0x0124...

Page 1180: ...R257 8 bit Base 0x0141 Priority select register 258 INTC_PSR258 8 bit Base 0x0142 Priority select register 259 INTC_PSR259 8 bit Base 0x0143 Priority select register 260 INTC_PSR260 8 bit Base 0x0144...

Page 1181: ...R289 8 bit Base 0x0161 Priority select register 290 INTC_PSR290 8 bit Base 0x0162 Priority select register 291 INTC_PSR291 8 bit Base 0x0163 Priority select register 292 INTC_PSR292 8 bit Base 0x0164...

Page 1182: ...C4 MAC Address Low Register PALR 32 bit Base 0x00E4 MAC Address Upper Register Type Field PAUR 32 bit Base 0x00E8 Opcode Pause Duration OPD 32 bit Base 0x00EC Upper 32 bits of Individual Hash Table IA...

Page 1183: ...t Base 0x0030 Result FIFO pop register 1 EQADC_RFPR1 32 bit Base 0x0034 Result FIFO pop register 2 EQADC_RFPR2 32 bit Base 0x0038 Result FIFO pop register 3 EQADC_RFPR3 32 bit Base 0x003C Result FIFO...

Page 1184: ...sfer counter register 2 EQADC_CFTCR2 16 bit Base 0x0094 CFIFO transfer counter register 3 EQADC_CFTCR3 16 bit Base 0x0096 CFIFO transfer counter register 4 EQADC_CFTCR4 16 bit Base 0x0098 CFIFO transf...

Page 1185: ...EQADC_CF4R0 32 bit Base 0x0200 CFIFO 4 register 1 EQADC_CF4R1 32 bit Base 0x0204 CFIFO 4 register 2 EQADC_CF4R2 32 bit Base 0x0208 CFIFO 4 register 3 EQADC_CF4R3 32 bit Base 0x020C Reserved Base 0x02...

Page 1186: ...32 bit Base 0x0404 RFIFO 4 register 2 EQADC_RF4R2 32 bit Base 0x0408 RFIFO 4 register 3 EQADC_RF4R3 32 bit Base 0x040C Reserved Base 0x0410 0x043F RFIFO 5 register 0 EQADC_RF5R0 32 bit Base 0x0440 RF...

Page 1187: ...Ix_CTAR7 32 bit Base 0x0028 Status register DSPIx_SR 32 bit Base 0x002C DMA interrupt request select and enable register DSPIx_RSER 32 bit Base 0x0030 Push TX FIFO register DSPIx_PUSHR 32 bit Base 0x0...

Page 1188: ...Base 0x0018 Reserved Base 0x001C 0xFFFB_3FFF A 0xFFFB_7FFF B FlexCAN2 Controller Area Network CANx 0xFFFC_0000 FlexCAN A 0xFFFC_4000 FlexCANB 2 0xFFFC_8000 FlexCAN C Chapter 22 FlexCAN2 Controller Ar...

Page 1189: ...Base 0x0100 Message buffer 9 MB9 16 bit Base 0x0110 Message buffer 10 MB10 16 bit Base 0x0120 Message buffer 11 MB11 16 bit Base 0x0130 Message buffer 12 MB12 16 bit Base 0x0140 Message buffer 13 MB13...

Page 1190: ...ssage buffer 40 MB40 16 bit Base 0x0300 Message buffer 41 MB41 16 bit Base 0x0310 Message buffer 42 MB42 16 bit Base 0x0320 Message buffer 43 MB43 16 bit Base 0x0330 Message buffer 44 MB44 16 bit Base...

Page 1191: ...r to optimize code portability to other members of the eSys MPU family use of the watchdog registers in the ECSM is not recommended 2 MPC5554 Only Table A 3 e200z6 Core SPR Numbers Supervisor Mode Reg...

Page 1192: ...IVOR5 Interrupt Vector Offset Register 5 405 IVOR6 Interrupt Vector Offset Register 6 406 IVOR7 Interrupt Vector Offset Register 7 407 IVOR8 Interrupt Vector Offset Register 8 408 IVOR9 Not Supported...

Page 1193: ...egister 304 DBCNT Debug Counter Register 562 IAC1 Instruction Address Compare Register 1 312 IAC2 Instruction Address Compare Register 2 313 IAC3 Instruction Address Compare Register 3 314 IAC4 Instru...

Page 1194: ...eral Registers CTR Count Register 9 LR Link Register 8 XER Integer Exception Register 1 GPR0 GPR31 General Purpose Registers N A Special Purpose Registers SPRG4 Special Purpose Register 4 260 SPRG5 Sp...

Page 1195: ...hanges to MPC5553 5554RM for Rev 4 0 Release Description of Change No changes since the 3 1 release Table A 6 Changes to MPC5553 5554RM for Rev 5 0 Release Description of Change Changed instances of P...

Page 1196: ...iled in Figure B 1 Freescale produced VertiCal bases use the calibration assembled MPC5500 device mounted on a small circuit board with a footprint which is compatible with that of the production BGA...

Page 1197: ...op Board VertiCal Base Application Production PCB VertiCal Connector System Calibration Packaged MPC5500 Device Production packaged sized 23mm 324 BGA calibration board production package compatible f...

Page 1198: ...s In the MPC5553 the calibration chip selects CAL_CS n have a higher priority in address decoding than the non calibration chip selects CS n Refer to Section B 6 Application Information for applicatio...

Page 1199: ...dge TA_ GPIO 70 TA_ GPIO 70 CAL_WE BE 0 1 Write Byte Enable WE BE 2 3 3 _ CAL_WE BE 0 1 _ GPIO 66 67 WE BE 0 1 _ GPIO 64 65 Clock Synthesizer 1 CLKOUT System Clock Output CLKOUT CLKOUT 1 The BR and BG...

Page 1200: ...uration Register for that pin B 3 2 MPC5553 Calibration Bus Implementation The MPC5553 device is similar to the MPC5554 in that no signals are dedicated for calibration usage Instead signals that are...

Page 1201: ...n 6 3 1 12 35 MPC5553 Pad Configuration Register 73 SIU_PCR73 on page 6 50 CLKOUT Section 6 3 1 12 115 Pad Configuration Register 229 SIU_PCR229 on page 6 91 For MPC5554 see Address Bus pins Section 6...

Page 1202: ...n For this application an SRAM top board is added onto the VertiCal connector This allows the engine calibrator to modify settings in SRAM possibly using the Nexus interface or even by using the eSCI...

Page 1203: ...on chip selects CAL_CS n have a higher priority in address decoding than the non calibration chip selects CS n Changed CS1 to CAL_CS1 in the last paragraph of Section B 2 Calibration Bus Table B 1 Add...

Page 1204: ...tion Unit SIU In Section 6 3 1 12 61 Pad Configuration Register 105 SIU_PCR105 rephrased footnote 1 to the following When configured as PCSB 0 the OBE bit has no effect When configured as PCSD 2 set t...

Page 1205: ...ill be generated In Section 10 5 5 2 Ensuring Coherency moved the text in Section 10 5 5 2 Ensuring Coherency under a new Section 10 5 5 2 1 Interrupt with Blocked Priority Added a new Section 10 5 5...

Page 1206: ...o 31 RT clock cycles in the following sections PBERR bit description in Table 21 6 Section 21 4 9 2 14 PBERR Description Section 21 4 10 4 LIN Error Handling Appendix A MPC5553 MPC 5554 Register Map C...

Page 1207: ...Revision History 4 Freescale Semiconductor...

Page 1208: ...ication or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Fr...

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