MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor
17-61
It is important to note that, like in OPWMB and OPWFMB modes, the match signal used to set or clear
the channel output flip-flop is generated on the negation of the channel comparator output signal which
compares the selected time base with A1 or B1. Refer to
, which illustrates the delay from
matches to output flip-flop transition in OPWFMB mode.
17.4.4.4.18 Output Pulse Width Modulation, Buffered Mode (OPWMB) (MPC5553 Only)
OPWMB mode is used to generate pulses with programmable leading and trailing edge placement. An
external counter is selected from one of the counter buses. The A1 register value defines the first edge and
B1 defines the second edge. The output signal polarity is defined by the EDPOL bit. If EDPOL is zero, a
negative edge occurs when A1 matches the selected counter bus and a positive edge occurs when B1
matches the selected counter bus.
The A1 and B1 registers are double buffered and updated from A2 and B2, respectively, at the cycle
boundary. The load operation is similar to the OPWFMB mode. Refer to
for more
information on A1 and B1 register updates.
Flags are generated at B1 matches when MODE[5] is cleared, or on both A1 and B1 matches when
MODE[5] is set. If subsequent matches occur on comparators A and B, the PWM pulses continue to be
generated regardless of the state of the FLAG bit.
The FORCMA and FORCMB bits allow software to force the output flip-flop to the level corresponding
to a match on A1 or B1 respectively. FLAG is not set by the FORCMA and FORCMB operations.
The following rules apply to the OPWMB mode:
•
B1 matches have precedence over A1 matches if they occur at the same time within the same
counter cycle.
•
A1 = 0 match from cycle (
n
) has precedence over a B1 match from cycle (n-1).
•
A1 matches are masked if they occur after a B1 match within the same cycle.
•
Values written to A2 or B2 on cycle (
n
) are loaded to A1 or B1 at the following cycle boundary
(assuming EMIOS_OUDR[
n
] is not asserted). Thus the new values will be used for A1 and B1
matches in cycle (
n
+1).
illustrates operation in OPWMB mode with A1/B1 matches and the transition of the channel
output flip-flop. In this example EDPOL is zero.
Table 17-31. Mode of Operation: OPWMB Mode
MODE[0:6]
Unified Channel Mode of Operation
0b1100000
Output pulse width modulation, buffered
(FLAG set on second match)
0b1100001
Reserved
0b1100010
Output pulse width modulation, buffered
(FLAG set on both matches)
Summary of Contents for MPC5553
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