MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor
2-21
2
Each line in the signal name column corresponds to a separate signal function on the pin. For all device I/O pins, the primary, alternate, or GPIO signal
functions are designated in the PA field of the system integration unit (SIU) PCR registers except where explicitly noted.
3
V
DDE
(fast I/O) and V
DDEH
(slow I/O) power supply inputs are grouped into segments. Each segment of V
DDEH
pins can connect to a separate
3.3–5.0 V (
5%/–10%) power supply input. Each segment of V
DDE
pins can connect to a separate 1.8–3.3 V (
10%) power supply, with the exception of the
V
DDE2
and V
DDE3
segments that are shorted together and must use the same power supply input. This segment is labeled V
DDE2
in the BGA map.
for a definition of the I/O pins that are powered by each segment.
4
The pad type is indicated by one of the abbreviations; F for fast, MH for medium (high voltage), SH for slow (high voltage), A for analog, AE for analog with
ESD protection circuitry. Some pads may have two types, depending on which pad function is selected.
5
The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. Terminology is O — output,
I — input, up — weak pullup enabled, down — weak pulldown enabled, low — output driven low, high — output driven high. A dash on the left side of the
slash denotes that both the input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled
on the pin. The signal name to the left or right of the slash indicates the pin is enabled.
6
F
unction after reset of GPI is general-purpose input. A dash on the left side of the slash denotes that both the input and output buffers for the pin are off. A
dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin.
7
The 496 assembly is only available as an internal component of the 416, 324, and 208 VertiCal base devices and is not available directly to customers.
8
The calibration signal functions are not available on the 416 package because it does not have a calibration bus. The fast Ethernet controller (FEC) signals
are available on the 416 package as alternate functions muxed with the primary EBI signal functions.
9
Availability currently not planned. Consult factory for availability.
10
BOOTCFG[0] is not available and will always be read as 0 in the 208 package of the MPC5553.
11
The EBI is specified and tested at 1.8 V and 3.3 V.
12
The 32-bit external bus interface (EBI) can be configured as: a 32-bit external I/O data bus for the EBI; a 16-bit external I/O data bus for the EBI which uses
the lower 16-bits, and a 16-bit FEC, which uses the upper 16-bits; and the calibration bus interface (CBI), which uses 21 address pins [10:30] and 16 data
pins [0:15].
13
Do not configure both the primary function in ADDR[8:11]_GPIO[4:7] and the secondary function in CS[0:3]_ADDR[8:11]_GPIO[0:3] pins as input. Only
configure one set of pins for the address input.
14
When using the EBI functions, select the function in the SIU_PCR register and enable the EBI functions in the EBI for these pins. Both the SIU and EBI
configurations must match for proper operation.
15
The function and state of these pins after execution of the BAM (Boot Assist Module) program is determined by the BOOTCFG[1:0] pins. Refer to
for detail on the EBI configuration after execution of the BAM program.
16
Because the CBI and the EBI share the same bus, the CBI uses EBI signals ADDR[12:26] in addition to the CAL_ADDR[10:11, 27:30] signals for calibration
addressing. Set the PA field in the SUI_PCR register to 0b1 to use the CBI or EBI.
17
V
DDE3
and V
DDE2
are shorted together in this device.
18
Because the CBI and the EBI share the same external bus, RD_WR is used for both the CBI and the EBI.
19
The function for the WE/BE[0:1]_GPIO[64:65] and WE/BE[2:3]_CAL_WE/BE[0:1]_GPIO[66:67] pins is specified in the SIU. When configured for EBI, the
write enable or byte enable operation is specified in the EBI_BR0 through EBI_BR3 registers. When configured for the Calibration bus, the write enable or
byte enable operation is specified in the EBI_CAL_BR0 through EBI_CAL_BR3 registers for each chip select region.
20
Because the CBI and the EBI share the same external bus, OE is used for both the CBI and the EBI.
21
Because the CBI and the EBI share the same external bus, TS is used for both the CBI and the EBI.
22
The BR and BG functions are not implemented on the MPC5553 and are replaced by FEC and calibration functions. The pin name on the ball map, however,
does remain BR and BG. The primary functions for these pins are CAL_ADDR[10] and CAL_ADDR[11], respectively.
23
MCKO is only enabled if debug mode is enabled. Debug mode can be enabled before or after exiting System Reset (RSTOUT negated).
24
MDO[0] is driven high following a power-on-reset (POR) until the system clock achieves lock, at which time it is then negated. There is an internal pull up on
MDO[0].
25
The function of the MDO[11:4]_GPIO[82:75] pins is selected during a debug port reset by the EVTI pin or by selecting FPM in the NPC_PCR. When
functioning as MDO[11:4] the pad configuration specified by the SIU does not apply. Refer to
Section 2.3.4.5, “Nexus Message Data Out / GPIO
” for more detail on MDO[11:4] pin operation.
26
The pullup on TDO is functional only when not in JTAG mode (JCOMP negated).
27
The function and state of the FlexCAN A and eSCI A pins after execution of the BAM program is determined by the BOOTCFG[0:1] pins. Refer to
for details on the FlexCAN A and eSCI A pin configurations after execution of the BAM program.
28
The primary signal is not available on this device and is listed only for reference to the pin label in the BGA map.
29
To allow one DSPI to operate at a different operating voltage than another DSPI, connect V
DDEH6
and V
DDEH10
to separate power supplies. However,
connecting V
DDEH6
and V
DDEH10
to separate power supplies is not compatible with the MPC5554.
30
For compatibility to the MPC5554, power V
DDEH6
and V
DDEH10
from the same power supply (3–5.25 V).
31
All analog input channels are connected to both ADC blocks. The supply designation for this pin(s) specifies only the ESD rail used.
32
Because the primary signal function designations for the analog functions AN[12] through AN[15] are internally reserved, the PA field of the corresponding
SIU_PCR registers must be set to the main primary function value of 0b011 to use analog functions AN[12] through AN[15].
33
To use the serial data strobe functions, the PA field in the SIU_PCR registers must be set to 0b00. Because SDS, SDO, SDI, and FCK use the GPIO setting,
a G is shown in the P/A/G column. However, these signals do not support true GPIO functionality.
34
If analog features are used, tie V
DDEH9
to V
DDA1
.
35
Because other balls are already named EMIOS[14:15] on the BGA map, the ball names used for these signals are named GPIO[203:204].
36
The GPIO[205] pin is a protect-for pin for configuring an external boot for a double data rate memory.
37
The GPIO[206:207] pins are protect-for pins for double data rate memory data strobes. These pins can source the ADC trigger in SIU_ETISR.
Summary of Contents for MPC5553
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