MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
25-80
Freescale Semiconductor
25.14.2.8 Breakpoint/Watchpoint Address Registers 1 and 2 (BWA1 and BWA2)
The breakpoint/watchpoint address registers are compared with bus addresses in order to generate internal
watchpoints.
25.14.2.9 Unimplemented Registers
Unimplemented registers are those with client select and index value combinations other than those listed
in
. For unimplemented registers, the NXDM module will drive TDO to zero during the
“SHIFT-DR” state. It will also transmit an error message with the invalid access opcode encoding.
25.14.2.10 Programming Considerations (RESET)
If Nexus3 register configuration is to occur during system reset (as opposed to debug mode), all NXDM
configuration should be completed between the negation of JCOMP and system reset de-assertion, after
the JTAG ID Register has been read by the tool.
25.14.2.11 IEEE
1149.1 (JTAG) Test Access Port
The NXDM module uses the IEEE
1149.1
TAP controller for accessing Nexus resources. The JTAG
signals themselves are shared by all TAP controllers on the device. Refer to
Access Port Controller (JTAGC)
for more information on the JTAG interface.
The NXDM module implements a 4-bit instruction register (IR). The valid instructions and method for
register access are outlined in
.
15
BWT2
Breakpoint/watchpoint #2 Type
0 Reserved
1 Watchpoint #2 on data accesses
14–0
–
Reserved, read as 0.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
BREAKPOINT / WATCHPOINT ADDRESS
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
BREAKPOINT / WATCHPOINT ADDRESS
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 25-61. Breakpoint / Watchpoint Address Registers (BWA1, BWA2)
Table 25-52. BWC2 Field Description (Continued)
Bit
Name
Description
Summary of Contents for MPC5553
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