MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor
18-7
In the host address space each parameter occupies four bytes (32 bits). eTPU usage of the upper byte is
achieved by having a 32-bit Preload (P) register that can access the upper byte, the lower 24 bits, or all the
32 bits. The microcode can switch between access sizes at any time.
Each function may require a different number of parameters. During the eTPU initialization the host has
to program channel base addresses, allocating proper parameters for each channel according to its selected
function.
18.1.3.1.5
Task
Scheduler
As mentioned in
Section 18.1.3, “eTPU Operation Overview
” every channel function is composed of one
or more threads, and threads cannot be interrupted by host or channel events, such as channel servicing.
The function of the task scheduler, therefore, is to recognize and prioritize the channels needing service
and grant execution time to each channel. The time given to an individual thread for execution or service
is called a time slot. The duration of a time slot is determined by the number of instructions executed in
the thread plus SDM wait-states received, and varies in length. Although several channels may request
service at the same time, the function threads must be executed serially.
At any time, an arbitrary number of channels can require service. The channel logic, eTPU microcode, or
the host application notifies the scheduler by issuing a service request.
Out of reset, all channels are disabled. The MPC5553/MPC5554 core makes a channel active by assigning
it one of three priorities: high, middle, or low. The scheduler determines the order in which channels are
serviced based on channel number and assigned priority. The priority mechanism, implemented in
hardware, ensures that all requesting channels are serviced.
18.1.3.1.6
Microengine
The eTPU microengine is a simple RISC implementation that performs each instruction in a microcycle
of two system clocks, while pre-fetching the next instruction through an instruction pipeline. Instruction
execution time is constant for the arithmetic logic unit (ALU) unless it gets wait states from SDM
arbitration.
Microcode is stored in shared code memory (SCM) that is 32 bits wide. The microengine instruction set
provides basic arithmetic and logic operations, flow control (jumps and subroutine calls), SDM access, and
channel configuration and control. The instruction formats are defined in such a way that allow particular
combinations of two or three of these operations with unconflicting resources to be executed in parallel in
the same microcycle, thus improving performance.
The microengine also has an independent multiply/divide/MAC unit that performs these complex
operations in parallel with other microengine instructions.
Channel functionality is integrated to the instruction set through channel control operations and
conditional branch operations, which support jumps/calls on channel-specific conditions. This allows
quick and terse channel configuration and control code, contributing to reduced service time.
18.1.3.1.7
Dual eTPU Engine System (MPC5554 Only)
The MPC5554 eTPU implementation includes two eTPU engines sharing SDM and the same code in the
SCM.
The two eTPU engines share the bus interface unit (BIU) and the shared data memory (SDM). This allows
the MPC5554 core to communicate with the eTPU and also provides a means of communication between
the eTPU engines. The shared BIU includes coherency logic which supports dual parameter (8 bytes)
coherency in transfers between the host and eTPU, using a temporary parameter area within the SDM. This
is applicable to single eTPU engine systems as well.
Summary of Contents for MPC5553
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