MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor
21-37
NOTE
LIN 2.0 now requires that a break character is always 13 bits long, so the
BRK13 bit should always be set to 1. The eSCI will work with BRK13=0,
but it will violate LIN 2.0.
The application software can decide to turn off the checksum generation/verification on a per frame basis
and handle that function on its own. The application software can also decide to let the LIN hardware
append two CRC bytes (
). The CRC bytes are not part of the LIN standard, but could be part
of the application layer, that is they would be treated as data bytes by the LIN protocol. This can be useful
when very long frames are transmitted. By default the CRC polynomial used is the same polynomial as for
the CAN protocol.
Figure 21-24. LIN Frame with CRC bytes
It is possible to force a resync of the LIN FSM, with the LRES bit in the LIN control register. However,
under normal circumstances, the LIN hardware will automatically abort a frame after detecting a bit error.
21.4.10.2 Generating a TX Frame
The following procedure describes how a basic TX frame is generated.
The frame is controlled via the LIN transmit register (ESCI
x
_LTR). Initially, the application software will
need to check the TXRDY bit (either using an interrupt, the TX DMA interface, or by polling the LIN
status register). If TXRDY is set, the register is writable. Before each write, TXRDY must be checked
(though this step is performed automatically in DMA mode). The first write to the ESCI
x
_LTR must
contain the LIN ID field. The next write to ESCI
x
_LTR specifies the length of the frame (0 to 255 Bytes).
The third write to ESCI
x
_LTR contains the control byte (frame direction, checksum/CRC settings). Note
that timeout bits are not included in TX frames, because they only refer to LIN slaves. The three previously
mentioned writes to the ESCI
x
_LTR specify the LIN frame data. After the LIN frame data is specified, the
eSCI LIN hardware starts to generate a LIN frame.
First, the eSCI transmits a break field. The sync field is transmitted next. The third field is the ID field.
After these three fields have been broadcast, the ESCIx_LTR accepts data bytes; the LIN hardware
transmits these data bytes as soon as they are available and can be sent out. After the last step the LIN
hardware automatically appends the checksum field.
It is possible to set up a DMA channel to handle all the tasks required to send a TX frame. (See
for more information.) For this operation, the TX DMA channel must be activated by setting
the ESCI
x
_CR2[TXDMA] bit. The control information for the LIN frame (ID, message length, TX/RX
type, timeout, etc.) and the data bytes are stored at an appropriate memory location. The DMA controller
is then set up to transfer this block of memory to a location (the ESCI
x
_LTR). After transmission is
complete, either the DMA controller or the LIN hardware can generate an interrupt to the CPU.
NOTE
In contrast to the standard software implementation where each byte
transmission requires several interrupts, the DMA controller and eSCI
handle communication, bit error and physical bus error checking,
checksum, and CRC generation (checking on the RX side).
Break
Sync
ID
Data
Data
CRC1
CRC2
CSum
• • •
Summary of Contents for MPC5553
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