MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
9-28
Freescale Semiconductor
225–230 /
0x1C [1:6]
BITER
[0:5]
or
BITER.LINKCH[
0:5]
Starting “major” iteration count or link channel number.
If channel-to-channel linking is disabled (TCD.BITER.E_LINK = 0), then
• No channel-to-channel linking (or chaining) is performed after the inner minor
loop is exhausted. TCD bits [225:239] are used to form a 15-bit BITER field.
Otherwise
• After the minor loop is exhausted, the eDMA engine initiates a channel service
request at the channel, defined by BITER.LINKCH[0:5], by setting that channel’s
TCD.START bit.
Note: When the TCD is first loaded by software, this field must be set equal to the
corresponding CITER field, otherwise a configuration error will be reported. As the
major iteration count is exhausted, the contents of this field is reloaded into the
CITER field.
231–239 /
0x1C [7:15]
BITER
[6:14]
Starting major iteration count. As the transfer control descriptor is first loaded by
software, this field must be equal to the value in the CITER field. As the major
iteration count is exhausted, the contents of this field is reloaded into the CITER
field.
Note: If the channel is configured to execute a single service request, the initial
values of BITER and CITER should be 0x0001.
240–241 /
0x1C [16:17]
BWC
[0:1]
Bandwidth control. This two-bit field provides a mechanism to effectively throttle the
amount of bus bandwidth consumed by the eDMA. In general, as the eDMA
processes the inner minor loop, it continuously generates read/write sequences
until the minor count is exhausted. This field forces the eDMA to stall after the
completion of each read/write access to control the bus request bandwidth seen by
the system bus crossbar switch (XBAR).
To minimize start-up latency, bandwidth control stalls are suppressed for the first
two system bus cycles and after the last write of each minor loop.
00 No eDMA engine stalls
01 Reserved
10 eDMA engine stalls for 4 cycles after each r/w
11 eDMA engine stalls for 8 cycles after each r/w
242–247 /
0x1C [18:23]
MAJOR.LINKC
H
[0:5]
Link channel number.
If channel-to-channel linking on major loop complete is disabled
(TCD.MAJOR.E_LINK = 0) then
• No channel-to-channel linking (or chaining) is performed after the outer major
loop counter is exhausted.
Otherwise
• After the major loop counter is exhausted, the eDMA engine initiates a channel
service request at the channel defined by MAJOR.LINKCH[0:5] by setting that
channel’s TCD.START bit.
248 /
0x1C [24]
DONE
Channel done. This flag indicates the eDMA has completed the outer major loop. It
is set by the eDMA engine as the CITER count reaches zero; it is cleared by
software or hardware when the channel is activated (when the channel has begun
to be processed by the eDMA engine, not when the first data transfer occurs).
Note: This bit must be cleared in order to write the MAJOR.E_LINK or E_SG bits.
249 /
0x1C [25]
ACTIVE
Channel active. This flag signals the channel is currently in execution. It is set when
channel service begins, and is cleared by the eDMA engine as the inner minor loop
completes or if any error condition is detected.
Table 9-18. TCDn Field Descriptions (Continued)
Bits /
Word Offset [n:n]
Name
Description
Summary of Contents for MPC5553
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