System Interface Unit (SIU)
MPC5553/MPC5554 Microcontroller Reference Manual,
Rev. 5
6-92
Freescale Semiconductor
6.3.1.12.116 Pad Configuration Register 230 (SIU_PCR230)
The SIU_PCR230 register controls the slew rate of the RSTOUT pin.
Figure 6-128. RSTOUT Pad Configuration Register (SIU_PCR230)
Refer to
for bit field definitions.
6.3.1.13
GPIO Pin Data Output Registers 0–213 (SIU_GPDOn)
The definition of the 8-bit SIU_GPDO
n
registers, with each register specifying the drive data for a single
GPIO pin, is given in
. The
n
notation in the name of the 214 SIU_GPDO
n
registers
corresponds to the pins with the same GPIO pin numbers. For example, PDO0 is the pin data output bit
for the CS[0]_GPIO[0] pin and is found in SIU_GPDO0, and PDO213 is the pin data output bit for the
WKPCFG_GPIO[213] pin and is found in SIU_GPDO213. The GPDO address for a particular pin is equal
to the GPIO pin number with an offset of SI 0x0600.
The SIU_GPDO
n
registers are written to by software to drive data out on the external GPIO pin. Each
register drives a single external GPIO pin, which allows the state of the pin to be controlled independently
from other GPIO pins. Writes to the SIU_GPDO
n
registers have no effect on pin states if the pins are
configured as inputs by the associated pad configuration registers. The SIU_GPDO[
n
] register values are
automatically driven to the GPIO pins without software update if the direction of the GPIO pins is changed
from input to output.
Writes to the SIU_GPDO
n
registers have no effect on the state of the corresponding pins when the pins
are configured for their primary function by the corresponding PCR.
Address: Base + 0x020C
Access: Read / write[12:13]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
0
0
SRC
0
0
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
Address: Base + n
Access: Read / write[7]
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
PDOn
Reset
0
0
0
0
0
0
0
0
Figure 6-129. GPIO Pin Data Output Register 0–213 (SIU_GPDOn)
Summary of Contents for MPC5553
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