MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
19-100
Freescale Semiconductor
a transmission operation becomes the output data for the slave, and data in the master receive shift register
after a transmission operation is the input data from the slave.
Figure 19-56. Full-Duplex Pin Connection
19.4.8.1
eQADC SSI Data Transmission Protocol
shows the timing of an eQADC SSI transmission operation. The main characteristics of this
protocol are the following:
•
FCK is free running, it does not stop between data transmissions. FCK will be driven low:
— When the serial interface is disabled
— In stop/debug mode
— Immediately after reset
•
Frame size is fixed to 26 bits.
•
Msb bit is always transmitted first.
•
Master drives data on the positive edge of FCK and latches incoming data on the next positive edge
of FCK.
•
Slave drives data on the positive edge of FCK and latches incoming data on the negative edge of
FCK.
Master initiates a data transmission by driving SDS low, and its msb bit on SDO on the positive edge of
FCK. After an asserted SDS is detected, the slave shifts its data out, one bit at a time, on every FCK
positive edge. Both the master and the slave drive new data on the serial lines on every FCK positive edge.
This process continues until all the initial 26-bits in the master shift register are moved into the slave shift
register. t
DT
is the delay between two consecutive serial transmissions, time during which SDS is negated.
When ready to start of the next transmission, the slave must drive the msb bit of the message on every
positive edge of FCK regardless of the state of the SDS signal. On the next positive edge, the second bit
of the message is conditionally driven according to if an asserted SDS was detected by the slave on the
preceding FCK negative edge. This is an important requisite because the SDS and the FCK are not
synchronous. The SDS signal is not generated by FCK, rather both are generated by the system clock, so
that it is not guaranteed that FCK edges will precede SDS edges. While SDS is negated, the slave
continuously drives its msb bit on every positive edge of FCK until it detects an asserted SDS on the
immediately next FCK negative edge. See
for three situations showing how the slave should
behave according to when SDS is asserted.
Transmit Shift Register
Receive Shift Register
Data Registers
Receive Shift Register
Transmit Shift Register
CFIFOs & RFIFOs
SDI
SDO
FCK
SDS
Baud Rate
Generator
Master
Slave
Summary of Contents for MPC5553
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