MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
19-84
Freescale Semiconductor
•
Ignores the data in case of a null or “reserved for customer use” MESSAGE_TAG
In general, received data is moved into RFIFOs as they become available, while an exception happens
when multiple results from different sources become available at the same time. In that case, result data
from ADC0 is processed first, result data from ADC1 is only processed after all ADC0 data is processed,
and result data from the external device is only processed after all data from ADC0/1 is processed.
When time-stamped results return from the on-chip ADCs, the conversion result and the time stamp are
always moved to the RFIFOs in consecutive clock cycles in order to guarantee they are always stored in
consecutive RFIFO entries.
19.4.5
On-Chip ADC Configuration and Control
19.4.5.1
Enabling and Disabling the on-chip ADCs
The on-chip ADCs have an enable bit (ADC0_CR[ADC0_EN] and ADC1_CR[ADC1_EN], see Section
19.3.3.1) which allows the enabling of the ADCs only when necessary. When the enable bit for an ADC
is negated, the clock input to that ADC is stopped. The ADCs are disabled out of reset - ADC0/1_EN bits
are negated - to allow for their safe configuration. The ADC must only be configured when its enable bit
is negated. After the enable bit of an ADC is asserted, clock input is started, and the bias generator circuit
is turned on. When the enable bits of both ADCs are negated, the bias circuit generator is stopped.
NOTE
Conversion commands sent to a disabled ADC are ignored by the ADC
control hardware.
NOTE
NOTE
An 8ms wait time from V
DDA
power up to enabling ADC is required to pre-charge the external
100nf capacitor on REFBYPC. This time must be guaranteed by crystal startup time plus reset duration or
the user. The ADC internal bias generator circuit will start up after 10us upon VRH/VRL power up and
produces a stable/required bias current to the pre-charge circuit, but the current to the other analog circuits
are disabled until ADCs are enabled. As soon as the ADCs are enabled, the bias currents to other analog
circuits will be ready.
Because of previous design versions, the EQADC will always wait 120
ADC clocks before issuing the first conversion command following the
enabling of one of on-chip ADCs, or the exiting of stop mode. There are two
independent counters checking for this delay: one clocked by ADC0_CLK
and another by ADC1_CLK. Conversion commands can start to be executed
whenever one of these counters completes counting 120 ADC clocks.
19.4.5.2
ADC Clock and Conversion Speed
The clock input to the ADCs is defined by setting the ADC0_CR[ADC0_CLK_PS] and
ADC1_CR[ADC1_CLK_PS] fields (see Section 19.3.3.1) The ADC0/1_CLK_PS field selects the clock
divide factor by which the system clock will be divided as showed in
frequency is calculated as below and it must not exceed 12 MHz.
Summary of Contents for MPC5553
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