MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
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Freescale Semiconductor
set the transfer attributes. Transfer attribute control is on a frame by frame basis. See
“Serial Peripheral Interface (SPI) Configuration
” for more details.
In DSI configuration, master mode transfer attributes are controlled by the DSPI
x
_DSCIR. A detailed
description of the DSPI
x
_DSCIR is located in
Section 20.3.2.10, “DSPI DSI Configuration Register
.” The DSISCTAS field in the DSPI
x
_DSICR selects which of the DSPI
x
_CTARs will be
used to set the transfer attributes. Transfer attributes are set up during initialization and must not be
changed between frames. See
Section 20.4.4, “Deserial Serial Interface (DSI) Configuration
,” for more
details.
The CSI configuration is only available in master mode. In CSI configuration, the DSI data is transferred
using DSI configuration transfer attributes and SPI data is transferred using the SPI configuration transfer
attributes. In order for the bus slave to distinguish between DSI and SPI frames, the transfer attributes for
the two types of frames must utilize different peripheral chip select signals. See
Serial Interface (CSI) Configuration
,” for details.
20.4.1.2
Slave Mode
In slave mode the DSPI responds to transfers initiated by an SPI master. The DSPI operates as bus slave
when the MSTR bit in the DSPI
x
_MCR is negated. The DSPI slave is selected by a bus master by having
the slave’s SS asserted. In slave mode the SCK is provided by the bus master. All transfer attributes are
controlled by the bus master but clock polarity, clock phase and numbers of bits to transfer must still be
configured in the DSPI slave for proper communications.
The SPI and DSI configurations are valid in slave mode. CSI configuration is not available in slave mode.
In SPI slave mode the slave transfer attributes are set in the DSPI
x
_CTAR0. In DSI slave mode the slave
transfer attributes are set in the DSPI
x
_CTAR1. In slave mode, for both SPI and DSI configurations, data
is transferred MSB first. The LSBFE field of the associated CTAR is ignored.
20.4.1.3
Module Disable Mode
The module disable mode is used for MCU power management. The clock to the non-memory mapped
logic in the DSPI is stopped while in module disable mode. The DSPI enters the module disable mode
when the MDIS bit in DSPI
x
_MCR is set. See
Section 20.4.10, “Power Saving Features
on the module disable mode.
20.4.1.4
Debug Mode
The debug mode is used for system development and debugging. If the MPC5553/MPC5554 enters debug
mode while the FRZ bit in the DSPI
x
_MCR is set, the DSPI stops all serial transfers and enters a stopped
state. If the MPC5553/MPC5554 enters debug mode while the FRZ bit is negated, the DSPI behavior is
unaffected and remains dictated by the module-specific mode and configuration of the DSPI. The DSPI
enters debug mode when a debug request is asserted by an external controller. See
for a state
diagram.
20.4.2
Start and Stop of DSPI Transfers
The DSPI has two operating states; STOPPED and RUNNING. The states are independent of DSPI
configuration. The default state of the DSPI is STOPPED. In the STOPPED state no serial transfers are
initiated in master mode and no transfers are responded to in slave mode. The STOPPED state is also a
safe state for writing the various configuration registers of the DSPI without causing undetermined results.
The TXRXS bit in the DSPI
x
_SR is negated in this state. In the RUNNING state, serial transfers take
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